CN114356014A - Low-voltage reference voltage generating circuit and chip - Google Patents

Abstract

The invention discloses a low-voltage reference voltage generating circuit and a chip, wherein the circuit comprises a reference current source module, a buffer module and a high-order temperature compensation module, wherein the reference current source module is used for respectively providing zero-temperature current for the buffer module and the high-order temperature compensation module and providing negative temperature characteristic voltage for the buffer module; the buffer module is used for generating an offset voltage with positive temperature characteristics according to the zero-temperature current and superposing the offset voltage and the negative temperature characteristic voltage to output a first band gap reference voltage; the high-order temperature compensation module is used for performing high-order temperature compensation on the first bandgap reference voltage according to the zero temperature current so as to enable the buffer module to output the low-temperature floating bandgap reference voltage. Therefore, the output of the low-temperature drift band gap reference voltage can be realized, the low working voltage can be in a wide working voltage range, and the circuit design complexity and the power consumption can be reduced.

Description

Low-voltage reference voltage generating circuit and chip

technical field

The present invention relates to the technical field of integrated circuits, in particular to a low-voltage reference voltage generating circuit and a chip.

Background technique

The bandgap reference voltage circuit can provide a reference voltage independent of process, voltage and temperature, so it is widely used in various analog circuits. With the rapid development of high-precision data acquisition systems in the industrial field, the sampling accuracy of the chips in the acquisition system and the The variation of sampling accuracy with temperature depends heavily on the high-precision reference source on the chip. In order to ensure that the absolute sampling accuracy does not change with temperature when the chip operates in a wide temperature range, it is urgent to develop a high-precision low-temperature drift and wide-temperature range operation. Bandgap reference voltage source, at the same time, with the continuous shrinking of the process node, the chip operating voltage is also gradually decreasing, which also puts forward higher requirements for the minimum operating voltage of the chip reference source.

The current solution of the related bandgap reference source is usually a traditional bandgap reference source circuit plus a high-order temperature compensation loop to achieve high-order temperature compensation for the bandgap reference voltage, thereby improving the accuracy of the reference source, but This method is difficult to further reduce the reference voltage, and cannot meet the low-voltage reference voltage with a wide operating voltage range, and at the same time, this method also greatly increases the design complexity and power consumption.

SUMMARY OF THE INVENTION

The present invention aims to solve one of the technical problems in the related art at least to a certain extent. Therefore, the first object of the present invention is to provide a low-voltage reference voltage generating circuit, which can not only realize the output of the low-temperature drift bandgap reference voltage, but also make the low working voltage in a wide working voltage range, and at the same time can reduce the Circuit design complexity and power consumption.

The second object of the present invention is to provide a chip.

In order to achieve the above object, an embodiment of the first aspect of the present invention provides a low-voltage reference voltage generating circuit, including a reference current source module, a buffer module and a high-order temperature compensation module, wherein the reference current source module is used to respectively supply the buffer to the buffer. The module and the high-order temperature compensation module provide zero temperature current and negative temperature characteristic voltage to the buffer module; the buffer module is used to generate an offset voltage with positive temperature characteristic according to the zero temperature current, and compare the offset voltage with the negative temperature characteristic voltage superimpose to output the first bandgap reference voltage; the high-order temperature compensation module is used to perform high-order temperature compensation on the first bandgap reference voltage according to the zero temperature current, so that the buffer module outputs the low temperature drift bandgap reference voltage.

According to the low-voltage reference voltage generating circuit of the embodiment of the present invention, the reference current source module provides the buffer module and the high-order temperature compensation module with zero temperature current, respectively, and provides the buffer module with a negative temperature characteristic voltage, and the buffer module is based on the zero temperature characteristic voltage. The temperature current generates an offset voltage with positive temperature characteristics, and superimposes the offset voltage with the negative temperature characteristic voltage provided by the reference current source module to output the first bandgap reference voltage, and the high-order temperature compensation module is based on the zero temperature current. The first bandgap reference voltage performs high-order temperature compensation, so that the buffer module outputs the low-temperature drift bandgap reference voltage. Therefore, not only the output of the low temperature drift bandgap reference voltage can be realized, but also the low operating voltage can be in a wide operating voltage range, and the circuit design complexity and power consumption can also be reduced.

According to one embodiment of the present invention, the buffer module includes at least one buffer.

According to an embodiment of the present invention, when there are multiple buffers, the multiple buffers are cascaded.

According to an embodiment of the present invention, the buffer includes: a first transistor, the source of the first transistor is connected to a preset power supply, the gate of the first transistor is connected to the reference current source module; the second transistor and the third transistor, the first transistor The source of the second transistor is connected to the source of the third transistor and then connected to the drain of the first transistor, the gate of the second transistor is connected to the reference current source module, and the gate of the third transistor is connected to the drain as a buffer The cascade output terminal of the fourth transistor, the gate of the fourth transistor is connected to the drain and then connected to the drain of the second transistor, and the source of the fourth transistor is grounded; the fifth transistor, the gate of the fifth transistor is connected to the drain of the second transistor. The gates of the four transistors are connected, the drain of the fifth transistor is connected to the drain of the third transistor, and the source of the fifth transistor is grounded.

According to an embodiment of the present invention, the first transistor, the second transistor and the third transistor are all PMOS transistors, and the fourth transistor and the fifth transistor are all NMOS transistors.

According to an embodiment of the present invention, the second transistor, the third transistor, the fourth transistor and the fifth transistor operate in the sub-threshold region.

According to an embodiment of the present invention, the size ratio of the second transistor to the third transistor is 1:M, and the size ratio of the fourth transistor to the fifth transistor is P:1, wherein M and P are positive integers greater than 1.

According to an embodiment of the present invention, the reference current source module includes: a sixth transistor and a seventh transistor, the source of the sixth transistor is connected to the source of the seventh transistor and then connected to a preset power supply, and the gate of the sixth transistor is connected to the source of the seventh transistor. The gate of the seventh transistor is connected to and has a first node; the eighth transistor, the emitter of the eighth transistor is connected to the drain of the sixth transistor and has a second node, the base of the eighth transistor is connected to the collector and then grounded; The first resistor, one end of the first resistor is connected to the drain of the seventh transistor and has a third node; the ninth transistor, the emitter of the ninth transistor is connected to the other end of the first resistor, and the base of the ninth transistor is connected to the collector. The electrodes are connected and then grounded; for the error amplifier, the positive input end of the error amplifier is connected to the third node, the negative input end of the error amplifier is connected to the second node, and the output end of the error amplifier is connected to the first node and then connected to the gate of the first transistor pole; the second resistor, one end of the second resistor is connected to the negative input end of the error amplifier; the third resistor, one end of the third resistor is connected to the positive input end of the error amplifier, and the other end of the third resistor is connected to the other end of the second resistor One end is connected and has a fourth node, the fourth node is connected to the gate of the second transistor; a fourth resistor, one end of the fourth resistor is connected to the fourth node, and the other end of the fourth resistor is grounded.

According to an embodiment of the present invention, the ratio of the emitter areas of the eighth transistor to the ninth transistor is 1:N, where N is an integer greater than 1.

According to an embodiment of the present invention, the high-order temperature compensation module includes: a tenth transistor, the source of the tenth transistor is connected to a preset power supply, and the gate of the tenth transistor is connected to the output end of the error amplifier; the eleventh transistor, The emitter of the eleventh transistor is connected to the drain of the tenth transistor and has a fifth node, the collector of the eleventh transistor is connected to the base and then grounded; the fifth resistor, one end of the fifth resistor is connected to the fifth node, The other end of the fifth resistor is connected to the second node; the sixth resistor, one end of the sixth resistor is connected to the fifth node, and the other end of the sixth resistor is connected to the third node.

According to an embodiment of the present invention, the eighth transistor, the ninth transistor and the eleventh transistor are all bipolar transistors.

According to an embodiment of the present invention, the sixth transistor, the seventh transistor and the tenth transistor are all PMOS transistors and have the same size.

According to an embodiment of the present invention, the final low temperature drift bandgap reference voltage output by the buffer module is based on the emitter-base voltage of the eighth transistor, the emitter-base voltage of the eleventh transistor, and the resistance value of the second resistor , the resistance value of the fourth resistor, the resistance value of the fifth resistor, and the difference between the gate-source voltage of the third transistor and the gate-source voltage of the fourth transistor are determined.

In order to achieve the above object, an embodiment of the second aspect of the present invention provides a chip including the low-voltage reference voltage generating circuit as in the embodiment of the first aspect.

According to the chip of the embodiment of the present invention, through the above-mentioned low-voltage reference voltage generating circuit, not only the output of the low-temperature drift bandgap reference voltage can be realized, but also the low operating voltage can be kept in a wide operating voltage range, and the circuit design complexity can be reduced at the same time. power consumption.

Additional aspects and advantages of the present invention will be set forth, in part, from the following description, and in part will be apparent from the following description, or may be learned by practice of the invention.

Description of drawings

1 is a schematic structural diagram of a low-voltage reference voltage generating circuit according to a first embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a low-voltage reference voltage generating circuit according to a second embodiment of the present invention.

Detailed ways

The following describes in detail the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, and are intended to explain the present invention and should not be construed as limiting the present invention.

The following describes the low-voltage reference voltage generating circuit and chip provided by the embodiments of the present invention with reference to the accompanying drawings.

FIG. 1 is a schematic structural diagram of a low-voltage reference voltage generating circuit according to a first embodiment of the present invention. As shown in FIG. 1 , the low-voltage reference voltage generating circuit includes a reference current source module 100 , a buffer module 200 and a high-order temperature compensation module 300 .

Wherein, the reference current source module 100 is used to provide zero-temperature current to the buffer module 200 and the high-order temperature compensation module 300 respectively, and to provide a negative temperature characteristic voltage to the buffer module 200; the buffer module 200 is used to generate a current according to the zero-temperature current. The offset voltage has a positive temperature characteristic, and the offset voltage and the negative temperature characteristic voltage are superimposed to output the first bandgap reference voltage; the high-order temperature compensation module 300 is used to increase the first bandgap reference voltage according to the zero temperature current. order temperature compensation, so that the buffer module 300 outputs the low temperature drift bandgap reference voltage.

Specifically, when the low-voltage reference voltage generating circuit works, the reference current source module 100 can generate a current that does not change with temperature, that is, a zero-temperature current, and can also generate a voltage with negative temperature characteristics. The buffer module 200 and the reference current source module 100 is connected to receive the zero temperature current and the negative temperature characteristic voltage generated from the reference current source module 100, and the buffer module 200 can form an offset voltage with positive temperature characteristic according to the received zero temperature current, which will have a positive temperature characteristic. The characteristic offset voltage is superimposed with the negative temperature characteristic voltage obtained directly from the reference current source module 100 to form the first bandgap reference voltage, since the first bandgap reference voltage is composed of the positive temperature characteristic offset voltage and the negative temperature characteristic voltage The high-order temperature compensation module 300 is connected to the reference current source module 100 and the buffer module 200 respectively. The high-order temperature compensation module 300 can perform high-order temperature compensation on the first bandgap reference voltage formed by the buffer module 200 according to the zero-temperature current obtained from the reference current source module 100, so as to realize the accurate compensation of the bandgap reference voltage, and finally make the The buffer module 300 outputs a bandgap reference voltage with low temperature drift.

According to the low-voltage reference voltage generating circuit of the embodiment of the present invention, the reference current source module provides the buffer module and the high-order temperature compensation module with zero temperature current, respectively, and provides the buffer module with a negative temperature characteristic voltage, and the buffer module is based on the zero temperature characteristic voltage. The temperature current generates an offset voltage with positive temperature characteristics, and superimposes the offset voltage with the negative temperature characteristic voltage provided by the reference current source module to output the first bandgap reference voltage, and the high-order temperature compensation module is based on the zero temperature current. The first bandgap reference voltage performs high-order temperature compensation, so that the buffer module outputs the low-temperature drift bandgap reference voltage. Therefore, not only the output of the low temperature drift bandgap reference voltage can be realized, but also the low operating voltage can be in a wide operating voltage range, and the circuit design complexity and power consumption can also be reduced.

In some embodiments, the buffer module 200 includes at least one buffer; when there are multiple buffers, the multiple buffers are cascaded, and the number of buffers can be selected and set according to actual requirements, for example, as shown in FIG. 2 As shown, the buffer module 200 includes two buffers.

Further, referring to FIG. 2, each buffer includes: a first transistor (eg M1), a second transistor (eg M2), a third transistor (eg M3), a fourth transistor (eg M4) and a Five transistors (such as M5), wherein the source of the first transistor (such as M1) is connected to the preset power supply VDD, and the gate of the first transistor (such as M1) is connected to the reference current source module 100; the second transistor (such as M2) is connected to the reference current source module 100; ) is connected to the source of the third transistor (eg M3) and then to the drain of the first transistor (eg M1), the gate of the second transistor (eg M2) is connected to the reference current source module 100, the third The gate of the transistor (such as M3) is connected to the drain as the cascade output end of the buffer; the gate of the fourth transistor (such as M4) is connected to the drain of the second transistor (such as M2) after being connected to the drain, The source of the fourth transistor (such as M4) is grounded to GND; the gate of the fifth transistor (such as M5) is connected to the gate of the fourth transistor (such as M4), and the drain of the fifth transistor (such as M5) is connected to the third transistor The drain (eg M3 ) is connected to the drain, and the source of the fifth transistor (eg M5 ) is grounded to GND.

Specifically, taking the buffer module 200 including two buffers as an example, as shown in FIG. 2 , the two buffers are a first buffer and a second buffer respectively, and the two buffers are connected in cascade. The source of the transistor M1 in the buffer and the transistor M1' in the second buffer are both connected to the preset power supply VDD, and the gate of the transistor M1 and the transistor M1' are connected to the reference current source module 100 after being connected, and the first buffer The source of the transistor M2 and the transistor M3 in the device are connected to the drain of the transistor M1, the gate of the transistor M2 is connected to the reference current source module 100, the gate of the transistor M3 is connected to the drain and then connected to the second buffer. The gate of the transistor M2' is connected to the gate, the gate of the transistor M4 in the first buffer is connected to the drain and then connected to the drain of the transistor M2, the source of the transistor M4 is grounded to GND, and the gate of the transistor M5 in the first buffer is connected The electrode is connected to the gate of the transistor M4, the drain of the transistor M5 is connected to the drain of the transistor M3, and the source of the transistor M5 is grounded to GND; the source of the transistor M2' and the transistor M3' in the second buffer are connected to the The drain of the transistor M1', the gate of the transistor M3' is connected to the drain and used as the cascade output terminal of the buffer, and the gate of the transistor M4' in the second buffer is connected to the drain and then connected to the transistor M2'. The drain, the source of the transistor M4' is grounded to GND, the gate of the transistor M5' in the second buffer is connected to the gate of the transistor M4', the drain of the transistor M5' is connected to the drain of the transistor M3', and the transistor M5 ' source to ground GND.

In some embodiments, the first transistor (eg, M1 ), the second transistor (eg, M2 ) and the third transistor (eg, M3 ) are all PMOS transistors, and the fourth transistor (eg, M4 ) and the fifth transistor (eg, M5 ) are all PMOS transistors. For the NMOS tube. That is to say, as shown in FIG. 2, the transistors M1, M2 and M3 in the first buffer are all PMOS transistors, and the transistors M4 and M5 are both NMOS transistors; the transistors M1', M2' and M3' in the second buffer are all They are PMOS transistors, and transistors M4' and M5' are both NMOS transistors.

In some embodiments, the second transistor (eg, M2), the third transistor (eg, M3), the fourth transistor (eg, M4), and the fifth transistor (eg, M5) operate in the sub-threshold region. That is to say, as shown in FIG. 2, transistors M2, M3, M4 and M5 in the first buffer work in the sub-threshold region; M2', M3', M4' and M5' in the second buffer work in the sub-threshold region .

In some embodiments, the size ratio of the second transistor (eg M2) to the third transistor (eg M3) is 1:M, and the size ratio of the fourth transistor (eg M4) to the fifth transistor (eg M5) is P: 1, where M and P are positive integers greater than 1. That is to say, as shown in FIG. 2 , the size ratio of the transistor M2 and the transistor M3 in the first buffer is 1:M, and the size ratio of the transistor M4 and the transistor M5 is P:1; The size ratio of the transistor M3' is 1:M, and the size ratio of the transistor M4' and the transistor M5' is P:1.

Specifically, when the buffer module 200 is working, the transistor M1 in the first buffer and the transistor M1 ′ in the second buffer are controlled by the reference current source module 100 and flow the same current, the first buffer The middle transistors M2, M3, M4 and M5 work in the sub-threshold region. Using the characteristics of the transistors working in the sub-threshold region, the size ratio of the transistors is designed, for example, the size ratio of the transistor M2 and the transistor M3 in the first buffer is set. is 1:M, the size ratio of transistor M4 and transistor M5 is P:1, which can generate an offset voltage with positive temperature characteristics; the structure of the second buffer is the same as that of the first buffer, and the transistor M2' in the second buffer , M3', M4' and M5' also work in the sub-threshold region, so that an offset voltage with positive temperature characteristics can be generated, and the gate of the transistor M2' in the second buffer is the same as the gate of the transistor M3 in the first buffer. The gates are connected to realize the cascade connection of the buffers, and finally the negative temperature characteristic voltage formed by the reference current source module 100 is superimposed according to the offset voltage of the positive temperature characteristic formed by the first buffer and the second buffer, so as to obtain A bandgap reference voltage with zero temperature characteristic, that is, the first bandgap reference voltage.

In some embodiments, as shown in FIG. 2 , the reference current source module 100 includes: a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a first resistor R1, a ninth transistor M9, an error amplifier A, a second transistor Resistor R2, third resistor R3 and fourth resistor R4.

The source of the sixth transistor M6 is connected to the source of the seventh transistor M7 and then connected to the preset power supply VDD, the gate of the sixth transistor M6 is connected to the gate of the seventh transistor M7 and has a first node; the eighth The emitter of the transistor M8 is connected to the drain of the sixth transistor M6 and has a second node, the base of the eighth transistor M8 is connected to the collector and then grounded to GND; one end of the first resistor R1 is connected to the drain of the seventh transistor M7 and has a third node; the emitter of the ninth transistor M9 is connected to the other end of the first resistor R1, the base of the ninth transistor M9 is connected to the collector and then grounded to GND; the positive input end of the error amplifier A is connected to the third node , the negative input end of the error amplifier A is connected to the second node, the output end of the error amplifier A is connected to the first node and then connected to the gate of the first transistor (such as M1); one end of the second resistor R2 is connected to the error amplifier A’s gate The negative input end is connected; one end of the third resistor R3 is connected to the positive input end of the error amplifier A, the other end of the third resistor R3 is connected to the other end of the second resistor R2 and has a fourth node, and the fourth node is connected to the second The gate of the transistor (eg M2); one end of the fourth resistor R4 is connected to the fourth node, and the other end of the fourth resistor R4 is grounded to GND.

Specifically, the output end of the operational amplifier A is connected to the sixth transistor M6 and the seventh transistor M7, respectively, and both the sixth transistor M6 and the seventh transistor M7 are controlled by the operational amplifier A, and the magnitude of the current generated by it is proportional to its size, The eighth transistor M8 and the ninth transistor M9 generate a current proportional to temperature, that is, a positive temperature current, and transmit it to the first resistor R1, while the second resistor R2, the third resistor R3 and the fourth resistor R4 generate a negative temperature current , the current in the seventh transistor M7 is the sum of the currents flowing through the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4, so by adjusting the first resistor R1 and the second resistor R2, the third resistor The ratio of the resistor R3 to the fourth resistor R4 can obtain the first-order zero-temperature current, which is transmitted to the buffer module 200 and the high-order temperature compensation module 300 respectively.

In some embodiments, the ratio of the emitter areas of the eighth transistor M8 to the ninth transistor M9 is 1:N, where N is an integer greater than 1. That is to say, the ratio of the saturation current of the eighth transistor M8 to the ninth transistor M9 is 1:N.

In some embodiments, as shown in FIG. 2 , the high-order temperature compensation module 300 includes: a tenth transistor M10 , an eleventh transistor M11 , a fifth resistor R5 and a sixth resistor R6 .

The source of the tenth transistor M10 is connected to the preset power supply VDD, the gate of the tenth transistor M10 is connected to the output end of the error amplifier A; the emitter of the eleventh transistor M11 is connected to the drain of the tenth transistor M10 and There is a fifth node, the collector of the eleventh transistor M11 is connected to the base and then grounded to GND; one end of the fifth resistor R5 is connected to the fifth node, and the other end of the fifth resistor R5 is connected to the second node; the sixth resistor R6 One end of the resistor R6 is connected to the fifth node, and the other end of the sixth resistor R6 is connected to the third node.

Specifically, the output end of the operational amplifier A is connected to the tenth transistor M10, and the tenth transistor M10 is controlled by the operational amplifier A, so the current in the seventh transistor M7 can be mirrored to the tenth transistor M10, then the tenth transistor M10 A current with zero temperature coefficient can be provided to the eleventh crystal M11, and the emitters of the eighth transistor M8 and the ninth transistor M9 are respectively connected to the emitter of the eleventh transistor M11 through the fifth resistor R5 and the sixth resistor R6, Based on the difference between the positive temperature coefficient current in the eighth transistor M8 and the ninth transistor M9 and the zero temperature coefficient current in the eleventh transistor M11 , high-order temperature compensation of the bandgap reference voltage is realized.

In some embodiments, the eighth transistor M8, the ninth transistor M9 and the eleventh transistor M11 are all bipolar transistors.

In some embodiments, the sixth transistor M6 , the seventh transistor M7 and the tenth transistor M10 are all PMOS transistors and have the same size.

In some embodiments, the final low temperature drift bandgap reference voltage output by the buffer module 200 is based on the emitter-base voltage of the eighth transistor M8, the emitter-base voltage of the eleventh transistor M11, and the voltage of the second resistor R2. The resistance value, the resistance value of the fourth resistor R4, the resistance value of the fifth resistor R5, and the difference between the gate-source voltage of the third transistor (such as M3) and the gate-source voltage of the fourth transistor (such as M4) Sure.

As a specific example, as shown in Figure 2, assuming that the gain of the operational amplifier A is large enough and the input impedance is infinite, the voltages of the positive input terminal and the negative input terminal of the operational amplifier A are equal, ignoring the mismatch in the circuit, such as between the resistors The mismatch between the transistors, the mismatch between the transistors and the mismatch between the bipolar transistors, assuming that the emitter-base voltage of the eighth transistor M8 is V _EB1 , and the emitter-base voltage of the ninth transistor M9 is V _EB2 , The emitter-base voltage of the eleventh crystal M11 is V _EB3 , and the relationship between the collector current of the bipolar transistor and its emitter-base voltage is:

Among them, IC is the collector current of the bipolar transistor, _{IS is the saturation current of the bipolar transistor, V T is the} thermal voltage, V _T =KT/q, q is the electron charge, and V _EB is the bipolar transistor The emitter-base voltage of , K is the Boltzmann constant, and T is the absolute temperature.

The current in a bipolar transistor is:

Among them, I _Q is the bipolar transistor current, _IE is the bipolar transistor emitter current, _IB is the bipolar transistor base current, and β _F is the current amplification factor.

Thus it can be deduced that the emitter-base voltage of the bipolar transistor is:

The current of a transistor operating in the subthreshold region is:

为晶体管的宽长比，n亚阈值斜坡因子，是一个与工艺有关的常量，典型值为1～1.5，V_GS为晶体管栅极-源极电压，K为波尔兹曼常数，T为绝对温度，q为电子电荷。where I _ds is the drain-source voltage of the transistor, I _D0 is the saturation current of the transistor drain,

is the aspect ratio of the transistor, n is a subthreshold slope factor, which is a constant related to the process, with a typical value of 1 to 1.5, V _GS is the gate-source voltage of the transistor, K is the Boltzmann constant, and T is the absolute temperature, and q is the electron charge.

Ignoring the effect of the channel length of the transistor, in this application, the size ratio of the transistor M2 and the transistor M3 in the first buffer is 1:M, and the size ratio of the transistor M4 and the transistor M5 is P:1. The offset voltage of the positive temperature characteristic formed by a snubber:

ΔV _GS =V _GS1 -V _GS2 =nV _T ln[P×M]

Among them, ΔV _GS is the offset voltage of the positive temperature characteristic, V _GS1 is the gate-source voltage of the third transistor M3 , and V _GS2 is the gate-source voltage of the fourth transistor M4 . It should be noted that the offset voltage of the positive temperature characteristic formed by the second buffer is the same as the offset voltage of the positive temperature characteristic formed by the second buffer.

The offset voltage of the positive temperature characteristic formed by the two buffers and the negative temperature characteristic voltage are superimposed to obtain the first bandgap reference voltage:

Wherein, V _EB1 is the emitter-base voltage of the eighth transistor M8 , R2 is the second resistor, and R4 is the fourth resistor.

Since the sixth transistor M6, the seventh transistor M7 and the tenth transistor M10 are all PMOS transistors and have the same size, the currents of the three are also equal, and the current I M8 of the eighth transistor _M8 and the current I _M9 of the ninth transistor M9 are positive temperature Current, the current I _R2 in the second resistor R2 is a negative temperature current. By adjusting the size of the second resistor R2, the current weakly related to the temperature can be obtained:

Among them, I _M6 sixth transistor M6 current, I _M7 seventh transistor M7 current, I _M10 tenth transistor M10 current, V _EB1 is the emitter-base voltage of the eighth transistor M8, V _EB2 is the emission of the ninth transistor M9 The pole-base voltage, R1 is the first resistor, R2 is the second resistor, and R4 is the fourth resistor.

Perform high-order temperature compensation on the first bandgap reference voltage according to the zero-temperature current, and finally obtain the low-temperature drift bandgap reference voltage:

Wherein, V _EB1 is the emitter-base voltage of the eighth transistor M8, V _EB3 is the emitter-base voltage of the eleventh transistor M11, R2 is the second resistor, R4 is the fourth resistor, and R4 is the fifth resistor , ΔV _GS is the offset voltage of the positive temperature characteristic.

To sum up, according to the low-voltage reference voltage generating circuit according to the embodiment of the present invention, the reference current source module provides zero-temperature current to the buffer module and the high-order temperature compensation module, respectively, and provides the buffer module with a negative temperature characteristic voltage, buffering the buffer module. The controller module generates an offset voltage with positive temperature characteristics according to the zero temperature current, and superimposes the offset voltage with the negative temperature characteristic voltage provided by the reference current source module to output the first bandgap reference voltage, which is passed through the high-order temperature compensation module. High-order temperature compensation is performed on the first bandgap reference voltage according to the zero temperature current, so that the buffer module outputs the low-temperature drift bandgap reference voltage. Therefore, not only the output of the low temperature drift bandgap reference voltage can be realized, but also the low operating voltage can be in a wide operating voltage range, and the circuit design complexity and power consumption can also be reduced.

An embodiment of the present invention also provides a chip, including the above-mentioned low-voltage reference voltage generating circuit.

It should be noted that, in this application, the above-mentioned chips may be ADC chips, reference voltage source chips, switching power supply chips, or other chips that can generate reference voltages, which are not specifically limited here.

According to the chip of the embodiment of the present invention, through the above-mentioned low-voltage reference voltage generating circuit, not only the output of the low-temperature drift bandgap reference voltage can be realized, but also the low operating voltage can be kept in a wide operating voltage range, and the circuit design complexity can be reduced at the same time. power consumption.

It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein, for example, may be considered as an ordered listing of executable instructions for implementing the logical functions, and may be embodied in any computer readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device), or in combination with these used to execute a system, device or device. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport the program for use by or in connection with an instruction execution system, apparatus, or apparatus. More specific examples (non-exhaustive list) of computer readable media include the following: electrical connections with one or more wiring (electronic devices), portable computer disk cartridges (magnetic devices), random access memory (RAM), Read Only Memory (ROM), Erasable Editable Read Only Memory (EPROM or Flash Memory), Fiber Optic Devices, and Portable Compact Disc Read Only Memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program may be printed, as the paper or other medium may be optically scanned, for example, followed by editing, interpretation, or other suitable medium as necessary process to obtain the program electronically and then store it in computer memory.

It should be understood that various parts of the present invention may be implemented in hardware, software, firmware or a combination thereof. In the above-described embodiments, various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one or a combination of the following techniques known in the art: Discrete logic circuits, application specific integrated circuits with suitable combinational logic gates, Programmable Gate Arrays (PGA), Field Programmable Gate Arrays (FPGA), etc.

In the description of this specification, description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., mean specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature delimited with "first", "second" may expressly or implicitly include at least one of that feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise expressly and specifically defined.

In the present invention, unless otherwise expressly specified and limited, the terms "installed", "connected", "connected", "fixed" and other terms should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection , or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between the two elements, unless otherwise specified limit. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

Although the embodiments of the present invention have been shown and described above, it should be understood that the above-mentioned embodiments are exemplary and should not be construed as limiting the present invention. Embodiments are subject to variations, modifications, substitutions and variations.

Claims (14)

1. A low-voltage reference voltage generating circuit, comprising a reference current source module, a buffer module and a high-order temperature compensation module, wherein, The reference current source module is configured to provide a zero-temperature current to the buffer module and the high-order temperature compensation module, respectively, and to provide a negative temperature characteristic voltage to the buffer module; The buffer module is configured to generate an offset voltage with a positive temperature characteristic according to the zero temperature current, and superimpose the offset voltage and the negative temperature characteristic voltage to output a first bandgap reference voltage; The high-order temperature compensation module is configured to perform high-order temperature compensation on the first bandgap reference voltage according to the zero temperature current, so that the buffer module outputs a low-temperature drift bandgap reference voltage. 2 . The low-voltage reference voltage generating circuit according to claim 1 , wherein the buffer module comprises at least one buffer. 3 . 3 . The low-voltage reference voltage generating circuit according to claim 2 , wherein when there are a plurality of the buffers, a plurality of the buffers are cascaded. 4 . 4. The low-voltage reference voltage generating circuit according to claim 2 or 3, wherein the buffer comprises: a first transistor, the source of the first transistor is connected to a preset power supply, and the gate of the first transistor is connected to the reference current source module; A second transistor and a third transistor, the source of the second transistor is connected to the source of the third transistor and then connected to the drain of the first transistor, the gate of the second transistor is connected to the reference the current source module is connected, and the gate of the third transistor is connected to the drain as the cascade output end of the buffer; a fourth transistor, the gate of the fourth transistor is connected to the drain and then connected to the drain of the second transistor, and the source of the fourth transistor is grounded; a fifth transistor, the gate of the fifth transistor is connected to the gate of the fourth transistor, the drain of the fifth transistor is connected to the drain of the third transistor, and the source of the fifth transistor ground. 5 . The low-voltage reference voltage generating circuit according to claim 4 , wherein the first transistor, the second transistor and the third transistor are all PMOS transistors, and the fourth transistor and the third transistor are PMOS transistors. 6 . The five transistors are all NMOS transistors. 6 . The low-voltage reference voltage generating circuit according to claim 5 , wherein the second transistor, the third transistor, the fourth transistor and the fifth transistor operate in a sub-threshold region. 7 . 7 . The low-voltage reference voltage generating circuit according to claim 5 , wherein the size ratio of the second transistor and the third transistor is 1:M, and the difference between the fourth transistor and the fifth transistor is 1:M. 8 . The size ratio is P:1, where M and P are positive integers greater than 1. 8. The low-voltage reference voltage generating circuit according to claim 4, wherein the reference current source module comprises: A sixth transistor and a seventh transistor, the source of the sixth transistor is connected to the source of the seventh transistor and then connected to the preset power supply, and the gate of the sixth transistor is connected to the seventh transistor. the gates are connected and have a first node; an eighth transistor, the emitter of the eighth transistor is connected to the drain of the sixth transistor and has a second node, the base of the eighth transistor is connected to the collector and then grounded; a first resistor, one end of the first resistor is connected to the drain of the seventh transistor and has a third node; a ninth transistor, the emitter of the ninth transistor is connected to the other end of the first resistor, and the base of the ninth transistor is connected to the collector and then grounded; an error amplifier, the positive input end of the error amplifier is connected to the third node, the negative input end of the error amplifier is connected to the second node, and the output end of the error amplifier is connected to the first node connected to the gate of the first transistor; a second resistor, one end of the second resistor is connected to the negative input end of the error amplifier; A third resistor, one end of the third resistor is connected to the positive input end of the error amplifier, the other end of the third resistor is connected to the other end of the second resistor and has a fourth node, the fourth a node connected to the gate of the second transistor; A fourth resistor, one end of the fourth resistor is connected to the fourth node, and the other end of the fourth resistor is grounded. 9 . The low-voltage reference voltage generating circuit according to claim 8 , wherein the ratio of the emitter area of the eighth transistor to the ninth transistor is 1:N, wherein N is an integer greater than 1. 10 . 10. The low-voltage reference voltage generating circuit according to claim 8, wherein the high-order temperature compensation module comprises: a tenth transistor, the source of the tenth transistor is connected to the preset power supply, and the gate of the tenth transistor is connected to the output end of the error amplifier; an eleventh transistor, the emitter of the eleventh transistor is connected to the drain of the tenth transistor and has a fifth node, and the collector of the eleventh transistor is connected to the base and then grounded; a fifth resistor, one end of the fifth resistor is connected to the fifth node, and the other end of the fifth resistor is connected to the second node; A sixth resistor, one end of the sixth resistor is connected to the fifth node, and the other end of the sixth resistor is connected to the third node. 11 . The low-voltage reference voltage generating circuit according to claim 10 , wherein the eighth transistor, the ninth transistor and the eleventh transistor are all bipolar transistors. 12 . 12 . The low-voltage reference voltage generating circuit according to claim 10 , wherein the sixth transistor, the seventh transistor and the tenth transistor are all PMOS transistors and have the same size. 13 . 13 . The low-voltage reference voltage generating circuit according to claim 10 , wherein the final low temperature drift bandgap reference voltage output by the buffer module is based on the emitter-base voltage of the eighth transistor, the first The emitter-base voltage of the eleventh transistor, the resistance value of the second resistor, the resistance value of the fourth resistor, the resistance value of the fifth resistor, and the gate-source voltage of the third transistor The difference with the gate-source voltage of the fourth transistor is determined. 14. A chip, characterized by comprising the low-voltage reference voltage generating circuit according to any one of claims 1-13.

Images