CN113804319B

CN113804319B - Temperature sensor and integrated circuit

Info

Publication number: CN113804319B
Application number: CN202111204768.7A
Authority: CN
Inventors: 习伟; 李鹏; 蔡田田; 邓清唐; 陈波
Original assignee: Southern Power Grid Digital Grid Research Institute Co Ltd
Current assignee: Southern Power Grid Digital Grid Research Institute Co Ltd
Priority date: 2021-10-15
Filing date: 2021-10-15
Publication date: 2024-08-27
Anticipated expiration: 2041-10-15
Also published as: CN113804319A

Abstract

The application relates to a temperature sensor and an integrated circuit, which comprise a voltage generating module, a voltage compensating module and an output module, wherein the input end of the voltage generating module is electrically connected with an external power supply; the voltage generation module is used for generating negative temperature coefficient voltage inversely proportional to temperature; the output end of the voltage generation module is electrically connected with the input end of the voltage compensation module; the voltage compensation module is used for compensating the negative temperature coefficient voltage and generating a compensation voltage irrelevant to temperature; the output end of the voltage generating module and the output end of the voltage compensating module are electrically connected with the input end of the output module; the output module is used for outputting positive temperature coefficient voltage according to the compensation voltage and the negative temperature coefficient voltage. The compensation voltage can carry out voltage compensation on the negative temperature coefficient voltage, and the positive temperature coefficient voltage obtained by the difference between the compensation voltage and the negative temperature coefficient voltage can effectively remove the influence caused by process deviation, so that the temperature measurement precision of the temperature sensor is improved.

Description

Temperature sensor and integrated circuit

Technical Field

The present application relates to the field of sensor technologies, and in particular, to a temperature sensor and an integrated circuit.

Background

In recent years, with rapid development of smart grids, temperature sensors are increasingly widely used in smart grid devices. On the one hand, the temperature sensor can detect temperature abnormality caused by the occurrence of faults of the intelligent power grid equipment, and on the other hand, the temperature sensor can detect the temperatures of different modules in the intelligent power grid equipment and control the different modules to adjust the working states of the temperature sensor based on the temperatures. Therefore, the temperature sensor is an important temperature control device in the smart grid device.

The types of temperature sensors are various, and thermal resistance temperature sensors, thermocouple temperature sensors, integrated temperature sensors and the like are commonly used. With the high-speed development of integrated circuit technology, integrated temperature sensors are widely applied to integrated circuits, and the conventional integrated temperature sensors mainly adopt bipolar transistors to realize temperature acquisition. However, at present, the measurement accuracy of the bipolar transistor to the temperature is low.

Based on this, it is desirable to provide a temperature sensor to improve the accuracy of temperature measurement.

Disclosure of Invention

In view of the above, it is necessary to provide a temperature sensor and an integrated circuit capable of improving the accuracy of temperature measurement.

The temperature sensor comprises a voltage generation module, a voltage compensation module and an output module, wherein the input end of the voltage generation module is electrically connected with an external power supply; the voltage generation module is used for generating negative temperature coefficient voltage inversely proportional to temperature; the output end of the voltage generation module is electrically connected with the input end of the voltage compensation module; the voltage compensation module is used for compensating the negative temperature coefficient voltage and generating a compensation voltage irrelevant to temperature; the output end of the voltage generating module and the output end of the voltage compensating module are electrically connected with the input end of the output module; the output module is used for outputting positive temperature coefficient voltage according to the compensation voltage and the negative temperature coefficient voltage.

In one embodiment, the voltage generation module comprises a bias current generation circuit, a MOS transistor operating in a subthreshold region, a first current mirror circuit, a second current mirror circuit and a third current mirror circuit; the first current mirror circuit, the second current mirror circuit and the third current mirror circuit are cascode current mirrors;

In one embodiment, a bias current generating circuit is used for generating bias current; a MOS transistor operating in a subthreshold region for generating a voltage inversely proportional to temperature; the first current mirror circuit, the second current mirror circuit and the third current mirror circuit are used for copying bias currents according to different proportions to generate a first bias current, a second bias current and a third bias current; the voltage generation module is used for generating equivalent voltages of the first current mirror circuit, the second current mirror circuit and the third current mirror circuit based on the equivalent resistances of the first bias current, the second bias current and the third bias current, the first current mirror circuit, the second current mirror circuit and the third current mirror circuit; the negative temperature coefficient voltage is generated from the voltage inversely proportional to the temperature, the equivalent voltages of the first current mirror circuit, the second current mirror circuit, and the third current mirror circuit.

In one embodiment, the bias current generating circuit includes a first NMOS transistor and a second NMOS transistor.

The source electrode of the first NMOS transistor is grounded, the drain electrode of the first NMOS transistor is electrically connected with the source electrode of the second NMOS transistor, the drain electrode of the second NMOS transistor is electrically connected with the first current mirror circuit, and the grid electrode of the first NMOS transistor and the grid electrode of the second NMOS transistor are electrically connected with the MOS transistor working in the subthreshold region.

In one embodiment, the MOS transistors operating in the sub-threshold region include a third NMOS transistor and a fourth NMOS transistor.

The source electrode of the third NMOS transistor is grounded, the drain electrode of the third NMOS transistor is electrically connected with the source electrode of the fourth NMOS transistor, the drain electrode of the third NMOS transistor is electrically connected with the grid electrode of the first NMOS transistor, the drain electrode of the fourth NMOS transistor is electrically connected with the grid electrode of the third NMOS transistor, the grid electrode of the second NMOS transistor is electrically connected with the grid electrode of the fourth NMOS transistor, and the drain electrode of the fourth NMOS transistor is electrically connected with the second current mirror circuit.

In one embodiment, the first current mirror circuit includes a fifth PMOS transistor and a sixth PMOS transistor, the second current mirror circuit includes a seventh PMOS transistor and an eighth PMOS transistor, and the third current mirror circuit includes a ninth PMOS transistor and a tenth PMOS transistor.

The drain electrode of the fifth PMOS transistor, the drain electrode of the eighth PMOS transistor and the drain electrode of the tenth PMOS transistor are electrically connected with an external power supply, the source electrode of the sixth PMOS transistor is electrically connected with the drain electrode of the fifth PMOS transistor, and the source electrode of the fifth PMOS transistor is electrically connected with the drain electrode of the second NMOS transistor;

The source electrode of the eighth PMOS transistor is electrically connected with the drain electrode of the seventh PMOS transistor, and the source electrode of the seventh PMOS transistor is electrically connected with the drain electrode of the fourth NMOS transistor;

The source electrode of the tenth PMOS transistor is electrically connected with the drain electrode of the ninth PMOS transistor, and the source electrode of the ninth PMOS transistor is electrically connected with the source electrode of the fourth NMOS transistor;

the grid electrode of the sixth PMOS transistor is electrically connected with the source electrode of the sixth PMOS transistor, the grid electrode of the sixth PMOS transistor is electrically connected with the grid electrode of the eighth PMOS transistor and the grid electrode of the tenth PMOS transistor respectively, the grid electrode of the fifth PMOS transistor is electrically connected with the source electrode of the fifth PMOS transistor, and the grid electrode of the fifth PMOS transistor is electrically connected with the grid electrode of the seventh PMOS transistor and the grid electrode of the ninth PMOS transistor respectively.

In one embodiment, the voltage compensation module includes a fourth current mirror circuit, a differential pair operating in a subthreshold region, and a fifth current mirror circuit.

In one embodiment, a fourth current mirror circuit is configured to replicate the bias current in different proportions to generate a fourth bias current; the fifth current mirror circuit is a basic current mirror and is used for generating a fifth bias current according to the negative temperature coefficient voltage; the voltage compensation module is used for inputting a fourth bias current and a fifth bias current into the differential pair working in the subthreshold region to generate a first output voltage of the differential pair and a second output voltage of the differential pair; a temperature independent compensation voltage is generated based on the first output voltage of the differential pair and the second output voltage of the differential pair.

In one embodiment, the differential pair operating in the subthreshold region includes an eleventh PMOS transistor and a twelfth PMOS transistor.

The grid electrode of the eleventh PMOS transistor is respectively and electrically connected with the output end of the voltage generation module, the drain electrode of the eleventh PMOS transistor and the drain electrode of the twelfth PMOS transistor are electrically connected with the fourth current mirror circuit, and the source electrode of the eleventh PMOS transistor and the source electrode of the twelfth PMOS transistor are electrically connected with the fifth current mirror circuit.

In one embodiment, the fourth current mirror circuit includes a fifteenth PMOS transistor and a sixteenth PMOS transistor.

The drain electrode of the sixteenth PMOS transistor is electrically connected with an external power supply, the source electrode of the sixteenth PMOS transistor is electrically connected with the drain electrode of the fifteenth PMOS transistor, the source electrode of the fifteenth PMOS transistor is electrically connected with the drain electrode of the eleventh PMOS transistor, the grid electrode of the sixteenth PMOS transistor is electrically connected with the voltage generation module, and the grid electrode of the fifteenth PMOS transistor is electrically connected with the voltage generation module.

In one embodiment, the fifth current mirror circuit includes a thirteenth NMOS transistor and a fourteenth NMOS transistor.

The drain of the thirteenth NMOS transistor and the gate of the thirteenth NMOS transistor are electrically connected to the source of the eleventh PMOS transistor, the source of the thirteenth NMOS transistor is grounded, the source of the twelfth PMOS transistor is electrically connected to the drain of the fourteenth NMOS transistor, the gate of the fourteenth NMOS transistor is electrically connected to the gate of the thirteenth NMOS transistor, and the source of the fourteenth NMOS transistor is grounded.

An integrated circuit comprising a temperature sensor according to any one of the above embodiments.

The temperature sensor and the integrated circuit comprise a voltage generation module, a voltage compensation module and an output module, wherein the input end of the voltage generation module is electrically connected with an external power supply; the voltage generation module is used for generating negative temperature coefficient voltage inversely proportional to temperature; the output end of the voltage generation module is electrically connected with the input end of the voltage compensation module; the voltage compensation module is used for compensating the negative temperature coefficient voltage and generating a compensation voltage irrelevant to temperature; the output end of the voltage generating module and the output end of the voltage compensating module are electrically connected with the input end of the output module; the output module is used for outputting positive temperature coefficient voltage according to the compensation voltage and the negative temperature coefficient voltage. The temperature-independent compensation voltage generated by the voltage compensation module performs voltage compensation on the negative temperature coefficient voltage generated by the voltage generation module, and the finally obtained positive temperature coefficient voltage can effectively remove the influence caused by process deviation, so that the temperature measurement precision of the temperature sensor is improved.

Drawings

FIG. 1 is a block diagram of a temperature sensor in one embodiment;

FIG. 2 is a block diagram of a voltage generation module in one embodiment;

FIG. 3 is a block diagram of a voltage compensation module in one embodiment;

FIG. 4 is a block diagram of a temperature sensor in one embodiment;

FIG. 5 is a schematic diagram of a negative temperature coefficient voltage V _ctat at different process angles according to one embodiment;

FIG. 6 is a schematic diagram of the compensation voltage V _bgr at different process angles according to one embodiment;

FIG. 7 is a schematic diagram of a positive temperature coefficient voltage at different process angles according to one embodiment;

FIG. 8 is a schematic diagram of the positive temperature coefficient voltage error at different process angles according to one embodiment;

Fig. 9 is a block diagram of an integrated circuit in one embodiment.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

FIG. 1 is a block diagram of a temperature sensor in one embodiment, as shown in FIG. 1, a temperature sensor is provided, including a voltage generation module 120, a voltage compensation module 140, and an output module 160, where an input end of the voltage generation module 120 is electrically connected to an external power source 180; the voltage generation module 120 is configured to generate a negative temperature coefficient voltage inversely proportional to temperature; the output end of the voltage generation module 120 is electrically connected with the input end of the voltage compensation module 140; the voltage compensation module 140 is configured to compensate the negative temperature coefficient voltage to generate a compensation voltage independent of temperature; the output end of the voltage generation module 120 and the output end of the voltage compensation module 140 are electrically connected with the input end of the output module 160; the output module 160 is configured to output a positive temperature coefficient voltage according to the compensation voltage and the negative temperature coefficient voltage.

In general, devices provided by manufacturers often have process variations, which specifically refer to variations in the actual manufactured device parameters from the design parameters. The actual integrated circuit manufacturing process has larger process deviation, such as resistance, and the deviation between the actual resistance and the design resistance is generally about + -20%. Similarly, there are also large process variations in devices such as MOS transistors and bipolar transistors, and the variation in parameters of MOS transistors is large between wafers and between batches compared to bipolar transistors, and particularly, the variation in threshold voltages of MOS transistors, the variation in channel lengths of MOS transistors, and the like are exhibited. Therefore, for a temperature sensor composed of MOS transistors, process deviation of the MOS transistors can greatly influence the measurement accuracy of the temperature sensor on temperature. To alleviate some of the difficulties of circuit design tasks, process engineers have to ensure that the performance of the device is within a certain range, i.e., the device is rejected if the set performance range is exceeded. This performance range is usually given in the form of a "process angle (Process Corners)", i.e. the range of variation of the parameters of the transistor is limited within a range defined by the process angle. The basic idea of the process angle is as follows: the speed fluctuation range of the NMOS transistor and the PMOS transistor is limited to a rectangle defined by four corners. The process angle is selected to obtain acceptable yield, and test simulation of the circuit under various process angles and extreme temperature conditions is the basis for determining the yield.

Further, the voltage generating module 120 is configured to generate a negative temperature coefficient voltage inversely proportional to the temperature, but the problem of process deviation causes a large difference between the negative temperature coefficient voltages at different process angles, thereby affecting the accuracy of temperature measurement. It is therefore desirable to eliminate the effect of process variations on the negative temperature coefficient voltage to improve the accuracy of the temperature sensor.

Further, the voltage compensation module 140 is configured to compensate the negative temperature coefficient voltage to eliminate the influence of the process deviation, and generate a compensation voltage independent of temperature. The compensation voltage generated by the voltage compensation module 140 and the negative temperature coefficient voltage generated by the voltage generation module 120 are respectively input into the output module 160 to obtain a difference value between the two voltages, namely, a positive temperature coefficient voltage. Further, since the compensation voltage and the negative temperature coefficient voltage are both analog signals, the output module 160 may convert the compensation voltage and the negative temperature coefficient voltage into digital signals, and then calculate the difference between the two signals to output. It is also possible to calculate the difference between the compensation voltage and the negative temperature coefficient voltage and then convert the difference into a digital signal for output. Preferably, the present application uses a differential Analog-to-Digital Converter (ADC) as an output module, i.e. the difference between the compensation voltage and the negative temperature coefficient voltage is calculated first, and then the difference is converted into a digital signal to be output, so as to obtain the final positive temperature coefficient voltage.

The temperature sensor provided by the application comprises a voltage generation module 120, a voltage compensation module 140 and an output module 160, wherein the input end of the voltage generation module 120 is electrically connected with an external power supply 180; the voltage generation module 120 is configured to generate a negative temperature coefficient voltage inversely proportional to temperature; the output end of the voltage generation module 120 is electrically connected with the input end of the voltage compensation module 140; the voltage compensation module 140 is configured to compensate the negative temperature coefficient voltage to generate a compensation voltage independent of temperature; the output end of the voltage generation module 120 and the output end of the voltage compensation module 140 are electrically connected with the input end of the output module 160; the output module 160 is configured to output a positive temperature coefficient voltage according to the compensation voltage and the negative temperature coefficient voltage. The negative temperature coefficient voltage may vary greatly at different process angles due to process variation, and the compensation voltage generated by the voltage compensation module 140 is independent of temperature. Therefore, the compensation voltage can perform voltage compensation on the negative temperature coefficient voltage, and the positive temperature coefficient voltage obtained by the output module 160 after the compensation voltage and the negative temperature coefficient voltage are subjected to difference can effectively remove the influence caused by process deviation, so that the measurement accuracy of the temperature sensor on the temperature is improved.

In one embodiment, fig. 2 is a block diagram of the voltage generating module 120 in one embodiment, and as shown in fig. 2, a block diagram of the voltage generating module 120 is provided, including a bias current generating circuit 121, a MOS transistor 122 operating in a subthreshold region, a first current mirror circuit 123, a second current mirror circuit 124, and a third current mirror circuit 125; the first current mirror circuit 123, the second current mirror circuit 124, and the third current mirror circuit 125 are cascode current mirrors.

Specifically, the bias current generating circuit 121 may generate a bias current. The basic bias of the analog integrated circuit includes a current bias and a voltage bias. The bias is provided to make the MOS transistor and its circuit in normal operation, and the current bias provides static operation current for relevant branch of the circuit. If the circuit supplies current to the circuit by setting an external current source, on the one hand, the addition of additional devices into the circuit can lead to an increase in circuit area; on the other hand, the addition of an external current source leads to an increase in the overall power consumption of the circuit. Therefore, by the bias current generated by the bias current generating circuit 121, the problems of an increase in circuit area and an increase in power consumption due to the use of an additional current source are avoided.

Further, the MOS transistor 122 operating in the subthreshold region has a smaller output current, thereby reducing the power consumption of the voltage generation module 120. The transistor subthreshold state is an important state or mode of operation of the MOS transistor, and a transistor subthreshold state of the MOS transistor is also referred to as a subthreshold region of the MOS transistor. In this state, the gate voltage of the MOS transistor is below the threshold voltage, no conduction channel is present, and the MOS transistor in this operating state generates a small current, which is a subthreshold current. Compared with the MOS transistor working in the saturation region, the subthreshold current generated by the MOS transistor working in the subthreshold region is smaller, but the subthreshold current generated by the MOS transistor 122 working in the subthreshold region can be well controlled by the gate voltage of the MOS transistor, so that the power consumption of the MOS transistor in the subthreshold region is lower.

Further, the first current mirror circuit 123, the second current mirror circuit 124 and the third current mirror circuit 125 are all MOS current mirror circuits, and the current mirror is one of the most basic unit circuits in the analog integrated circuit, and the current mirror is a circuit capable of reproducing or copying the reference current of one branch in the circuit in other branches. Current mirrors are often used to construct dc bias current sources in analog integrated circuits and devices due to their current replication capability. The current mirror may be classified into a bipolar current mirror and a MOS current mirror according to the integration process employed. Because the MOS process has higher integration level than the bipolar process and the N-channel and P-channel complementary symmetrical tube process transaction of manufacturing the MOS tube is realized, the MOS current mirror has wider application compared with the bipolar current mirror. In analog circuits, the current source design is based on a replica of the reference current, provided that an accurate current source is already available, which does not change the output current value due to the change in the potential of the output node. Assuming that the current source exists, if the effect of the channel length modulation effect of the MOS tube is not considered, the output current of the device working in the saturation region is irrelevant to the gate source voltage, and the error of the current ratio caused by the difference of the gate source voltage is avoided. Wherein the ratio of the replicated current to the reference current is determined by the ratio of the device dimensions. Through the design of the width-to-length ratio of the MOS transistor structure, a current source which is in any proportional relation with the reference current can be obtained, so that the requirements of all stages of amplifying circuits in the analog integrated circuit on different bias currents can be met.

Further, the first current mirror circuit 123, the second current mirror circuit 124, and the third current mirror circuit 125 are cascode current mirrors. The current mirror is used for accurately copying current, however, in practical application, the channel length modulation effect of the MOS transistor can cause a large error in the current copied by the basic current mirror. The channel length modulation effect refers to that in a MOS transistor, after a channel under a gate is pre-pinched off, if the drain-source voltage is continuously increased, the pinching-off point moves slightly to the source direction. The channel length between the pinch-off point and the source electrode is slightly reduced, and the effective channel resistance is slightly reduced, so that more electrons drift from the source electrode to the pinch-off point, the drift electrons in the depletion region are increased, and the drain current is increased. That is, when the drain-source voltage of the MOS transistor has a voltage difference, the current copied by the current mirror deviates. The drain-source voltage of the cascode current mirror is insensitive to the change of the output voltage, and the influence of channel length modulation can be effectively restrained, so that the cascode current mirror can more accurately replicate current.

In the embodiment of the present application, the voltage generating module 120 includes a bias current generating circuit 121, a MOS transistor 122 operating in a subthreshold region, a first current mirror circuit 123, a second current mirror circuit 124, and a third current mirror circuit 125; the first current mirror circuit 123, the second current mirror circuit 124, and the third current mirror circuit 125 are cascode current mirrors. Wherein, the bias current generating circuit 121 can generate bias current, which avoids the problems of increased area and power consumption of the voltage generating module 120 caused by using additional current sources. The MOS transistor 122 operating in the subthreshold region has a smaller output current, thereby reducing the power consumption of the voltage generation module 120. The first current mirror circuit 123, the second current mirror circuit 124 and the third current mirror circuit 125 are all cascode current mirrors, which can effectively inhibit the influence of channel length modulation in the MOS transistor, improve the precision of the replica current, provide accurate current for the voltage compensation circuit, and finally improve the measurement precision of the temperature sensor to the temperature.

In one embodiment, as shown in fig. 2, a bias current generating circuit 121 is used to generate a bias current; a MOS transistor 122 operating in a subthreshold region for generating a voltage inversely proportional to temperature; a first current mirror circuit 123, a second current mirror circuit 124, and a third current mirror circuit 125 for generating a first bias current, a second bias current, and a third bias current by copying the bias currents in different ratios; a voltage generation module 120 for generating equivalent voltages of the first current mirror circuit 123, the second current mirror circuit 124, and the third current mirror circuit 125 based on the equivalent resistances of the first bias current, the second bias current, and the third bias current, the first current mirror circuit 123, the second current mirror circuit 124, and the third current mirror circuit 125; the negative temperature coefficient voltage V _ctat is generated from the voltage inversely proportional to the temperature, the equivalent voltages of the first current mirror circuit 123, the second current mirror circuit 124, and the third current mirror circuit 125.

Specifically, the bias current generating circuit 121 may generate a bias current for use as a self-bias current source to provide a current bias to the entire circuit. The MOS transistor 122 operating in the subthreshold region generates a voltage inversely proportional to temperature, and compared with the MOS transistor operating in the saturation region, the MOS transistor 122 operating in the subthreshold region has a smaller current flowing therethrough, thereby effectively reducing the power consumption of the circuit. The first current mirror circuit 123 is configured to copy the bias current generated by the bias current generation circuit 121 at a predetermined ratio to generate a first bias current. The second current mirror circuit 124 is configured to copy the bias current generated by the bias current generating circuit 121 at a predetermined ratio to generate a second bias current. The third current mirror circuit 125 is configured to copy the bias current generated by the bias current generating circuit 121 at a predetermined ratio to generate a third bias current. Specifically, the first current mirror circuit 123, the second current mirror circuit 124, and the third current mirror circuit 125 can accurately reproduce the bias current generated by the bias current generating circuit 121 by controlling the sizes of the respective MOS transistors within a reasonable accuracy range, thereby providing currents of different proportions for the respective branch currents.

Further, based on the equivalent resistances of the first bias current, the second bias current, and the third bias current, the first current mirror circuit 123, the second current mirror circuit 124, and the third current mirror circuit 125, equivalent voltages of the first current mirror circuit 123, the second current mirror circuit 124, and the third current mirror circuit 125 are generated. Further, the negative temperature coefficient voltage V _ctat is generated from the voltage inversely proportional to the temperature, the equivalent voltages of the first current mirror circuit 123, the second current mirror circuit 124, and the third current mirror circuit 125. Specifically, the equivalent voltages of the first current mirror circuit 123, the second current mirror circuit 124, and the third current mirror circuit 125 are subtracted from the voltage inversely proportional to the temperature generated by the MOS transistor 122 operating in the sub-threshold region to obtain the negative temperature coefficient voltage V _ctat.

In the embodiment of the application, the bias current generating circuit 121 generates one path of bias current as a current source, so that the problems of enlarged circuit area and increased power consumption caused by using an additional current source are avoided. The MOS transistor 122 operating in the subthreshold region generates a voltage inversely proportional to temperature, and the first current mirror circuit 123, the second current mirror circuit 124, and the third current mirror circuit 125 replicate bias currents according to different ratios to generate a first bias current, a second bias current, and a third bias current. The voltage generating module 120 generates the negative temperature coefficient voltage V _ctat according to the equivalent voltages of the first current mirror circuit 123, the second current mirror circuit 124 and the third current mirror circuit 125 and the voltage of the MOS transistor 122 operating in the sub-threshold region, which is inversely proportional to the temperature, and the finally generated negative temperature coefficient voltage V _ctat is smaller and inversely proportional to the temperature, so that the requirement of low power consumption of the temperature sensor is well satisfied.

In one embodiment, as shown in fig. 2, the bias current generating circuit 121 includes a first NMOS transistor NM1 and a second NMOS transistor NM2.

The source of the first NMOS transistor NM1 is grounded, the drain of the first NMOS transistor NM1 is electrically connected to the source of the second NMOS transistor NM2, the drain of the second NMOS transistor NM2 is electrically connected to the first current mirror circuit 123, and the gate of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2 are electrically connected to the MOS transistor 122 operating in the sub-threshold region.

Specifically, the bias current generating circuit 121 is composed of N-channel depletion type MOS transistors, that is, the first NMOS transistor NM1 and the second NMOS transistor NM2 are both N-channel depletion type MOS transistors. The turn-on characteristic of an N-channel MOS (NMOS) transistor is specifically that the NMOS transistor is turned on when the gate-source voltage of the NMOS transistor is greater than a certain value, and is adapted to the case that the source is grounded, that is, low-side driving. The NMOS transistor is divided into an N-channel depletion type MOS transistor and an N-channel enhancement type MOS transistor, the N-channel enhancement type MOS transistor must apply a forward bias voltage to the gate, and the N-channel depletion type MOS transistor generates a conductive channel only when the gate-source voltage is greater than the threshold voltage, and the N-channel depletion type MOS transistor generates a conductive channel when the gate-source voltage is not applied (the gate-source voltage is zero). Further, the first NMOS transistor NM1 in the bias current generating circuit 121 uses its own voltage as bias, and generates a self-biased current source, which provides current bias for the whole circuit.

Further, the second NMOS transistor NM2 is a cascode structure, and the biggest characteristic of the cascode structure is that the output impedance is relatively large, and in addition, the drain-source voltage of the cascode transistor is insensitive to the output voltage, that is, even when the output load of the cascode structure changes greatly, the change of the source-drain voltage of the cascode transistor is small. Therefore, the second NMOS transistor NM2 further improves the linearity of the current source.

In the embodiment of the present application, the bias current generating circuit 121 includes a first NMOS transistor NM1 and a second NMOS transistor NM2, where the first NMOS transistor NM1 is configured to generate a current source with a self-bias by using its own voltage as a bias, so as to provide a current bias for the whole circuit, thereby reducing the circuit area and reducing the circuit power consumption. The second NMOS transistor NM2 is a cascode MOS transistor, and the output impedance of the cascode structure is relatively large, and the drain-source voltage is insensitive to the output voltage, so that the linearity of the current source is further improved.

In one embodiment, as shown in fig. 2, the MOS transistor 122 operating in the sub-threshold region includes a third NMOS transistor NM3 and a fourth NMOS transistor NM4.

The source of the third NMOS transistor NM3 is grounded, the drain of the third NMOS transistor NM3 is electrically connected to the source of the fourth NMOS transistor NM4, the drain of the third NMOS transistor NM3 is electrically connected to the gate of the first NMOS transistor NM1, the drain of the fourth NMOS transistor NM4 is electrically connected to the gate of the third NMOS transistor NM3, the gate of the second NMOS transistor NM2 is electrically connected to the gate of the fourth NMOS transistor NM4, and the drain of the fourth NMOS transistor NM4 is electrically connected to the second current mirror circuit 124.

Specifically, the MOS transistor 122 operating in the subthreshold region is composed of an N-channel depletion MOS transistor, that is, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are N-channel depletion MOS transistors.

In the embodiment of the present application, the MOS transistor 122 operating in the subthreshold region includes a third NMOS transistor NM3 and a fourth NMOS transistor NM4. Since the MOS transistor 122 operating in the sub-threshold region flows a smaller current, the power consumption of the circuit is effectively reduced.

In one embodiment, as shown in fig. 2, the first current mirror circuit 123 includes a fifth PMOS transistor PM5 and a sixth PMOS transistor PM6, the second current mirror circuit 124 includes a seventh PMOS transistor PM7 and an eighth PMOS transistor PM8, and the third current mirror circuit 125 includes a ninth PMOS transistor PM9 and a tenth PMOS transistor PM10; the drain of the fifth PMOS transistor PM5, the drain of the eighth PMOS transistor PM8, the drain of the tenth PMOS transistor PM10 are electrically connected to an external power supply, the source of the sixth PMOS transistor PM6 is electrically connected to the drain of the fifth PMOS transistor PM5, and the source of the fifth PMOS transistor PM5 is electrically connected to the drain of the second NMOS transistor NM 2; the source of the eighth PMOS transistor PM8 is electrically connected to the drain of the seventh PMOS transistor PM7, the source of the seventh PMOS transistor PM7 is electrically connected to the drain of the fourth NMOS transistor NM4, the source of the tenth PMOS transistor PM10 is electrically connected to the drain of the ninth PMOS transistor PM9, the source of the ninth PMOS transistor PM9 is electrically connected to the source of the fourth NMOS transistor NM4, the gate of the sixth PMOS transistor PM6 is electrically connected to the source of the sixth PMOS transistor PM6, the gates of the sixth PMOS transistor PM6 are electrically connected to the gates of the eighth PMOS transistor PM8 and the tenth PMOS transistor PM10, respectively, the gate of the fifth PMOS transistor PM5 is electrically connected to the source of the fifth PMOS transistor PM5, and the gates of the fifth PMOS transistor PM5 are electrically connected to the gates of the seventh PMOS transistor PM7 and the ninth PMOS transistor PM9, respectively.

Specifically, the first current mirror circuit 123, the second current mirror circuit 124, and the third current mirror circuit 125 are composed of P-channel depletion type MOS transistors, that is, the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, the eighth PMOS transistor PM8, the ninth PMOS transistor PM9, and the tenth PMOS transistor PM10 are all P-channel depletion type MOS transistors. The on-state characteristic of the P-channel MOS (PMOS) transistor is specifically that the PMOS transistor is turned on when the gate-source voltage of the PMOS transistor is smaller than a certain value, and is suitable for the case that the source is connected to the power supply, that is, the high-side driving. Further, PMOS transistors are classified into a P-channel depletion type MOS transistor and a P-channel enhancement type MOS transistor, and when a positive voltage is applied to a gate (source is grounded), the P-channel enhancement type MOS transistor can form a channel connecting between a source and a drain, and the resistance of the channel is changed by changing a gate tooth. The P-channel depletion MOS transistor has a channel connected between the source and the drain without applying a gate voltage, and the resistance of the channel can be increased or decreased by applying an appropriate bias voltage.

Further, the first current mirror circuit 123, the second current mirror circuit 124, and the third current mirror circuit 125 are cascode current mirrors, and the drain-source voltages of the cascode current mirrors are insensitive to the output voltage variation, so that the influence of the channel length modulation can be effectively suppressed, and thus the bias currents generated by the bias current generating circuit 121 can be more accurately duplicated by the first current mirror circuit 123, the second current mirror circuit 124, and the third current mirror circuit 125.

In the embodiment of the present application, the first current mirror circuit 123, the second current mirror circuit 124 and the third current mirror circuit 125 can copy the bias current generated by the bias current generating circuit 121 to provide different proportions of current for each branch current by controlling the size of each MOS transistor within a reasonable precision range. In addition, since the first current mirror circuit 123, the second current mirror circuit 124 and the third current mirror circuit 125 are cascode current mirrors, more accurate current can be provided for each branch, and thus the measurement accuracy of the temperature sensor to the temperature is improved to a certain extent.

In one embodiment, fig. 3 is a block diagram of the voltage compensation module 140 in one embodiment, and as shown in fig. 3, a block diagram of the voltage compensation module 140 is provided, including a fourth current mirror circuit 142, a differential pair 144 operating in a subthreshold region, and a fifth current mirror circuit 146.

Specifically, the fourth current mirror circuit 142 and the fifth current mirror circuit 146 can accurately replicate the current by adjusting the width-to-length ratio of the MOS transistor, and provide the corresponding proportion of current to the branch circuit in the voltage compensation module 140. The differential pair 144, operating in the subthreshold regime, functions like a bandgap reference, widely including a voltage reference and a current reference in analog circuits, such references being direct current, which has little relationship to power and process parameters, but a deterministic relationship to temperature. The bandgap reference is a voltage reference that is independent of temperature by using the sum of a voltage with a positive temperature coefficient and a voltage with a negative temperature coefficient, where the temperature coefficients cancel each other out, thereby removing the temperature effects.

In the embodiment of the application, a voltage compensation module 140 is provided, which includes a fourth current mirror circuit 142, a differential pair 144 working in a subthreshold region and a fifth current mirror circuit 146, and generates a voltage which is irrelevant to temperature through the differential pair 144 working in the subthreshold region, so that voltage compensation can be performed on the negative temperature coefficient voltage V _ctat generated by the voltage generation module 120, thereby eliminating the influence caused by process deviation and further improving the measurement accuracy of the temperature sensor on temperature.

In one embodiment, as shown in fig. 3, a fourth current mirror circuit 142 is configured to replicate the bias currents in different proportions to generate a fourth bias current; the fifth current mirror circuit 146 is a basic current mirror for generating a fifth bias current according to the negative temperature coefficient voltage V _ctat; the voltage compensation module 140 is configured to input a fourth bias current and a fifth bias current to the differential pair 144 operating in the subthreshold region, and generate a first output voltage of the differential pair and a second output voltage of the differential pair; a temperature independent compensation voltage V _bgr is generated based on the first output voltage of the differential pair and the second output voltage of the differential pair.

Specifically, the fourth current mirror circuit 142 is a cascode current mirror, which can effectively inhibit the influence of channel length modulation in the MOS transistor, and improve the accuracy of the replica current, so as to generate the fourth bias current. The fifth current mirror circuit 146 is a basic current mirror for providing current to the branch of the voltage compensation module 140 and generating a fifth bias current according to the inputted negative temperature coefficient voltage V _ctat. Further, the voltage compensation module 140 is configured to input the fourth bias current and the fifth bias current to the differential pair 144 operating in the subthreshold region, generate a first output voltage of the differential pair and a second output voltage of the differential pair, cancel a temperature coefficient between the first output voltage and the second output voltage by making a difference between the first output voltage and the second output voltage, implement a voltage reference independent of temperature, and generate a compensation voltage V _bgr independent of temperature.

In the embodiment of the present application, the fourth bias current generated by the fourth current mirror circuit 142 and the fifth bias current generated by the fifth current mirror circuit 146 are respectively input into the differential pair 144 operating in the subthreshold region, and then the differential pair 144 operating in the subthreshold region generates the first output voltage and the second output voltage, and the first output voltage and the second output voltage of the differential pair are subtracted, so that the influence of the temperature coefficient can be eliminated, and finally the compensation voltage V _bgr irrelevant to the temperature is generated. The obtained temperature-independent compensation voltage V _bgr can carry out voltage compensation on the negative temperature coefficient voltage V _ctat, so that the influence caused by process deviation is eliminated, and the accuracy of the temperature sensor is improved.

In one embodiment, as shown in fig. 3, the differential pair 144 operating in the subthreshold region includes an eleventh PMOS transistor PM11 and a twelfth PMOS transistor PM12. The gate of the eleventh PMOS transistor PM11 is electrically connected to the output terminal of the voltage generating module 120, the drain of the eleventh PMOS transistor PM11 and the drain of the twelfth PMOS transistor PM12 are electrically connected to the fourth current mirror circuit 142, and the source of the eleventh PMOS transistor PM11 and the source of the twelfth PMOS transistor PM12 are electrically connected to the fifth current mirror circuit 146.

Specifically, the differential pair 144 operating in the subthreshold regime cancels out the temperature dependent coefficient by taking the difference between the input and output voltages, thereby generating a temperature independent compensation voltage V _bgr. Further, the gate of the eleventh PMOS transistor PM11 is electrically connected to the source of the ninth PMOS transistor PM9, the drain of the eleventh PMOS transistor PM11 and the drain of the twelfth PMOS transistor PM12 are electrically connected to the fourth current mirror circuit 142, and the source of the eleventh PMOS transistor PM11 and the source of the twelfth PMOS transistor PM12 are electrically connected to the fifth current mirror circuit 146.

In the embodiment of the present application, the temperature independent compensation voltage V _bgr is generated by the differential pair 144 operating in the subthreshold region. The obtained temperature-independent compensation voltage V _bgr can carry out voltage compensation on the negative temperature coefficient voltage V _ctat, so that the influence caused by process deviation is eliminated, and the accuracy of the temperature sensor is improved.

In one embodiment, as shown in fig. 3, the fourth current mirror circuit 142 includes a fifteenth PMOS transistor PM15 and a sixteenth PMOS transistor PM16.

The drain of the sixteenth PMOS transistor PM16 is electrically connected to the external power supply, the source of the sixteenth PMOS transistor PM16 is electrically connected to the drain of the fifteenth PMOS transistor PM15, the source of the fifteenth PMOS transistor PM15 is electrically connected to the drain of the eleventh PMOS transistor PM11, the gate of the sixteenth PMOS transistor PM16 is electrically connected to the voltage generation module 120, and the gate of the fifteenth PMOS transistor is electrically connected to the voltage generation module 120.

Specifically, the fourth current mirror circuit 142 is a cascode current mirror that provides a fourth bias current to the differential pair 144 operating in the subthreshold region by accurately replicating a corresponding proportion of the current. Further, the drain of the sixteenth PMOS transistor PM16 is electrically connected to the external power supply, the source of the sixteenth PMOS transistor PM16 is electrically connected to the drain of the fifteenth PMOS transistor PM15, the source of the fifteenth PMOS transistor PM15 is electrically connected to the drain of the eleventh PMOS transistor PM11, the gate of the sixteenth PMOS transistor PM16 is electrically connected to the gate of the sixth PMOS transistor PM6, and the gate of the fifteenth PMOS transistor PM5 is electrically connected to the gate of the fifth PMOS transistor PM 5.

In the embodiment of the application, the fourth current mirror circuit 142 can accurately copy the bias current in the voltage generation module 120, so that the current copy precision is improved, and further, the measurement precision of the temperature sensor is improved.

In one embodiment, as shown in fig. 3, the fifth current mirror circuit 146 includes a thirteenth NMOS transistor NM13 and a fourteenth NMOS transistor NM14.

The drain of the thirteenth NMOS transistor NM13 and the gate of the thirteenth NMOS transistor NM13 are electrically connected to the source of the eleventh PMOS transistor PM11, the source of the thirteenth NMOS transistor NM13 is grounded, the source of the twelfth PMOS transistor NM12 is electrically connected to the drain of the fourteenth NMOS transistor NM14, the gate of the fourteenth NMOS transistor NM14 is electrically connected to the gate of the thirteenth NMOS transistor NM13, and the source of the fourteenth NMOS transistor NM14 is grounded.

Specifically, the fifth current mirror circuit 146 is a basic current mirror that copies a corresponding proportion of current to provide a fifth bias current to the differential pair 144 operating in the subthreshold region.

In the embodiment of the present application, the fifth current mirror 146 can replicate the bias current in the voltage generating module 120, thereby reducing the use of external current sources and further reducing the power consumption of the temperature sensor.

In a specific embodiment, fig. 4 is a schematic diagram of a temperature sensor in a specific embodiment, and as shown in fig. 4, the temperature sensor includes a voltage generating module 120, a voltage compensating module 140, and an output module.

Specifically, the voltage generation module 120 includes a bias current generation circuit 121, a MOS transistor 122 operating in a sub-threshold region, a first current mirror circuit 123, a second current mirror circuit 124, and a third current mirror circuit 125; the first current mirror circuit 123, the second current mirror circuit 124, and the third current mirror circuit 125 are cascode current mirrors. The voltage compensation module 140 includes a fourth current mirror circuit 142, a differential pair 144 operating in the subthreshold regime, and a fifth current mirror circuit 146.

Further, the bias current generating circuit 121 includes a first NMOS transistor NM1 and a second NMOS transistor NM2. The source of the first NMOS transistor NM1 is grounded, the drain of the first NMOS transistor NM1 is electrically connected to the source of the second NMOS transistor NM2, the drain of the second NMOS transistor NM2 is electrically connected to the first current mirror circuit 123, and the gate of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2 are electrically connected to the MOS transistor 122 operating in the sub-threshold region. The first NMOS transistor NM1 in the bias current generating circuit 121 generates a self-biased current source by using its own voltage as bias, and provides a current bias for the whole circuit, and the bias current generated by the first NMOS transistor NM1 is:

Φ_t＝kT/q (2)

Wherein I _s1 is the normalized current of the first NMOS transistor NM1, V _ctat is the negative temperature coefficient voltage V _ctat,V_T1 generated by the voltage generation module 120 is the threshold voltage of the first NMOS transistor NM1, n ₁ is the subthreshold slope coefficient of the first NMOS transistor NM1, Φ _t is the thermoelectric potential, k is the boltzmann constant, T is the temperature, and q is the unit charge.

Further, the MOS transistor 122 operating in the sub-threshold region includes a third NMOS transistor NM3 and a fourth NMOS transistor NM4. The source of the third NMOS transistor NM3 is grounded, the drain of the third NMOS transistor NM3 is electrically connected to the source of the fourth NMOS transistor NM4, the drain of the third NMOS transistor NM3 is electrically connected to the gate of the first NMOS transistor NM1, the drain of the fourth NMOS transistor NM4 is electrically connected to the gate of the third NMOS transistor NM3, the gate of the second NMOS transistor NM2 is electrically connected to the gate of the fourth NMOS transistor NM4, and the drain of the fourth NMOS transistor NM4 is electrically connected to the second current mirror circuit 124.

The drain current of the third NMOS transistor NM3 or the fourth NMOS transistor NM4 in the sub-threshold region may be expressed as:

Wherein I _S＝I_SQ(W/L),I_S is a source current of the third NMOS transistor NM3 or the fourth NMOS transistor NM4, I _SQ is a normalized current of the third NMOS transistor NM3 or the fourth NMOS transistor NM4, specifically denoted as I _SQ＝μC'_OXn(Φ_t ²/2), μ is a carrier mobility, n is a sub-threshold slope coefficient, C' _OX is a gate capacitance per unit area, W is a width of the third NMOS transistor NM3 or the fourth NMOS transistor NM4, L is a length of the third NMOS transistor NM3 or the fourth NMOS transistor NM4, V _G is a gate voltage of the third NMOS transistor NM3 or the fourth NMOS transistor NM4, V _T is a threshold voltage of the third NMOS transistor NM3 or the fourth NMOS transistor NM4, and V _S is a source voltage of the third NMOS transistor NM3 or the fourth NMOS transistor NM 4. Compared with the MOS which normally works in the saturation region, the MOS transistor 122 which works in the subthreshold region has smaller current, the branch current is lower than 1nA, and the requirement of low power consumption is well met.

Further, the first current mirror circuit 123 includes a fifth PMOS transistor PM5 and a sixth PMOS transistor PM6, the second current mirror circuit 124 includes a seventh PMOS transistor PM7 and an eighth PMOS transistor PM8, and the third current mirror circuit 125 includes a ninth PMOS transistor PM9 and a tenth PMOS transistor PM10; the drain of the fifth PMOS transistor PM5, the drain of the eighth PMOS transistor PM8, the drain of the tenth PMOS transistor PM10 are electrically connected to an external power supply, the source of the sixth PMOS transistor PM6 is electrically connected to the drain of the fifth PMOS transistor PM5, and the source of the fifth PMOS transistor PM5 is electrically connected to the drain of the second NMOS transistor NM 2; the source of the eighth PMOS transistor PM8 is electrically connected to the drain of the seventh PMOS transistor PM7, the source of the seventh PMOS transistor PM7 is electrically connected to the drain of the fourth NMOS transistor NM4, the source of the tenth PMOS transistor PM10 is electrically connected to the drain of the ninth PMOS transistor PM9, the source of the ninth PMOS transistor PM9 is electrically connected to the source of the fourth NMOS transistor NM4, the gate of the sixth PMOS transistor PM6 is electrically connected to the source of the sixth PMOS transistor PM6, the gates of the sixth PMOS transistor PM6 are electrically connected to the gates of the eighth PMOS transistor PM8 and the tenth PMOS transistor PM10, respectively, the gate of the fifth PMOS transistor PM5 is electrically connected to the source of the fifth PMOS transistor PM5, and the gates of the fifth PMOS transistor PM5 are electrically connected to the gates of the seventh PMOS transistor PM7 and the ninth PMOS transistor PM9, respectively.

Assuming that the current flowing through the sixth PMOS transistor PM6 is I ₆, the currents flowing through the eighth PMOS transistor PM8 and the tenth PMOS transistor PM10 are αi ₆ and βi ₆, respectively, where α, β are real numbers between 0 and 1. The currents of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 of the MOS transistor 122 operating in the sub-threshold region are I _D3 and I _D4, respectively, specifically expressed as:

I_D3＝(α+β)I₆ (4)

I_D4＝αI₆ (5)

V_G3＝V_G4 (6)

Wherein V _G3 is the gate voltage of the third NMOS transistor NM3, V _G4 is the gate voltage of the fourth NMOS transistor NM4, and further, the negative temperature coefficient voltage V _ctat generated by the voltage generating module 120 is:

where n3 is the sub-threshold slope coefficient of the third NMOS transistor NM3, n4 is the sub-threshold slope coefficient of the fourth NMOS transistor NM4, V _T3 is the threshold voltage of the third NMOS transistor NM3, V _T4 is the threshold voltage of the fourth NMOS transistor NM4, I _s3 is the normalized current of the third NMOS transistor NM3, and I _s4 is the normalized current of the fourth NMOS transistor NM 4. As can be seen from the formula (7), the threshold voltage V _T3 of the third NMOS transistor NM3 is greater than the threshold voltage V _T4 of the fourth NMOS transistor NM 4. After bringing formula (3) into formula (7), it is possible to obtain:

wherein, As can be seen from equation (8), since the coefficient of Φ _t is a negative number, the generated negative temperature coefficient voltage V _ctat is linearly inversely related to temperature.

The voltage generation module generation 120 has great advantages in area and power consumption, but the operating voltage of the MOS device is affected by process deviation, thereby affecting the performance of the circuit. Fig. 5 is a schematic diagram of the negative temperature coefficient voltage V _ctat at different process angles according to an embodiment, and fig. 5 shows the variation of the negative temperature coefficient voltage V _ctat at SS, SNFP, TT, FNSP, FF at five process angles, and the coordinate axes are temperature-voltage. As can be seen from fig. 5, the negative temperature coefficient voltage V _ctat at different process corners maintains a better linearity and a more uniform slope, whereas the ordinate of the negative temperature coefficient voltage V _ctat curve at each process corner differs by a fixed value. As can be seen from equation (8), the linearity and slope of the negative temperature coefficient voltage V _ctat curve are determined by the term Φ _t, and since Φ _t is a negative number, the negative temperature coefficient voltage V _ctat is inversely proportional to temperature. However, the V _T component in the formula (8) causes a fixed difference in the negative temperature coefficient voltage V _ctat curve at the ordinate, because the MOS transistor is affected by different process means, so that the threshold voltage of the MOS transistor is affected by process deviation, and a certain difference is shown at different process angles.

Further, the voltage compensation module 140 includes a fourth current mirror circuit 142, a differential pair 144 operating in a subthreshold region, and a fifth current mirror circuit 146.

Further, the fourth current mirror circuit 142 includes a fifteenth PMOS transistor PM15 and a sixteenth PMOS transistor PM16. The drain of the sixteenth PMOS transistor PM16 is electrically connected to the external power supply, the source of the sixteenth PMOS transistor PM16 is electrically connected to the drain of the fifteenth PMOS transistor PM15, the source of the fifteenth PMOS transistor PM15 is electrically connected to the drain of the eleventh PMOS transistor PM11, the gate of the sixteenth PMOS transistor PM16 is electrically connected to the gate of the sixth PMOS transistor PM6, and the gate of the fifteenth PMOS transistor PM5 is electrically connected to the gate of the fifth PMOS transistor PM 5.

Further, the fifth current mirror circuit 146 includes a thirteenth NMOS transistor NM13 and a fourteenth NMOS transistor NM14. The drain of the thirteenth NMOS transistor NM13 and the gate of the thirteenth NMOS transistor NM13 are electrically connected to the source of the eleventh PMOS transistor PM11, the source of the thirteenth NMOS transistor NM13 is grounded, the source of the twelfth PMOS transistor NM12 is electrically connected to the drain of the fourteenth NMOS transistor NM14, the gate of the fourteenth NMOS transistor NM14 is electrically connected to the gate of the thirteenth NMOS transistor NM13, and the source of the fourteenth NMOS transistor NM14 is grounded.

Further, the differential pair 144 operating in the sub-threshold region includes an eleventh PMOS transistor PM11 and a twelfth PMOS transistor PM12. The gate of the eleventh PMOS transistor PM11 is electrically connected to the source of the ninth PMOS transistor PM9, the drain of the eleventh PMOS transistor PM11 and the drain of the twelfth PMOS transistor PM12 are electrically connected to the fourth current mirror circuit 142, and the source of the eleventh PMOS transistor PM11 and the source of the twelfth PMOS transistor PM12 are electrically connected to the fifth current mirror circuit 146, respectively. The temperature independent compensation voltage V _bgr is obtained by the differential pair 144 operating in the subthreshold regime, denoted as:

Where k=w/L, W is the width of the MOS transistor, L is the length of the MOS transistor, and K ₁₁、K₁₂、K₁₃、K₁₄ is the K values of the eleventh PMOS transistor PM11, the twelfth PMOS transistor PM12, the thirteenth NMOS transistor NM13, and the fourteenth NMOS transistor NM14, respectively. As can be seen from the formula (9), the temperature-independent compensation voltage V _bgr can be obtained by adjusting the K values of the eleventh PMOS transistor PM11, the twelfth PMOS transistor PM12, the thirteenth NMOS transistor NM13, and the fourteenth NMOS transistor NM 14.

Fig. 6 is a schematic diagram of the compensation voltage V _bgr at different process angles according to an embodiment, and fig. 6 shows the variation of the compensation voltage V _bgr at SS, SNFP, TT, FNSP, FF at five process angles, and the coordinate axis is temperature-voltage. As can be seen from fig. 6, the compensation voltage V _bgr at SS, SNFP, TT, FNSP, FF five process angles is independent of temperature. the negative temperature coefficient voltage V _ctat can be compensated by the compensation voltage V _bgr, and the compensation voltage V _bgr and the negative temperature coefficient voltage V _ctat are input into the output module to obtain the positive temperature coefficient voltage. Fig. 7 is a schematic diagram of ptc voltage at different process angles according to an embodiment, and fig. 7 shows ptc voltage variation at SS, SNFP, TT, FNSP, FF process angles, with the coordinate axes being temperature-voltage. As can be seen from fig. 7, the positive temperature coefficient voltage obtained after compensation has a positive linear ratio relationship with temperature, and is less affected by process deviation. This is because the compensation voltage V _bgr contains the V _T component of the negative temperature coefficient voltage V _ctat, the compensation voltage V _bgr and the negative temperature coefficient voltage V _ctat are differentiated by the output module, The component V _T of the negative temperature coefficient voltage V _ctat is counteracted, and the positive temperature coefficient voltage obtained after compensation effectively eliminates the influence caused by process deviation. Fig. 8 is a schematic diagram of ptc voltage errors at different process angles in an embodiment, and fig. 8 shows ptc voltage errors at four process angles SS, SNFP, FNSP, FF with ptc voltage at TT as a reference, and the coordinate axes are temperature-voltage differences. As can be seen from fig. 8, the positive temperature coefficient voltage error range is controlled between-3 ℃ and 3 ℃ at different process angles in the temperature range between-10 ℃ and 70 ℃. Therefore, the positive temperature coefficient voltage obtained after the negative temperature coefficient voltage V _ctat is subjected to voltage compensation by the compensation voltage V _bgr can effectively remove the influence caused by process deviation.

Table 1 shows the comparison of the temperature sensor according to the present application and the comparison technology in one embodiment, and Table 1 shows the comparison of the parameters of the temperature sensor according to the present application and the comparison technology. As shown in Table 1, the design is based on UMC ULP 55nm technology, the whole area of the temperature sensor circuit is only 231um ², the power consumption is only 25nw, and the temperature sensor is far lower than that of the temperature sensor of the comparison technology. In addition, the measurement error of the temperature sensor can be controlled between-2.9 ℃ and 2.9 ℃ which is far smaller than that of the temperature sensor of the comparison technology. Compared with the comparison technology, the temperature sensor has the advantages of small circuit area, low power consumption and high measurement precision.

TABLE 1

Parameters (parameters)	The application is that	Contrast technique
			Art (nm)	55	65
Power supply voltage (V)	2.5	0.6～1.0
			Core device	CMOS	CMOS
Power consumption (nw)	25	360
			Area (um ²)	231	279
Range (. Degree. C.)	-10～70	0～100
			Error (. Degree. C.)	-2.9～2.9	-3.4～3.6

In one embodiment, fig. 9 is a block diagram of an integrated circuit in one embodiment, as shown in fig. 9, providing an integrated circuit 200 including a temperature sensor 100 for implementing any of the above embodiments.

Specifically, the integrated circuit 200 may be a chip, and may be specifically applied to the technical fields of power testing and the like. The provided integrated circuit 200 includes a temperature sensor 100 including a voltage generation module 120, a voltage compensation module 140, and an output module 160. Wherein the input end of the voltage generation module 120 is electrically connected with the external power supply 180; the voltage generation module 120 is configured to generate a negative temperature coefficient voltage inversely proportional to temperature; the output end of the voltage generation module 120 is electrically connected with the input end of the voltage compensation module 140; the voltage compensation module 140 is configured to compensate the negative temperature coefficient voltage to generate a compensation voltage independent of temperature; the output end of the voltage generation module 120 and the output end of the voltage compensation module 140 are electrically connected with the input end of the output module 160; the output module 160 is configured to output a positive temperature coefficient voltage according to the compensation voltage and the negative temperature coefficient voltage.

In the embodiments of the application, an integrated circuit 200 is provided that includes a temperature sensor 100 for implementing any of the embodiments provided above, the integrated circuit 200 provided can implement accurate measurement of temperature, and the integrated circuit 200 has a small area and low power consumption.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims

1. A temperature sensor is characterized by comprising a voltage generating module, a voltage compensating module and an output module, wherein,

The input end of the voltage generation module is electrically connected with an external power supply; the voltage generation module is used for generating negative temperature coefficient voltage inversely proportional to temperature;

The output end of the voltage generation module is electrically connected with the input end of the voltage compensation module; the voltage compensation module is used for compensating the negative temperature coefficient voltage and generating a compensation voltage irrelevant to temperature;

the output end of the voltage generation module and the output end of the voltage compensation module are electrically connected with the input end of the output module; the output module is used for outputting positive temperature coefficient voltage according to the compensation voltage and the negative temperature coefficient voltage;

The voltage compensation module comprises a fourth current mirror circuit, a differential pair working in a subthreshold region and a fifth current mirror circuit;

the fourth current mirror circuit is used for copying the bias current according to different proportions to generate a fourth bias current;

the fifth current mirror circuit is a basic current mirror and is used for generating a fifth bias current according to the negative temperature coefficient voltage;

The voltage compensation module is used for inputting the fourth bias current and the fifth bias current to the differential pair working in the subthreshold region to generate a first output voltage of the differential pair and a second output voltage of the differential pair;

the temperature independent compensation voltage is generated based on the first output voltage of the differential pair and the second output voltage of the differential pair.

2. The temperature sensor of claim 1, wherein the voltage generation module comprises a bias current generation circuit, a MOS transistor operating in a sub-threshold region, a first current mirror circuit, a second current mirror circuit, and a third current mirror circuit; the first current mirror circuit, the second current mirror circuit and the third current mirror circuit are cascode current mirrors.

3. The temperature sensor of claim 2, wherein the bias current generating circuit is configured to generate a bias current;

The MOS transistor working in the subthreshold region is used for generating voltage inversely proportional to temperature;

The first current mirror circuit, the second current mirror circuit and the third current mirror circuit are used for copying the bias current according to different proportions to generate a first bias current, a second bias current and a third bias current;

The voltage generation module is configured to generate equivalent voltages corresponding to the first current mirror circuit, the second current mirror circuit, and the third current mirror circuit based on equivalent resistances of the first bias current, the second bias current, and the third bias current, and the first current mirror circuit, the second current mirror circuit, and the third current mirror circuit;

And generating the negative temperature coefficient voltage according to the voltage inversely proportional to the temperature and the equivalent voltage.

4. A temperature sensor according to claim 2 or 3, wherein the bias current generating circuit comprises a first NMOS transistor and a second NMOS transistor;

5. The temperature sensor of claim 4, wherein the MOS transistors operating in the sub-threshold region comprise a third NMOS transistor and a fourth NMOS transistor;

The source electrode of the third NMOS transistor is grounded, the drain electrode of the third NMOS transistor is electrically connected with the source electrode of the fourth NMOS transistor, the drain electrode of the third NMOS transistor is electrically connected with the gate electrode of the first NMOS transistor, the drain electrode of the fourth NMOS transistor is electrically connected with the gate electrode of the third NMOS transistor, the gate electrode of the second NMOS transistor is electrically connected with the gate electrode of the fourth NMOS transistor, and the drain electrode of the fourth NMOS transistor is electrically connected with the second current mirror circuit.

6. The temperature sensor of claim 5, wherein the first current mirror circuit comprises a fifth PMOS transistor and a sixth PMOS transistor, the second current mirror circuit comprises a seventh PMOS transistor and an eighth PMOS transistor, and the third current mirror circuit comprises a ninth PMOS transistor and a tenth PMOS transistor;

The drain electrode of the fifth PMOS transistor, the drain electrode of the eighth PMOS transistor, the drain electrode of the tenth PMOS transistor are electrically connected with the external power supply, the source electrode of the sixth PMOS transistor is electrically connected with the drain electrode of the fifth PMOS transistor, and the source electrode of the fifth PMOS transistor is electrically connected with the drain electrode of the second NMOS transistor;

The source of the tenth PMOS transistor is electrically connected with the drain of the ninth PMOS transistor, and the source of the ninth PMOS transistor is electrically connected with the source of the fourth NMOS transistor;

The gate of the sixth PMOS transistor is electrically connected to the source of the sixth PMOS transistor, the gate of the sixth PMOS transistor is electrically connected to the gate of the eighth PMOS transistor and the gate of the tenth PMOS transistor, the gate of the fifth PMOS transistor is electrically connected to the source of the fifth PMOS transistor, and the gate of the fifth PMOS transistor is electrically connected to the gate of the seventh PMOS transistor and the gate of the ninth PMOS transistor, respectively.

7. The temperature sensor of claim 1, wherein the differential pair operating in the sub-threshold region comprises an eleventh PMOS transistor and a twelfth PMOS transistor;

the grid electrode of the eleventh PMOS transistor is electrically connected with the output end of the voltage generation module respectively, the drain electrode of the eleventh PMOS transistor and the drain electrode of the twelfth PMOS transistor are electrically connected with the fourth current mirror circuit, and the source electrode of the eleventh PMOS transistor and the source electrode of the twelfth PMOS transistor are electrically connected with the fifth current mirror circuit.

8. The temperature sensor of claim 7, wherein the fourth current mirror circuit comprises a fifteenth PMOS transistor and a sixteenth PMOS transistor;

The drain of the sixteenth PMOS transistor is electrically connected to the external power supply, the source of the sixteenth PMOS transistor is electrically connected to the drain of the fifteenth PMOS transistor, the source of the fifteenth PMOS transistor is electrically connected to the drain of the eleventh PMOS transistor, the gate of the sixteenth PMOS transistor is electrically connected to the voltage generation module, and the gate of the fifteenth PMOS transistor is electrically connected to the voltage generation module.

9. The temperature sensor of claim 7, wherein the fifth current mirror circuit comprises a thirteenth NMOS transistor and a fourteenth NMOS transistor;

10. An integrated circuit comprising the temperature sensor of any one of claims 1-9.