CN114334906B - A method for preparing an overlay mark - Google Patents
A method for preparing an overlay mark Download PDFInfo
- Publication number
- CN114334906B CN114334906B CN202011058736.6A CN202011058736A CN114334906B CN 114334906 B CN114334906 B CN 114334906B CN 202011058736 A CN202011058736 A CN 202011058736A CN 114334906 B CN114334906 B CN 114334906B
- Authority
- CN
- China
- Prior art keywords
- overlay mark
- mask layer
- layer
- window
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
本发明公开了一种套刻标记的制备方法，属于集成电路制备工艺技术领域。它包括提供衬底，衬底上形成有金属层；图形化金属层以获得位于衬底表面的套刻标记区；形成掩模层于金属层上，掩模层上与套刻标记区相对应的位置形成有悬垂的图形窗口，且图形窗口与待制备的套刻标记的形状一致；以掩模层为掩模，通过图形窗口蒸镀标记材料于套刻标记区；去除掩模层，套刻标记区上的标记材料形成套刻标记，从而解决现有技术中直接在晶圆(Wafer)上的铝膜等金属表面蒸镀贵金属Au等制作套刻标记时所产生的黑点、腐蚀痕迹等问题。
The invention discloses a method for preparing an overlay mark, belonging to the technical field of integrated circuit preparation process. It includes providing a substrate, on which a metal layer is formed; patterning the metal layer to obtain an overlay mark area located on the surface of the substrate; forming a mask layer on the metal layer, and forming a suspended graphic window at a position corresponding to the overlay mark area on the mask layer, and the graphic window is consistent with the shape of the overlay mark to be prepared; using the mask layer as a mask, evaporating a marking material in the overlay mark area through the graphic window; removing the mask layer, and forming an overlay mark with the marking material on the overlay mark area, thereby solving the problems of black spots, corrosion marks, etc. generated when the overlay mark is made by directly evaporating precious metal Au on the metal surface of an aluminum film or the like on a wafer in the prior art.
Description
Technical Field
The invention belongs to the technical field of integrated circuit preparation processes, and particularly relates to a preparation method of an overlay mark.
Background
In the preparation process of the superconducting quantum chip, a layer of aluminum film is generally plated on a Wafer (Wafer), then photoresist is coated, exposed, developed, etched and photoresist removed in sequence to form a control line, a coplanar waveguide transmission line and the like, and finally the Josephson junction is formed through the processes of photoresist coating, exposure, development, evaporation, photoresist removal and the like. In the above preparation process, as a very important step, the photolithography (photolithography) transfers the Mask pattern on the Mask plate (Mask) to the Wafer (Wafer) through a series of steps of alignment, exposure and the like, and the manufacturing of the superconducting quantum chip can be completed through multiple photolithography processes, even multiple photolithography processes.
In the patterning process, in order to achieve good performance of the chip, the lithography patterns on the wafer not only need to have accurate feature line width dimensions, but also need to align the positions between the upper layer of patterns and the lower layer of patterns by means of the Overlay mark, that is, when the alignment between the layer of lithography patterns (patterns on the wafer) and the front layer of lithography patterns (patterns on the wafer) needs to meet the requirement of Overlay Accuracy (Overlay Accuracy). Overlay accuracy refers to the position alignment error of the lithography patterns of the layers of the wafer, and the magnitude of the overlay accuracy reflects the magnitude of the position alignment deviation of the lithography patterns between different layers.
The shape of the overlay mark is related to the equipment used for the overlay, and for EBPG overlay, 20 μm squares are often used, and for JEOL6300 and laser direct write overlay, cross shapes of 3 μm wide and 20 μm long are often used. Currently, the method for preparing the overlay mark is to directly vapor-deposit noble metal Au or the like on the surface of a sample to prepare the overlay mark. However, the applicant found that if the overlay mark is made by vapor plating of noble metal Au or the like on the surface of an aluminum film on a Wafer (Wafer) based on this method, many black spots and corrosion marks are generated on the aluminum film, that is, by-products are generated to pollute the surface of a sample. Therefore, the current method for preparing the overlay mark is not suitable for the preparation process of the superconducting quantum chip.
Disclosure of Invention
In order to solve the defects in the prior art, the invention provides a preparation method of an overlay mark, which solves the problems that black spots and corrosion marks are generated when the overlay mark is manufactured by evaporating a noble metal Au and other marking materials on the surface of a metal layer such as an aluminum film on a Wafer (Wafer) at present so as to pollute the surface of a sample.
The application provides a preparation method of an overlay mark, which comprises the following steps:
Providing a substrate, wherein a metal layer is formed on the substrate;
patterning the metal layer to obtain an overlay mark region on the surface of the substrate;
Forming a mask layer on the metal layer, wherein a overhanging pattern window is formed on the mask layer at a position corresponding to the overlay mark region, and the pattern window is consistent with the shape of the overlay mark to be prepared;
Taking the mask layer as a mask, evaporating a marking material on the overlay marking area through the graphic window;
And removing the mask layer, and forming an overlay mark by the marking material on the overlay mark region.
Preferably, the patterning the metal layer to obtain an overlay mark region on the surface of the substrate includes:
forming a patterned resist layer on the metal layer, wherein an overlay mark region pattern is formed on the patterned resist layer;
and etching the metal layer by taking the patterned anti-corrosion layer as a mask to obtain an etching pattern, wherein the etching pattern comprises an overlay mark area positioned on the surface of the substrate.
The preparation method as described above, wherein preferably, the patterned resist layer is further formed with a josephson junction preparation region pattern and a control circuit pattern; the etched pattern further includes a Josephson junction preparation region and control lines on the surface of the substrate.
The method of making as described above, wherein preferably an undercut is formed between the patterned resist layer and the overlay mark region.
The above-mentioned preparation method, preferably, the forming a mask layer on the metal layer, where a overhanging pattern window is formed on the mask layer at a position corresponding to the overlay mark region, includes:
And forming a mask layer on the patterned resist layer, wherein a pattern window is formed in a position, corresponding to the pattern of the overlay mark region, on the mask layer, and the pattern window is in a suspension shape relative to the overlay mark region.
The above-mentioned preparation method, wherein preferably, the removing the mask layer, the marking material on the overlay mark region forms an overlay mark, includes:
Removing the mask layer;
and removing the patterned resist layer, and forming an overlay mark by the marking material on the overlay mark area.
Preferably, the forming a mask layer on the metal layer, forming a overhanging pattern window on the mask layer at a position corresponding to the overlay mark region, wherein the pattern window is consistent with the shape of the overlay mark to be prepared, and the forming comprises:
Providing a mask layer, wherein the mask layer is consistent with the shape of the substrate;
forming a graphic window on the mask layer at a position corresponding to the overlay mark region, wherein the window area of the graphic window is smaller than the area of the overlay mark region, and the shape of the graphic window is consistent with that of the overlay mark to be prepared;
And placing the mask layer on the metal layer, and enabling the pattern window which is hung to correspond to the overlay mark area.
The above preparation method, preferably, the first alignment structure is formed on the substrate, the second alignment structure matched with the first alignment structure is formed on the mask layer, the mask layer is placed on the metal layer, and the pattern window hanging on the overlay mark area corresponds to the pattern window, and the preparation method comprises the following steps:
the mask layer is placed on the metal layer, and the second alignment structure and the first alignment structure are aligned so that the graphic window corresponds to the position of the overlay mark region and is suspended relative to the overlay mark region.
The above-mentioned manufacturing method, wherein preferably, the placing the mask layer on the metal layer and aligning the second alignment structure and the first alignment structure so that the graphic window corresponds to the position of the overlay mark region and the graphic window is overhanging with respect to the overlay mark region, includes:
Providing a containing device, wherein the containing device is provided with a containing cavity, and the containing cavity comprises a third alignment structure matched with the first alignment structure and the second alignment structure;
placing the substrate in the accommodating cavity, and aligning the first alignment structure with the third alignment structure;
the mask layer is placed on the metal layer, and the second alignment structure is aligned with the third alignment structure, so that the graphic window corresponds to the position of the overlay mark region, and the graphic window is suspended relative to the overlay mark region.
Preferably, the vapor plating the marking material on the overlay mark region through the graphic window by using the mask layer as a mask includes:
Using the mask layer as a mask, and plating titanium on the overlay mark region through the graphic window to form an overlay mark base;
and taking the mask layer as a mask, and carrying out vapor plating on the base of the overlay mark through the pattern window to form the top of the overlay mark.
Compared with the prior art, the method has the advantages that the surface of the substrate is exposed through the metal layer on the patterned substrate to obtain the overlay mark region; then forming a mask layer on the metal layer, and forming a overhanging pattern window on the mask layer at a position corresponding to the overlay mark region; then the mask layer is used as a mask, and a pattern window is used for evaporating and plating a marking material on the overlay marking area; finally, the mask layer is removed, and the marking material on the overlay mark area forms an overlay mark. In the embodiment of the invention, the marking material is directly evaporated on the surface of the substrate and is gathered in the area right below the graphic window, and the marking material is not adhered to and contacted with the metal layer, so that the possibility of electrochemical reaction and the like between the overlay mark and the metal layer in the manufacturing process of the superconducting quantum chip is reduced, and the problems of black spots, corrosion marks and the like generated when the overlay mark is manufactured by directly evaporating noble metal such as Au and the like on the surface of the metal layer such as an aluminum film on a Wafer (Wafer) in the prior art are avoided. In addition, the invention integrates the process flow of gluing, exposing, developing, etching and photoresist removing and the process flow of gluing, exposing, developing, evaporating marking material and photoresist removing, thereby being beneficial to improving the chip preparation efficiency and shortening the chip preparation process period.
Drawings
FIG. 1 is a schematic view of a substrate according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart of a method for preparing overlay marks according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a structure corresponding to the steps in the flow chart of FIG. 2 according to an embodiment of the present invention;
in fig. 4, (1) is a schematic structural diagram of a mask layer 3 according to an embodiment of the present invention, and (2) is a partially enlarged schematic diagram of (1);
FIG. 5 is a cross-sectional view A-A' of FIG. 3 (c);
FIG. 6 is a schematic diagram of another embodiment of the present invention corresponding to the steps in the flow chart of FIG. 2;
in FIG. 7, (1) is a sectional view of B-B 'in FIG. 6 (B'), and (2) is a sectional view of C-C 'in FIG. 6 (C');
Fig. 8 is a schematic structural diagram of a receiving device according to an embodiment of the invention.
Reference numerals illustrate: 1-substrate, 11-chip area, 12-first alignment structure, 2-metal layer, 21-overlay mark area, 22-Josephson junction preparation area, 23-first control line, 24-second control line, 32-second alignment structure, 3-mask layer, 31-pattern window, 4-resist layer, 41-overlay mark area pattern, 42-Josephson junction preparation area pattern, 43-first control line pattern, 44-second control line pattern, 5-overlay mark, 6-undercut, 7-accommodation device, 71-accommodation cavity, 72-third alignment structure, 74-clamping part.
Detailed Description
The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
The overlay mark according to the embodiment of the invention is used as a reference for pattern alignment in the patterning process of the integrated circuit manufacturing process, namely, the overlay mark is used for accurately aligning the position of the lithography pattern generated on the substrate 1 (wafer) by the multiple lithography processes. Fig. 1 is a schematic structural diagram of a substrate in an embodiment of the present invention, where a substrate 1 in the embodiment of the present invention may be a silicon wafer, a sapphire wafer, or the like, a plurality of chip areas 11 are defined on the substrate 1 according to the requirements of preparation and design, and after the chip areas 11 on the substrate 1 are subjected to the processes of photolithography, oxidation, doping, deposition, metallization, and the like, the substrate 1 is cut into a plurality of chips according to the boundary lines of the dividing areas of the chip areas 11.
Fig. 2 is a schematic flow chart of a method for preparing an overlay mark according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram corresponding to each flow step in fig. 2 in the embodiment of the present invention, that is, the steps (a) to (e) in fig. 3 correspond to the steps S101 to S105 in fig. 2 one by one.
Fig. 4 (1) is a schematic structural diagram of a mask layer 3 according to an embodiment of the present invention, and (2) is a partially enlarged schematic diagram of (1).
FIG. 5 is a cross-sectional view A-A' of FIG. 3 (c).
Referring to fig. 2 and fig. 3 (a) to (e), an embodiment of the present invention provides a method for preparing an overlay mark, including steps S101 to S105, where:
S101, referring to fig. 3 (a), a substrate 1 is provided, on which a metal layer 2, such as an Al layer, a Ni layer, etc., is formed, and in practice, the material selected for the metal layer 2 is not limited thereto, and other metal materials may be selected according to the preparation process and purpose. In some embodiments of the quantum chip fabrication process, the substrate 1 is selected from a high-resistance silicon wafer, a sapphire wafer.
S102, with reference to FIG. 3 (b), patterning the metal layer 2 to obtain an overlay mark region 21 on the surface of the substrate 1, that is, etching to remove the metal layer 2 in a designated area by using a patterning process to form a groove, wherein the exposed surface of the substrate 1 after the metal layer 2 in the designated area is removed forms the overlay mark region 21.
S103, referring to fig. 3 (c), a mask layer 3 is formed on the metal layer 2, and a position on the mask layer 3 corresponding to the overlay mark region 21 is shown in fig. 3 (c), fig. 4, and fig. 5, that is, a overhanging pattern window 31 is formed at a position right above the overlay mark region 21, and the pattern window 31 is consistent with the shape of the overlay mark 5 to be prepared. In this step, the overhanging pattern window 31 is marked with reference to the dotted line in fig. 5, that is, the edge of the pattern window 31 above the overlay mark region 21 is overhanging, so that the notch area of the groove formed after etching to remove the metal layer 2 in the designated region is larger than the window area of the pattern window 31. The pattern window 31 is formed on the mask layer 3 at a position corresponding to the overlay mark region 21, so that the marking material can be accurately evaporated and collected at a position corresponding to the pattern window 31 on the overlay mark region 21, for example, directly under the pattern window 31, and meanwhile, in order to obtain the overlay mark 5 with a specific shape, the shape of the pattern window 31 needs to be consistent with the shape of the overlay mark 5.
S104, referring to FIG. 3 (d), the mask layer 3 is used as a mask, the marking material is vapor-deposited on the overlay mark region 21 through the pattern window 31, and because the edge of the formed pattern window 31 is suspended, the metal layer 2 is shielded and covered by the mask layer 3 during vapor deposition of the marking material, the vapor-deposited marking material is gathered on the overlay mark region 21 at the position corresponding to the pattern window 31, and referring to FIG. 5, the vapor-deposited marking material is gathered in the region right below the pattern window 31, and the vapor-deposited marking material and the metal layer 2 are not in adhesion contact.
S105, referring to fig. 3 (e), the mask layer 3 is removed, and the marking material on the overlay mark region 21 forms the overlay mark 5.
In the implementation of the invention, the surface of the substrate 1 is exposed through the metal layer 2 on the patterned substrate 1 to obtain an overlay mark region 21; then forming a mask layer 3 on the metal layer 2, and forming a overhanging pattern window 31 on the mask layer 3 at a position corresponding to the overlay mark region 21; then the mask layer 3 is used as a mask, and a pattern window 31 is used for evaporating and plating a marking material on the overlay mark region 21; finally, the mask layer 3 is removed and the marking material on the overlay mark region 21 forms the overlay mark 5. In the embodiment of the invention, the marking material is directly evaporated on the surface of the substrate 1, and the marking material is gathered in the area right below the pattern window 31 due to the shielding and masking functions of the suspended pattern window 31 and is not adhered to and contacted with the metal layer 2, so that the possibility of electrochemical reaction and the like between the overlay mark 5 and the metal layer 2 is reduced, and the problems of black spots and corrosion marks generated when the overlay mark is manufactured by directly evaporating the marking material such as noble metal Au on the surface of the metal layer such as an aluminum film on a Wafer (Wafer) in the prior art are avoided.
Fig. 6 is another schematic structural diagram corresponding to each flow step in fig. 2 in the embodiment of the present invention, and it should be noted that, with respect to (b), (c) and (d) in fig. 3, fig. 6 (b '), (c ') and (d ') are schematic structural diagrams corresponding to different embodiments.
In FIG. 7, (1) is a sectional view of B-B 'in FIG. 6 (B'), and (2) is a sectional view of C-C 'in FIG. 6 (C').
Referring to fig. 6 (b'), fig. 7 (1), in some embodiments of the present invention, for step S102, the patterning of the metal layer 2 to obtain the overlay mark region 21 on the surface of the substrate 1 includes steps S102-1 to S102-2:
S102-1, forming a patterned resist layer 4 on the metal layer 2, where the patterned resist layer 4 is formed with an overlay mark region pattern 41, it is understood that the overlay mark region pattern 41 is consistent with the shape of the overlay mark region 21 to be obtained, where, as an example, forming the patterned resist layer 4 on the metal layer 2 includes: coating photoresist on the metal layer, exposing and developing to form a patterned resist layer;
s102-2, etching the metal layer 2 by taking the patterned anti-corrosion layer 4 as a mask to obtain an etching pattern, wherein the etching pattern comprises an overlay mark area 21 positioned on the surface of the substrate 1, and the step can be used for etching and removing the metal layer 2 in a designated area by utilizing a wet etching process to form a groove to obtain the etching pattern.
More preferably, in order to improve the efficiency of the quantum chip preparation and shorten the quantum chip preparation process cycle, as shown in fig. 6 (b'), the patterned resist layer 4 in step S102-1 is further formed with a josephson junction preparation area pattern 42 and a control line pattern, and a coplanar waveguide transmission line pattern, where the control line pattern includes a first control line pattern 43 and a second control line pattern 44; the etching pattern in step S102-2 further includes a josephson junction preparation area 22, a control line and a coplanar waveguide transmission line on the surface of the substrate, where the control line includes a first control line 43 and a second control line 44, that is, the process of preparing alignment marks and the process of preparing quantum chip components are integrated, and the step forms an overlay mark area pattern 41, a josephson junction preparation area pattern 42 and a control line pattern in one patterning process, so that the chip preparation period is greatly shortened compared with the multiple patterning processes in which the overlay mark area pattern 41, the josephson junction preparation area pattern 42 and the control line pattern are formed respectively. Specifically, the process flow of gluing, exposing, developing, etching and photoresist removing required for preparing the josephson junction preparation area 22 and the control circuit pattern and the process flow of gluing, exposing, developing, evaporating the marking material and photoresist removing for preparing the overlay mark 5 can be integrated together, so that repeated process steps are saved, the chip preparation efficiency is improved, and the chip preparation process period is shortened.
As shown in fig. 7, more preferably, in order to further avoid adhesion and contact between the evaporated marking material and the metal layer 2, in step S102-1, an undercut 6 is formed between the patterned resist layer 4 and the overlay mark region 21, where the undercut 6 is a recess formed by recessing the edge of the metal layer 2 above the overlay mark region 21 toward one side with respect to the edge of the resist layer 4 due to the etching medium when the metal layer 2 in the designated region is etched and removed.
Referring to fig. 6 (c'), and fig. 7 (2), it is further preferable that, in order to further shorten the process cycle, after completing steps S102-1 to S102-2, a mask layer 3 is directly formed on the resist layer 4, that is, for step S103, the mask layer 3 is formed on the metal layer 2, and a suspended pattern window 31 is formed on the mask layer 3at a position corresponding to the overlay mark region 21, including:
A mask layer 3 is formed on the patterned resist layer 4, a pattern window 31 is formed on the mask layer 3 at a position corresponding to the overlay mark region 21, the pattern window 31 is in a hanging shape relative to the overlay mark region 21, and the edge of the formed pattern window 31 is suspended as shown by a dotted line circled part in fig. 7 (2).
If the mask layer 3 is directly formed on the resist layer 4, and then, referring to (d') in fig. 6, the mask layer 3 is used as a mask, the marking material is vapor deposited on the overlay mark region 21 through the pattern window 31, and for step S106, the removing the mask layer and the marking material on the overlay mark region forms the overlay mark 5, then the method includes:
removing the mask layer 3, and at this time, removing the mask layer together with the marking material remaining on the surface of the mask layer 3;
The patterned resist layer 4 is removed, the marking material on the overlay mark region 21 forms an overlay mark 5, as shown in fig. 6 (e), and since the edge of the formed pattern window 31 is suspended, the pattern window 31 can also play a role of shielding and masking when the marking material is evaporated, so that the marking material gathered on the overlay mark region 21 is not adhered to the resist layer 4, and the formed feature of the overlay mark 2 is not damaged when the resist layer 4 is removed.
Referring to fig. 4, 6 (c'), and 7 (2), in other embodiments of the present invention, in step S103, the forming a mask layer 3 on the metal layer 2, the mask layer 3 is formed with a overhanging pattern window 31 at a position corresponding to the overlay mark region 21, and the pattern window 31 is consistent with the shape of the overlay mark 4 to be prepared, including steps S103-1 to S103-3:
s103-1, providing a mask layer 3, wherein the mask layer 3 is consistent with the shape of the substrate 1 so as to align the mask layer 3 and the substrate 1 by utilizing shape characteristics;
S103-2, forming a graphic window 31 on the mask layer 3 at a position corresponding to the overlay mark region 21, wherein the window area of the graphic window 31 is smaller than the area of the overlay mark region 21, and the shape of the graphic window 31 is consistent with that of the overlay mark 5 to be prepared;
s103-3, placing the mask layer 3 on the metal layer 2 and enabling the pattern window 31 which is suspended to correspond to the overlay mark area 21, and referring to the dotted line circled part in the figure 7 (2).
Fig. 8 is a schematic structural diagram of a receiving device according to an embodiment of the invention.
Referring to fig. 3, 6 and 8, in order to facilitate alignment of the mask layer 3 and the substrate 1 so as to form the overlay mark 4 in a designated area, in an embodiment of the present invention, a first alignment structure 12 is formed on the substrate 1, a second alignment structure 32 that mates with the first alignment structure 12 is formed on the mask layer 3, and the positioning of the mask layer 3 on the metal layer 2 and the corresponding overhanging pattern window 31 on the overlay mark area 21 includes:
The mask layer 3 is placed on the metal layer 2 and the first alignment structure 12 and the second alignment structure are aligned 32 such that the graphic window 31 corresponds in position to the overlay mark region 21 and the graphic window 31 is overhanging with respect to the overlay mark region 21.
Wherein, as a specific example, in step S103-3, the placing the mask layer 3 on the metal layer 2 and aligning the second alignment structure 32 and the first alignment structure 12 so that the graphic window 31 corresponds to the position of the overlay mark region 21 and the graphic window 31 is suspended relative to the overlay mark region 21 includes:
S103-3-1, providing a containing device 7, wherein the containing device is provided with a containing cavity 71 and a rotatable clamping part 73, and a third aligning structure 73 matched with the first aligning structure 12 and the second aligning structure 32 is arranged in the containing cavity 71;
S103-3-2, placing the substrate 1 in the accommodating cavity 71, and aligning the first alignment structure 12 with the third alignment structure 73;
S103-3-3, placing the mask layer 3 on the metal layer 2, aligning the second alignment structure 32 with the third alignment structure 73 so that the graphic window 31 corresponds to the alignment mark region 21 in position, hanging the graphic window 31 relative to the alignment mark region 21, and then rotating the clamping part 73 to fix the mask plate 3 and the substrate 1 in the accommodating cavity 71.
In some embodiments of the present invention, in order to overcome the defect of poor adhesion between gold and the substrate 1, in step S104, the step of using the mask layer 3 as a mask to vapor deposit a marking material in the overlay mark region 21 through the pattern window 31 includes:
S104-1, using the mask layer 3 as a mask, evaporating titanium on the overlay mark region 21 through the graphic window 31 to form an overlay mark base;
s104-2, evaporating Jin Yu the overlay mark base through the graphic window 31 by taking the mask layer 3 as a mask to form an overlay mark top.
After the mask layer 3 is removed, the mark material on the overlay mark region 21 forms an overlay mark 5, that is, the overlay mark comprises an overlay mark base and an overlay mark top located on the overlay mark base, and the adhesion between titanium adopted by the overlay mark base and the substrate 1 is better than that of gold.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011058736.6A CN114334906B (en) | 2020-09-30 | 2020-09-30 | A method for preparing an overlay mark |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011058736.6A CN114334906B (en) | 2020-09-30 | 2020-09-30 | A method for preparing an overlay mark |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114334906A CN114334906A (en) | 2022-04-12 |
| CN114334906B true CN114334906B (en) | 2024-06-14 |
Family
ID=81011516
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011058736.6A Active CN114334906B (en) | 2020-09-30 | 2020-09-30 | A method for preparing an overlay mark |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114334906B (en) |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2555979B2 (en) * | 1994-05-30 | 1996-11-20 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| US6605519B2 (en) * | 2001-05-02 | 2003-08-12 | Unaxis Usa, Inc. | Method for thin film lift-off processes using lateral extended etching masks and device |
| US9768371B2 (en) * | 2012-03-08 | 2017-09-19 | D-Wave Systems Inc. | Systems and methods for fabrication of superconducting integrated circuits |
| CN103311144A (en) * | 2012-03-16 | 2013-09-18 | 中国科学院微电子研究所 | Method for manufacturing electron beam alignment mark based on tungsten metal |
| FR3038127B1 (en) * | 2015-06-24 | 2017-06-23 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING A PLURALITY OF ISLET-SHAPED DIPOLES HAVING SELF-ALIGNED ELECTRODES |
| WO2019032115A1 (en) * | 2017-08-11 | 2019-02-14 | Intel Corporation | Qubit devices with josephson junctions connected below supporting circuitry |
| CN111613661B (en) * | 2019-02-22 | 2024-03-26 | 中国科学院物理研究所 | Tunnel junction, preparation method and application thereof |
| CN110034228A (en) * | 2019-04-12 | 2019-07-19 | 中国科学院物理研究所 | Multi-layer film structure, preparation method and application |
| CN110783254B (en) * | 2019-11-08 | 2022-10-04 | 京东方科技集团股份有限公司 | Chip transfer method and semiconductor device |
-
2020
- 2020-09-30 CN CN202011058736.6A patent/CN114334906B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN114334906A (en) | 2022-04-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109795975A (en) | A kind of metal micro-/ nano linear array and preparation method thereof | |
| JPS61263172A (en) | Method for manufacturing thin film solar cells | |
| CN104465337A (en) | Method for manufacturing metal nanometer slit through PMMA/NEB double-layer glue | |
| CN105261555A (en) | Method for preparing metal electrode on diamond anvil cell | |
| CN109755127B (en) | An etch-and-deposition-stripping fusion method for chip fabrication | |
| CN114334906B (en) | A method for preparing an overlay mark | |
| CN101431025B (en) | Novel method for producing thin-film transistor channel region and source/drain electrode | |
| CN114460819B (en) | Alignment mark for electron beam exposure and preparation method thereof | |
| CN101320215A (en) | A photolithographic mark on a semiconductor material and its manufacturing method | |
| CN110277376A (en) | Air bridge integrated inductor and manufacturing method thereof | |
| CN102097303B (en) | Photolithographic process for thick metal | |
| CN113764262B (en) | Preparation method and equipment of large-size high-precision chip | |
| CN208898974U (en) | Manufacturing system of fine metal mask | |
| CN117276071A (en) | Chip product preparation method, system and chip | |
| CN112099311B (en) | Preparation method of photoetching mask based on AAO nanostructure | |
| CN106207745A (en) | A kind of method improving chip metal electroplating current on-state rate and wafer | |
| JP2003140366A (en) | Preparing method of alignment mark | |
| CN106919015B (en) | A kind of semiconductor devices making lithography alignment method | |
| US6696223B2 (en) | Method for performing photolithography | |
| CN215600395U (en) | Silicon-based OLED anode pixel photoetching internally-tangent structure | |
| CN113064333A (en) | Photoetching method of tiny wafer, wafer carrier and photoetching tool | |
| CN113161414B (en) | A kind of PN microwire preparation method | |
| CN113903657A (en) | Chip manufacturing method | |
| JP2508230B2 (en) | Electrode pattern forming method | |
| KR100234175B1 (en) | Manufacturing method of coil for thin film magnetic head |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 230088 6th floor, E2 building, phase II, innovation industrial park, 2800 innovation Avenue, high tech Zone, Hefei City, Anhui Province Applicant after: Benyuan Quantum Computing Technology (Hefei) Co.,Ltd. Address before: 230088 6th floor, E2 building, phase II, innovation industrial park, 2800 innovation Avenue, high tech Zone, Hefei City, Anhui Province Applicant before: ORIGIN QUANTUM COMPUTING COMPANY, LIMITED, HEFEI |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 230088 Anhui Province, Hefei City, Gaoxin District, Chengxiqiao Community Service Center, No. 900 Wangjiang West Road, Zhong'an Chuanggu Science and Technology Park Phase I, Building D8 Patentee after: Benyuan Quantum Computing Technology (Hefei) Co.,Ltd. Country or region after: China Address before: 230088 6th floor, E2 building, phase II, innovation industrial park, 2800 innovation Avenue, high tech Zone, Hefei City, Anhui Province Patentee before: Benyuan Quantum Computing Technology (Hefei) Co.,Ltd. Country or region before: China |