CN114328311B - Memory controller architecture, data processing circuit and data processing method - Google Patents
Memory controller architecture, data processing circuit and data processing method Download PDFInfo
- Publication number
- CN114328311B CN114328311B CN202111537979.2A CN202111537979A CN114328311B CN 114328311 B CN114328311 B CN 114328311B CN 202111537979 A CN202111537979 A CN 202111537979A CN 114328311 B CN114328311 B CN 114328311B
- Authority
- CN
- China
- Prior art keywords
- data
- memory
- bus interface
- data processing
- interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Advance Control (AREA)
Abstract
The invention discloses a memory controller architecture, a data processing circuit and a data processing method, wherein a block operation processor is embedded in a memory controller to intensively process processing requirements for block data. The memory controller can directly issue a command for reading data, so that the problem of larger command delay in the traditional circuit structure is solved, and the reading speed is accelerated to the greatest extent; the memory controller can process the data without CPU or DMA from the other end of the bus, thereby reducing the transmission time of the data on the bus, improving the efficiency of data processing, reducing the load of the CPU or DMA, and having more efficient circuit operation and smaller power consumption.
Description
Technical Field
The present invention relates to the field of electronic circuits, and in particular, to a memory controller architecture, a data processing circuit, and a data processing method.
Background
In SLAM (Simultaneous Localization AND MAPPING, instant localization and mapping) applications, it is often necessary to search and process large volumes (in a continuous piece of memory) of map data. The traditional circuit structure takes the role of issuing read-write commands by a CPU or a DMA, and takes out a large amount of data to be processed. Since the current SOC (System On Chip) mostly adopts NOC (Network On Chip) design, the bus structure is complex, resulting in a large command delay. Moreover, when the CPU or DMA reads and writes map data, system configuration related instructions are required, and the configuration of these instructions may interfere with the access efficiency of the memory controller. For the above reasons, the conventional circuit structure requires a lot of time to process the block map (i.e., the large-batch continuous map) data.
Disclosure of Invention
In order to solve the above problems, the present invention provides a memory controller architecture, a data processing circuit and a data processing method, which greatly reduce the transmission time of data on a bus and improve the efficiency of reading and processing data. The specific technical scheme of the invention is as follows:
A memory controller architecture, the architecture comprising a block operation processor, a bus interface, and a memory interface; the block operation processor is respectively connected with the bus interface and the memory interface, and sends command words to the memory interface according to configuration information of the bus interface, and then processes data returned by the memory interface.
Further, the block operation processor includes a decoder and a control state machine; the decoder is connected with the bus interface and the control state machine and is used for generating command words according to configuration information of the bus interface or data returned by the memory interface; and the control state machine is connected with the decoder, the bus interface and the memory interface and is used for reading and processing the data returned by the memory interface according to the command word.
A data processing circuit comprises a memory controller architecture, a central processing unit and a memory, wherein the central processing unit and the memory are respectively connected with the memory controller architecture.
Further, the central processing unit is connected with the bus interface, and is used for generating configuration information according to the data processing request and then sending the configuration information to the block operation processor through the bus interface.
Further, the central processing unit is connected with the block operation processor, and when the block operation processor finishes data processing, the block operation processor sends an interrupt signal to the central processing unit.
Further, the bus interface is connected with the memory interface, so that the central processing unit can realize communication with the memory interface through the bus interface in the switching gap of the command word.
A data processing method, the method being implemented by said data processing circuit, said method comprising: according to the data processing request, the central processing unit generates configuration information and sends the configuration information to the block operation processor, so that the block operation processor generates a command word and sends the command word to the memory interface to read data to be processed, then the data to be processed is processed according to the configuration information, and finally a processing result is returned to the central processing unit.
Further, the configuration information includes: the reading mode comprises a common mode and a linked list mode; the common mode represents that only one data is read, and the linked list mode represents that the data read next time is related to the last data read currently; wherein the last data currently read has a specific meaning; a start address representing a start position of data to be processed in the memory; the data length represents the size of the data to be processed; an operation mode representing a data operation method executed on data to be processed; and the timeout time limit represents the time limit of the block operation processor for processing the data, and the current operation is forcedly ended after the timeout.
Further, the block operation processor generates a next command word according to the specific meaning of the last data in the data to be processed; wherein the command word includes any one of a read mode, a start address, a data length, an operation mode, and a timeout period.
Further, after the block operation processor finishes processing the data to be processed, the processing result is stored in a register of the bus interface, and then interrupt information is sent to the central processing unit.
Further, the method further comprises: and in the switching gap of the command word, the central processing unit realizes communication with the memory interface through the bus interface so as to meet the operation requirement of the data processing circuit.
The invention has the beneficial effects that: in contrast to the prior art, the method of the present invention centrally handles the processing requirements for block data by embedding a block operation processor in the memory controller. The memory controller can directly issue a command for reading data, so that the problem of larger command delay in the traditional circuit structure is solved, and the reading speed is accelerated to the greatest extent; the memory controller can process the data without CPU or DMA from the other end of the bus, thereby reducing the transmission time of the data on the bus, improving the efficiency of data processing, reducing the load of the CPU or DMA, and having more efficient circuit operation and smaller power consumption.
Drawings
FIG. 1 is a schematic diagram of a data processing circuit according to an embodiment of the invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It should also be understood that the term "and/or" as used in this disclosure refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in this disclosure, the term "if" may be interpreted in context as "when …" or "upon" or "in response to a determination" or "in response to detection. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
Furthermore, references to "one embodiment" or "some embodiments" or the like described in this specification mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
In SLAM applications, a large volume of map data is often required to be searched. Searching for map data takes a lot of CPU running time because these map data are updated in real time and the amount of data is large and cannot be accelerated by Cache (Cache memory). Map search functions become a bottleneck in SLAM applications.
Accordingly, embodiments of the present invention provide a memory controller architecture including a block operation processor, a bus interface, and a memory interface; the block operation processor is respectively connected with the bus interface and the memory interface, and sends command words to the memory interface according to configuration information of the bus interface, and then processes data returned by the memory interface. The memory controller architecture embeds a block operation processor within a conventional memory controller, thereby centralizing the processing requirements of the processing system for block data. In particular, the block operation processor includes a decoder and a control state machine. The decoder is connected with the bus interface and the control state machine and is used for generating command words according to configuration information of the bus interface or data returned by the memory interface; the control state machine is connected with the decoder, the bus interface and the memory interface and is used for reading and processing data returned by the memory interface according to the command word. In the architecture of the memory controller, the memory controller itself is not a CPU or DMA, which is responsible for issuing the data read-write command, thus greatly reducing the transmission delay of the read-write command, improving the response efficiency of the memory controller and accelerating the data reading speed to the greatest extent. Meanwhile, the memory controller can also implement data processing operation without a CPU or a DMA (direct memory access) from the other end of the bus to process data, so that the transmission time of the data on the bus is reduced, the data processing efficiency is improved, meanwhile, the load of the CPU or the DMA is reduced, the circuit operation is more efficient, and the power consumption is smaller.
Referring to fig. 1, the present invention further provides a data processing circuit, where the circuit includes the memory controller architecture, and further includes a central processor and a memory respectively connected to the memory controller architecture. The central processing unit is connected with the bus interface and is used for generating configuration information according to the data processing request and then sending the configuration information to the block operation processor through the bus interface. The data processing request includes a map data search request of the system, and the central processor automatically generates configuration information of the block operation processor according to the request. And then, after the block operation processor receives the configuration information, the block operation processor can replace the central processing unit to read and process the data, so that the transmission time of the data on a bus is greatly reduced, and the efficiency of reading and processing the data is improved. The central processing unit is also connected with a control state machine of the block operation processor, and after the control state machine finishes data processing, the processing result is stored in a register of the bus interface and then an interrupt signal is sent to the central processing unit, so that the central processing unit can acquire the processing result from the bus interface at any time.
As one embodiment, the bus interface is connected to the memory interface, so that the central processor can communicate with the memory interface via the bus interface in the switching gap of the command word. While the memory interface is continuously read, the interface is continuously occupied, but the system still needs to operate. At this time, through the normal read/write channel between the bus interface and the memory interface, the CPU can directly read the required data from the memory in the switching gap of the command word, thus avoiding the system stop while ensuring the reading efficiency of the block data. It should be noted that the memory interfaces include, but are not limited to SPI, flash, DRAM and AMBA. There are two types of data read modes: single (single access mode) and burst (continuous access mode). During reading, the gap between reads may result in a decrease in data channel efficiency, so the smaller the gap, the better. Therefore, the mode adopted in this embodiment is burst, so as to improve the data reading efficiency, and meanwhile, the longer the data length supported by the mode is, the higher the transmission efficiency is.
The invention also provides a data processing method, which is realized by the data processing circuit, and comprises the following steps: according to the data processing request, the central processing unit generates configuration information and sends the configuration information to the block operation processor, so that the block operation processor generates a command word and sends the command word to the memory interface to read data to be processed, then the data to be processed is processed according to the configuration information, and finally a processing result is returned to the central processing unit.
As one embodiment, after receiving a map data search request from the system, the central processor generates relevant configuration information and sends the configuration information to the block operation processor. The configuration information includes: the reading mode comprises a common mode and a linked list mode; the common mode represents that only one data is read, and the linked list mode represents that the data read next time is related to the last data read currently; wherein the last data currently read has a specific meaning. For example, in the last word (word) of the data that is read consecutively, 0xA is read, which 0xA will be given a specific meaning that indicates how the data is to be read next (e.g., read from the next word of 0 xA); if 0xB is last read and 0xB is defined as the end of the read, the entire read operation is terminated. The start address indicates the start position of the data to be processed in the memory, i.e. the first data to be read. The data length represents the size of the data to be processed. An operational mode representing a data operation method performed on the data to be processed, including but not limited to, alignment, summation, maximization, and averaging. The timeout period, which represents the time limit for the block operation processor to process data, forces the end of the current operation, such as 2 seconds or 1 minute, after the timeout, preventing the operation from seizing.
The command word includes any one of a read mode, a start address, a data length, an operation mode, and a timeout period. When the reading mode is set to a linked list mode, the block operation processor generates a command word of the next time according to the specific meaning of the last data in the data to be processed. Specifically, the control state machine sends the command address contained in the last data in the data to be processed to the decoder, and the decoder generates the next command word. Based on the command word, the memory interface returns corresponding data from the memory to the block operation processor for processing.
Further, after the block operation processor finishes the processing of the data to be processed, the processing result is stored in a register of the bus interface, and then interrupt information is sent to the central processing unit immediately or after all the data processing is finished, so as to inform the central processing unit to read the processing result before. Or release the bus interface to change the bus from busy to idle. It can be seen that the central processor, except for sending configuration information to the block operation processor, is not involved in the process of data reading and processing, and all operations are completed by the memory controller. The memory controller directly issues the command for reading the data, so that the problem of larger command delay in the traditional circuit structure is solved, and the reading speed is accelerated to the greatest extent; meanwhile, the data is processed without the central processing unit from the other end of the bus, so that the transmission time of the data on the bus is reduced, the data processing efficiency is improved, meanwhile, the load of the central processing unit is reduced, the circuit operation is more efficient, and the power consumption is smaller.
It should be noted that while the memory interface is continuously being read, the interface is continuously occupied, but the system still needs to operate. As a preferred solution, the cpu reads the required data directly from the memory through the normal read/write channel between the bus interface and the memory interface in the switching gap of the command word, thus avoiding system stop while ensuring the reading efficiency of the block data. In another embodiment, the normal read/write channel between the bus interface and the memory interface is set to a higher priority, and the command word is run when the memory interface is idle, which has little impact on the performance of the system, but increases the run time of the command word. In yet another embodiment, the system runs the servo program in other memory, so that the operation of the block data is not affected.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Furthermore, functional units in various embodiments of the present application may be integrated together to form a single part, or each unit may exist alone, or two or more units may be integrated to form a single part.
Those skilled in the art will appreciate that implementing all or part of the above described embodiment methods may be accomplished by way of a computer program stored in a non-transitory computer readable storage medium, which when executed, may comprise the steps of embodiments of the above described methods. References to memory, storage, databases, or other media used in various embodiments provided herein may include non-volatile and/or volatile memory. The non-volatile memory may include read-only memory ROM, programmable memory PROM, electrically programmable memory DPROM, electrically erasable programmable memory DDPROM, or flash memory. Volatile memory can include random access memory RAM or external cache memory.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing embodiments are merely representative of several embodiments of the application, which are described in more detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application.
Claims (9)
1. A memory controller architecture, the architecture comprising a block operation processor, a bus interface, and a memory interface; the block operation processor is respectively connected with the bus interface and the memory interface, and sends command words to the memory interface according to configuration information of the bus interface and then processes data returned by the memory interface;
Wherein the bus interface is connected with the memory interface such that the bus interface can communicate directly with the memory interface in the switching gap of the command word.
2. The memory controller architecture of claim 1, wherein the block operation processor comprises a decoder and a control state machine; wherein,
The decoder is connected with the bus interface and the control state machine and is used for generating command words according to configuration information of the bus interface or data returned by the memory interface;
and the control state machine is connected with the decoder, the bus interface and the memory interface and is used for reading and processing the data returned by the memory interface according to the command word.
3. A data processing circuit comprising a memory controller architecture according to any one of claims 1 to 2, and further comprising a central processor and a memory each coupled to the memory controller architecture; the bus interface is connected with the memory interface, so that the central processing unit can realize communication with the memory interface through the bus interface in the switching gap of the command words.
4. A data processing circuit according to claim 3, wherein the central processor is coupled to the bus interface for generating configuration information in response to a data processing request and for transmitting the configuration information to the block operation processor via the bus interface.
5. A data processing circuit according to claim 3, wherein the central processing unit is connected to the block operation processor, and the block operation processor sends an interrupt signal to the central processing unit when the block operation processor completes the data processing.
6. A data processing method, characterized in that the method is implemented by a data processing circuit according to any of claims 3 to 5, said method comprising:
According to the data processing request, the central processing unit generates configuration information and sends the configuration information to the block operation processor, so that the block operation processor generates a command word and sends the command word to the memory interface to read data to be processed, then the data to be processed is processed according to the configuration information, and finally a processing result is returned to the central processing unit; and in the switching gap of the command word, the central processing unit realizes communication with the memory interface through the bus interface so as to meet the operation requirement of the data processing circuit.
7. The data processing method according to claim 6, wherein the configuration information includes:
the reading mode comprises a common mode and a linked list mode; the common mode represents that only one data is read, and the linked list mode represents that the data read next time is related to the last data read currently; wherein the last data currently read has a specific meaning;
A start address representing a start position of data to be processed in the memory;
the data length represents the size of the data to be processed;
An operation mode representing a data operation method executed on data to be processed;
And the timeout time limit represents the time limit of the block operation processor for processing the data, and the current operation is forcedly ended after the timeout.
8. A data processing method according to claim 7, wherein said block operation processor generates a command word for the next time based on a specific meaning of the last data among the data to be processed; wherein the command word includes any one of a read mode, a start address, a data length, an operation mode, and a timeout period.
9. The data processing method according to claim 6, wherein the block operation processor stores the processing result in a register of the bus interface after completing the processing of the data to be processed, and then transmits the interrupt information to the central processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111537979.2A CN114328311B (en) | 2021-12-15 | 2021-12-15 | Memory controller architecture, data processing circuit and data processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111537979.2A CN114328311B (en) | 2021-12-15 | 2021-12-15 | Memory controller architecture, data processing circuit and data processing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114328311A CN114328311A (en) | 2022-04-12 |
| CN114328311B true CN114328311B (en) | 2024-09-06 |
Family
ID=81051807
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111537979.2A Active CN114328311B (en) | 2021-12-15 | 2021-12-15 | Memory controller architecture, data processing circuit and data processing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114328311B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1695131A (en) * | 2002-08-27 | 2005-11-09 | 英特尔公司 | Address decode |
Family Cites Families (40)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0327782A1 (en) * | 1988-02-08 | 1989-08-16 | United Technologies Corporation | Bus controller command block processing system |
| US5471638A (en) * | 1991-10-04 | 1995-11-28 | Bull Hn Inforamtion Systems Inc. | Bus interface state machines with independent access to memory, processor and registers for concurrent processing of different types of requests |
| CA2080210C (en) * | 1992-01-02 | 1998-10-27 | Nader Amini | Bidirectional data storage facility for bus interface unit |
| US5848258A (en) * | 1994-06-30 | 1998-12-08 | Digital Equipment Corporation | Memory bank addressing scheme |
| JP3623379B2 (en) * | 1998-12-01 | 2005-02-23 | 富士通株式会社 | Microprocessor |
| US6425047B1 (en) * | 1999-06-24 | 2002-07-23 | Matsushita Electric Industrial Co., Ltd. | Process containing address decoders suited to improvements in clock speed |
| JP4114915B2 (en) * | 2002-05-24 | 2008-07-09 | 株式会社ルネサステクノロジ | Data processing apparatus and data processing system |
| JP2004029898A (en) * | 2002-06-21 | 2004-01-29 | Renesas Technology Corp | Data processor |
| FI115006B (en) * | 2003-06-13 | 2005-02-15 | Nokia Corp | Method and device for connection improved interface layer in between of computer screen and processor |
| CN100342360C (en) * | 2004-12-31 | 2007-10-10 | 北京中星微电子有限公司 | Access apparatus and method for direct memory |
| CN100507886C (en) * | 2005-12-22 | 2009-07-01 | 北京中星微电子有限公司 | Method and device for direct storage access to non-volatile memory |
| CN101071624A (en) * | 2006-05-11 | 2007-11-14 | 上海集通数码科技有限责任公司 | Storage unit chip with extensible input/output interface |
| US20080034146A1 (en) * | 2006-08-04 | 2008-02-07 | Via Technologies, Inc. | Systems and Methods for Transactions Between Processor and Memory |
| JP2009199344A (en) * | 2008-02-21 | 2009-09-03 | Toshiba Corp | Data processing unit |
| CN101819560B (en) * | 2009-02-27 | 2012-05-30 | 杭州晟元芯片技术有限公司 | Method and device for executing program of SPI interface memory |
| KR20110029220A (en) * | 2009-09-15 | 2011-03-23 | 주식회사 제니스트 | High-speed memory controller |
| US8266369B2 (en) * | 2009-12-18 | 2012-09-11 | Nxp B.V. | Flash memory interface |
| CN102135946A (en) * | 2010-01-27 | 2011-07-27 | 中兴通讯股份有限公司 | Data processing method and device |
| CN202404579U (en) * | 2011-12-16 | 2012-08-29 | 陕西千山航空电子有限责任公司 | Pseudo parallel bus interface circuit |
| CN103116551B (en) * | 2013-01-31 | 2016-05-04 | 苏州国芯科技有限公司 | Be applied to the NorFLASH store interface module of CLB bus |
| CN104252416B (en) * | 2013-06-28 | 2017-09-05 | 华为技术有限公司 | A kind of accelerator and data processing method |
| CN103995785B (en) * | 2014-05-07 | 2017-01-11 | 马鞍山百助网络科技有限公司 | Information processing method and system |
| CN105528311A (en) * | 2015-12-11 | 2016-04-27 | 中国航空工业集团公司西安航空计算技术研究所 | Memory reading-writing circuit and method based on data packet |
| CN105630735A (en) * | 2015-12-25 | 2016-06-01 | 南京大学 | Coprocessor based on reconfigurable computational array |
| CN105843206A (en) * | 2016-01-07 | 2016-08-10 | 乐卡汽车智能科技（北京）有限公司 | Vehicle bus security monitoring method, device and system |
| CN105930598B (en) * | 2016-04-27 | 2019-05-03 | 南京大学 | A hierarchical information processing method and circuit based on controller pipeline architecture |
| CN106484657A (en) * | 2016-11-18 | 2017-03-08 | 成都嘉纳海威科技有限责任公司 | A kind of reconfigurable signal processor ASIC framework and its reconstructing method |
| CN109240979A (en) * | 2018-08-13 | 2019-01-18 | 深圳市奥拓电子股份有限公司 | Data processing chip and LED display system |
| CN208706215U (en) * | 2018-08-13 | 2019-04-05 | 深圳市奥拓电子股份有限公司 | LED control system and LED display device |
| CN211403419U (en) * | 2018-08-14 | 2020-09-01 | 珠海市一微半导体有限公司 | Acceleration control system based on binarization algorithm, chip and robot |
| CN109522252B (en) * | 2018-11-15 | 2021-12-07 | 天津津航计算技术研究所 | Memory access method for high-speed bus communication controller |
| CN109710548A (en) * | 2018-12-21 | 2019-05-03 | 荆门博谦信息科技有限公司 | A kind of DMA control data transmission method, system and equipment |
| CN109743105A (en) * | 2019-01-08 | 2019-05-10 | 郑州云海信息技术有限公司 | Intelligent network card optical module management method, device, system, and intelligent network card and medium |
| CN110109853B (en) * | 2019-04-04 | 2021-04-16 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Data acquisition and processing device and method |
| CN110765046A (en) * | 2019-11-07 | 2020-02-07 | 首都师范大学 | A DMA transmission device and method for dynamically reconfigurable high-speed serial bus |
| CN110874337B (en) * | 2019-12-26 | 2024-11-22 | 山东方寸微电子科技有限公司 | OSPI control device and method |
| CN111382092A (en) * | 2020-03-05 | 2020-07-07 | 上海龙旗科技股份有限公司 | Sensor network, method and storage medium |
| JP2021182300A (en) * | 2020-05-20 | 2021-11-25 | キオクシア株式会社 | Memory controller, memory system, and control method of memory system |
| CN113014269A (en) * | 2021-02-08 | 2021-06-22 | 中山大学 | NAND Flash controller with error correction capability and control method |
| CN113220498B (en) * | 2021-05-08 | 2024-08-23 | 青芯半导体科技(上海)有限公司 | Embedded Flash controller supporting encryption storage |
-
2021
- 2021-12-15 CN CN202111537979.2A patent/CN114328311B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1695131A (en) * | 2002-08-27 | 2005-11-09 | 英特尔公司 | Address decode |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114328311A (en) | 2022-04-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| USRE48736E1 (en) | Memory system having high data transfer efficiency and host controller | |
| CN100555257C (en) | The memory controller of the dma operation between the processing page replicative phase and method | |
| US6425044B1 (en) | Apparatus for providing fast memory decode using a bank conflict table | |
| CN111221759B (en) | Data processing system and method based on DMA | |
| CN110910921A (en) | Command read-write method and device and computer storage medium | |
| CN211376201U (en) | Command read-write device and memory | |
| CN118363914B (en) | Data processing method, solid state disk device and host | |
| CN111512266A (en) | System, apparatus, and method for handshake protocol for low power state transitions | |
| US7725621B2 (en) | Semiconductor device and data transfer method | |
| CN111651384A (en) | Register reading and writing method, chip, subsystem, register bank and terminal | |
| CN116301627A (en) | NVMe controller and initialization and data read-write method thereof | |
| CN110990310B (en) | Device side SD controller, control method and electronic device | |
| CN119311627B (en) | Descriptor-based PCIe bus DMA high-speed data transmission method and device | |
| US20250077100A1 (en) | Control method, storage apparatus, and electronic device | |
| CN114328311B (en) | Memory controller architecture, data processing circuit and data processing method | |
| CN113849455B (en) | MCU based on hybrid memory and data caching method | |
| JP3756215B2 (en) | Interface controller and method | |
| US6425043B1 (en) | Method for providing fast memory decode using a bank conflict table | |
| CN119201822B (en) | A PCIe switch chip with storage and network acceleration functions | |
| US6904481B1 (en) | Bus sequence operation with automatic linking from current I/O information to subsequent I/O information | |
| CN118363901B (en) | PCIe device, electronic component and electronic device | |
| US6269430B1 (en) | Method for controlling a process of writing data sent by a central processing unit to a memory by using a central processing unit interface | |
| CN114385529B (en) | Direct memory access controller, electronic device using the same, and method of operating the same | |
| US20220237132A1 (en) | Data transmission method and ping-pong dma architecture | |
| CN120295757A (en) | Image data transmission method, system and medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |