CN114326911B - Reference voltage circuit and three-dimensional memory - Google Patents
Reference voltage circuit and three-dimensional memory Download PDFInfo
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- CN114326911B CN114326911B CN202210014088.7A CN202210014088A CN114326911B CN 114326911 B CN114326911 B CN 114326911B CN 202210014088 A CN202210014088 A CN 202210014088A CN 114326911 B CN114326911 B CN 114326911B
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Abstract
The present application provides a reference voltage circuit, comprising: a drive current module configured to generate a drive current; a reference generation module configured to generate a first voltage, a second voltage, and a reference voltage based on the driving current; an enable generation module comprising a first sub-circuit and a second sub-circuit connected in series; the error amplifier is characterized in that two input ends of the error amplifier respectively receive a first voltage and a second voltage, and an output end of the error amplifier generates a control voltage; the first sub-circuit is configured to generate a mirror current based on the drive current; the second sub-circuit is configured to turn on the second sub-circuit with the first sub-circuit based on the control voltage, and generate an enable signal for triggering the reference voltage according to a voltage between the turned-on first sub-circuit and the second sub-circuit. The reference voltage circuit can improve the accuracy of matching the enabling signal with the reference voltage and reduce the influence of device manufacturing process deviation on the accuracy of the enabling signal.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a reference voltage circuit and a three-dimensional memory.
Background
The reference voltage circuit is an important module in the integrated circuit, provides accurate reference voltage for the system, and the precision and stability of the reference voltage influence the performance of the whole circuit. For example, a bandgap reference (band gap) voltage circuit uses the sum of a positive temperature coefficient voltage proportional to temperature and a negative temperature coefficient voltage inversely proportional to temperature according to the characteristic that the bandgap voltage of a silicon material is irrelevant to temperature, and the temperature coefficients of the positive temperature coefficient voltage and the negative temperature coefficient voltage cancel each other to realize the voltage reference output irrelevant to temperature.
In some implementations, the reference voltage circuit may be triggered by a Power On Reset (POR) circuit, and provides a reference voltage and an enable signal that applies the reference voltage to a subsequent functional circuit. Further, the reference voltage circuit generally includes a reference generation module for generating a reference voltage and a start-up circuit module for driving the reference generation module. In addition, the starting circuit module also has the function of generating an enabling signal after the reference voltage reaches the ideal working voltage value.
However, due to the deviation of device process production, there is a problem that the enable signal generated by the reference voltage circuit is mismatched with the reference voltage of the ideal operating voltage value, so that the subsequent functional circuit applying the reference voltage is failed, thereby affecting the working process of the power-on reset operation, for example, and even affecting the working process of the whole chip.
Disclosure of Invention
The application provides a reference voltage circuit. The reference voltage circuit includes: a drive current module configured to generate a drive current; a reference generation module configured to generate a first voltage, a second voltage, and a reference voltage based on the driving current; an enable generation module comprising a first sub-circuit and a second sub-circuit connected in series; the error amplifier is characterized in that two input ends of the error amplifier respectively receive a first voltage and a second voltage, and an output end of the error amplifier generates a control voltage; the first sub-circuit is configured to generate a mirror current based on the drive current; and the second sub-circuit is configured to turn on the second sub-circuit and the first sub-circuit based on the control voltage, and generate an enable signal for triggering the reference voltage according to the voltage between the turned-on first sub-circuit and the second sub-circuit.
In some embodiments, the voltage pull-up capability of the first sub-circuit is lower than the voltage pull-down capability of the second sub-circuit with the first sub-circuit and the second sub-circuit turned on.
In some embodiments, the first sub-circuit comprises a first transistor and a first resistor connected in parallel, the second sub-circuit comprises a second transistor, wherein a first end of the first transistor is connected to a power supply end, a second end of the first transistor is connected to a first node, a control end of the first transistor is connected to the driving current module, and the control end of the first transistor is used for controlling generation of a mirror current flowing through the first transistor; the first end of the second transistor is connected to the first node, the second end of the second transistor is grounded, and the control end of the second transistor is used for enabling the second transistor to be turned on or off based on the control voltage, wherein the enabling signal is generated based on the voltage of the first node.
In some embodiments, the first transistor is a P-type transistor and the second transistor is an N-type transistor.
In some embodiments, the drive current module includes: the first end of the third transistor is connected to the second node, the second end of the third transistor is grounded, and the control end of the third transistor is connected with the output end of the error amplifier; a first end of a fourth transistor is connected to the bias branch, a second end of the fourth transistor is connected to one input end of the error amplifier and is grounded through the reference generating module, and a control end of the fourth transistor is connected to the first node; the bias branch is used for generating a driving current, and the first mirror branch is connected to the second node; the first end of the main control switch tube is connected to the bias branch, the second end of the main control switch tube is connected to the reference generation module, and the control end of the main control switch tube is connected to the second node.
In some embodiments, the first transistor is configured to generate a mirrored current through the first transistor based on the drive current generated by the bias arm.
In some embodiments, the bias branch includes a fifth transistor, the first mirror branch includes a sixth transistor, wherein first ends of the fifth transistor and the sixth transistor are connected to the power supply terminal, control ends of the fifth transistor, the sixth transistor, and the first transistor are connected to each other, a second end of the fifth transistor, the control end of the fifth transistor, and the first end of the main control switch are connected to each other, and a second end of the sixth transistor is connected to the second node.
In some embodiments, the fifth transistor and the sixth transistor are P-type transistors.
In some embodiments, the third transistor and the fourth transistor are each N-type transistors.
In some embodiments, the channel width to length ratio of the second transistor is greater than the channel width to length ratio of the third transistor.
In some embodiments, the fourth transistor has a channel width to length ratio of less than 0.1 based on the response time of the error amplifier.
In some embodiments, the master switch tube is an N-type transistor.
In some embodiments, the reference generation module includes: the first end of the first switching element group is grounded, the second end of the first switching element group is connected to a fourth node through the second resistor, and the control end of the first switching element group and the second end of the first switching element group are connected to the third node; the first end of the second switching element group is grounded through a third resistor, the second end of the second switching element group is connected to a fourth node through a fourth resistor, the control end of the second switching element group is connected to a third node, the voltage of the third node is a second voltage, the voltage of the second end of the second switching element group is a first voltage, the voltage of the fourth node is a reference voltage, and the fourth node is connected with the second end of the main control switching tube.
In some embodiments, the first switching element group includes M first switching tubes connected in parallel, and the second switching element group includes N second switching tubes connected in parallel, wherein M and N are both positive integers, and 1.ltoreq.M < N.
In some embodiments, the first and second switching transistors are NPN transistors, the first ends of the first and second switching transistors are collectors, and the second ends of the first and second switching transistors are emitters.
In some embodiments, the reference voltage circuit further comprises an inverter, an input of the inverter being connected to the first node, an output of the inverter generating the enable signal in dependence on a voltage of the first node.
The application further provides a three-dimensional memory. The three-dimensional memory includes peripheral circuitry including the reference voltage circuit as described in any of the embodiments above.
The reference voltage circuit provided by the embodiment of the application can improve the accuracy of matching the enable signal with the reference voltage and reduce the influence of device manufacturing process deviation on the accuracy of the enable signal by ensuring that the enable signal is generated by the positive temperature coefficient voltage and the negative temperature coefficient voltage after the reference voltage reaches an ideal working voltage value. Meanwhile, the reference voltage circuit is simple in structure, so that the required chip manufacturing area can be saved, and meanwhile, the manufacturing cost can be saved.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:
fig. 1 is a circuit diagram of a reference voltage circuit of an exemplary embodiment of the related art;
FIG. 2 is a circuit diagram of a reference voltage circuit of another exemplary embodiment of the related art;
FIG. 3 is a block diagram of a reference voltage circuit according to an embodiment of the application;
FIG. 4 is a schematic circuit diagram of a reference voltage circuit according to an embodiment of the application; and
fig. 5 is a circuit schematic of a reference voltage circuit according to another embodiment of the application.
Detailed Description
For a better understanding of the application, various aspects of the application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the application and is not intended to limit the scope of the application in any way.
The terminology used herein is for the purpose of describing particular example embodiments and is not intended to be limiting. The terms "comprises," "comprising," "includes," "including," and/or "having," when used in this specification, specify the presence of stated features, integers, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, elements, components, and/or groups thereof.
The description herein refers to schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the particular shapes and dimensions shown, but are to include various equivalent structures capable of performing the same function and shape and dimensional deviations, for example, from manufacturing. The locations shown in the drawings are schematic in nature and are not intended to limit the locations of the components.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 is a circuit diagram of an exemplary reference voltage circuit 10 of the related art. As shown in fig. 1, the reference voltage circuit 10 may include: reference generating module 11, first NMOS transistor M 1 Second NMOS transistor M 2 Third PMOS transistor M 3 Resistor R 1 . Wherein, the first NMOS transistor M 1 Second NMOS transistor M 2 Third PMOS transistor M 3 Resistor R 1 Can be formed into a start-up circuit module which can supply a drive current to the reference generating module 11 and cause the reference generating module 11 to generate a reference voltage Vbg reaching a desired operating voltage value 1 . At the same time, the start-up circuit module can generate the reference voltage Vbg at the reference generation module 11 1 After reaching the ideal operating voltage value, generating a reference voltage Vbg 1 Enable signal BGOK applied to subsequent functional circuit 1 。
Specifically, at the reference voltage circuit 10 and the power supply terminal Vdd 1 After connection, at resistor R 1 Under the action of (a) to enable the first node A 1 At a high level, due to the reference voltage Vbg generated by the reference generation module 11 1 The second node B does not reach the ideal operating voltage value 1 At a low level, a second NMOS transistor M 2 Turned on to supply the driving current to the reference generating module 11 to generate the reference voltage Vbg of the reference generating module 11 1 Gradually tending to and reaching the desired operating voltage value.
Further, the reference voltage Vbg generated by the reference generation module 11 1 After reaching the ideal operating voltage value, the second node B 1 Is high enough toLevel, make with second node B 1 Connected first NMOS transistor M 1 Conducting. By precisely controlling the resistance R 1 And a first NMOS transistor M 1 According to the device dimension parameter of R 1 And a first NMOS transistor M 1 First node A between 1 Voltage generation enable signal BGOK of (a) 1 。
In the prior art reference voltage circuit 10, the resistor R can be precisely controlled 1 And a first NMOS transistor M 1 To make the reference voltage Vbg generated by the reference generation module 11 1 After the voltage value of (2) reaches the ideal working voltage value, the enable signal BGOK is generated 1 . However, it is limited by the formation of the resistor R 1 And a first NMOS transistor M 1 May cause the reference voltage Vbg to be 1 The voltage value of the control signal does not reach the ideal operating voltage value, and generates an enable signal BGOK 1 This can severely affect the reference voltage Vbg 1 In the use case of the subsequent functional circuit.
Fig. 2 is a circuit diagram of another exemplary reference voltage circuit 20 of the related art. As shown in fig. 2, the reference voltage circuit 20 includes: a first reference generating module 21, a second reference generating module 22, a first current mirror 23, a second current mirror 24, and an NPN transistor B1.
When the reference voltage circuit 20 is in a steady state stage, i.e. after the reference voltage (not shown) generated by the first reference generating module 21 and/or the second reference generating module 22 reaches the desired operating voltage value, the reference voltage circuit is driven by the first resistor R in the first reference generating module 21 21 Is smaller than the second resistance R in the second reference generating module 22 22 Setting that the current value of the current Im flowing through the PMOS transistor M '1 is larger than the current value of the current Ib flowing through the NPN transistor B1, thereby changing the voltage at the node between the PMOS transistor M'1 and the NPN transistor B1, thereby ensuring that the enable signal BGOK is generated after the voltage value of the reference voltage generated by the first reference generating module 21 and/or the second reference generating module 22 reaches the ideal operating voltage value 2 . The first reference generation module 21 and the second reference generation shown in fig. 2The module 22 is exemplary, and the first reference generation module 21 and the second reference generation module 22 may further include, for example, an op amp for generating a reference voltage.
Although the reference voltage circuit 20 shown in fig. 2 is capable of enabling the signal BGOK 2 The reference voltage is generated after reaching the ideal operating voltage value. However, since the plurality of reference generating modules 21 to 22 are used to control the enable signal BGOK 2 Such a circuit configuration is disadvantageous in terms of manufacturing cost and operating efficiency.
Based on the technical problems of the prior reference voltage circuit in generating the reference voltage and the enabling signal, the application provides the reference voltage circuit which can improve the accuracy of the reference voltage and the ideal working voltage value thereof in the process of generating the enabling signal. In addition, the reference voltage circuit has low structural complexity, and can save the manufacturing area, thereby saving the manufacturing cost.
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
Fig. 3 is a block diagram of a reference voltage circuit 100 according to an embodiment of the application. As shown in fig. 3, the reference voltage circuit 100 includes: a driving current module 110, a reference generation module 120, an error amplifier 111, and an enable generation module 130.
The drive current module 110 is configured to generate a drive current Id, which is used, for example, as a current source of the reference generation module 120.
The reference generation module 120 is configured to generate a first voltage (e.g., a positive temperature coefficient voltage), a second voltage (e.g., a negative temperature coefficient voltage), and a reference voltage Vbg based on the driving current Id. For example, the reference voltage Vbg may be a zero temperature coefficient voltage formed by superimposing a positive temperature coefficient voltage and a negative temperature coefficient voltage.
The enable generation module 130 includes a first sub-circuit 131 and a second sub-circuit 132 connected in series.
The two inputs of the error amplifier 111 are for receiving, for example, a positive temperature coefficient voltage and, for example, a negative temperature coefficient voltage, respectively, and the output of the error amplifier 111 generates a control voltage, for example, from the positive temperature coefficient voltage and the negative temperature coefficient voltage. Illustratively, the output of the error amplifier 111 may be connected to the second sub-circuit 132, and the control voltage generated by the output of the error amplifier 111 can cause the second sub-circuit 132 to be in an on state, thereby causing the second sub-circuit 132 to be in communication with the first sub-circuit 131.
The first sub-circuit 131 is configured to generate the mirror current Im based on the driving current Id, the second sub-circuit 132 is configured to turn on the second sub-circuit 132 and the first sub-circuit 131 based on the control voltage generated at the output terminal of the error amplifier 113, and generate the enable signal BGOK for triggering the reference voltage Vbg according to the voltage between the first sub-circuit 131 and the second sub-circuit 132 after the turn-on (i.e., the potential of the first node a). It should be noted that the first sub-circuit 131 and the second sub-circuit 132 are turned on, which means that the first sub-circuit 131 and the second sub-circuit 132 form a circuit loop. Illustratively, one end of the first sub-circuit 131, which is not connected to the second sub-circuit 132, is connected to the power supply terminal Vdd, one end of the second sub-circuit 132, which is not connected to the first sub-circuit 131, is grounded, and both the first sub-circuit 131 and the second sub-circuit 132 are in an on state, so that the first sub-circuit 131 and the second sub-circuit 132 form a circuit loop.
It will be appreciated that after the drive current module 110 provides the drive current Id to bring the reference voltage Vbg generated by the reference generating module 120 to the desired operating voltage value, since the reference voltage Vbg is a zero temperature coefficient voltage generated by, for example, superimposing a positive temperature coefficient voltage and, for example, a negative temperature coefficient voltage, the error amplifier 111 generates a control voltage at its output terminal according to the received positive temperature coefficient voltage and negative temperature coefficient voltage when the reference voltage Vbg reaches the desired operating voltage value, and causes the second sub-circuit 132 to be turned on. Since the second sub-circuit 132 is disposed in series with the first sub-circuit 131, and the first sub-circuit 131 is capable of generating the mirror current Im based on the driving current Id, the first sub-circuit 131 and the second sub-circuit 132 form an on-circuit. Due to the difference in voltage dividing capability of the first sub-circuit 131 and the second sub-circuit 132, the enable signal BGOK is generated based on the voltage of the first node a between the first sub-circuit 131 and the second sub-circuit 132.
According to the reference voltage circuit provided by the embodiment of the application, the generation of the enabling signal based on the positive temperature coefficient voltage and the negative temperature coefficient voltage after the reference voltage reaches the ideal working voltage value is ensured, so that the accuracy of matching the enabling signal with the reference voltage can be improved, and the influence of device manufacturing process deviation on the accuracy of the enabling signal is reduced. Meanwhile, the reference voltage circuit is simple in structure, so that the required chip manufacturing area can be saved, and meanwhile, the manufacturing cost can be saved.
The accuracy of the enable signal generated by the reference voltage circuit can reach more than 95%. As an example, when the ideal operating voltage value of the reference voltage Vbg is 1.226V, the voltage value of the reference voltage Vbg when the reference voltage circuit provided by the present application generates the enable signal BGOK is 1.225V, and it can be determined that the error rate of the enable signal BGOK is as low as 2.3%.
In some embodiments, as shown in fig. 3, with the first sub-circuit 131 and the second sub-circuit 132 turned on, the voltage pull-up capability of the first sub-circuit 131 may be lower than the voltage pull-down capability of the second sub-circuit 132. It can be understood that, after the driving current module 110 provides the driving current Id to make the reference voltage Vbg generated by the reference generating module 120 reach the ideal operating voltage value, the second sub-circuit 132 is turned on, and the first sub-circuit 131 and the second sub-circuit 132 form an on circuit, since the voltage pull-up capability of the first sub-circuit 131 is lower than the voltage pull-down capability of the second sub-circuit 132, the first node a can be made to be at a low level, and the enable signal BGOK can be generated according to the first node a being at a low level.
Fig. 4 is a circuit schematic of the reference voltage circuit 100-1 according to an embodiment of the present application. As shown in fig. 4, the first sub-circuit 131 in the enable generation module 130 includes a first transistor Q1 (e.g., PMOS transistor) and a first resistor R1 connected in parallel, and the second sub-circuit 132 includes a second transistor Q2 (e.g., NMOS transistor). Illustratively, the first resistor R1 may be a pull-up resistor, for example, for enabling the first node a to be high before the second sub-circuit 132 of the first sub-circuit 131 is not turned on.
Illustratively, a first terminal (e.g., source terminal) of the first PMOS transistor Q1 is connected to the power supply terminal Vdd, a second terminal (e.g., drain terminal) of the first PMOS transistor Q1 is connected to the first node a, a control terminal (e.g., gate terminal) of the first PMOS transistor Q1 is connected to the driving current module 110, and the gate terminal of the first PMOS transistor Q1 generates the mirror current Im flowing through the first PMOS transistor Q1 based on the circuit structure control in the driving current module 110. The mirror current Im may be implemented by a current mirror circuit in the driving current module 110, for example, and the current mirror circuit may be implemented in any circuit structure capable of mirroring the driving current Id to the mirror current Im, which is not particularly limited in the present application.
A first terminal (e.g., drain terminal) of the second NMOS transistor Q2 is connected to the first node a, and a second terminal (e.g., source terminal) of the second NMOS transistor Q2 is grounded. The control terminal (e.g., gate terminal) of the second NMOS transistor Q2 is connected to the output terminal of the error amplifier 111, and the error amplifier 111 outputs a control voltage according to the positive temperature coefficient voltage and the negative temperature coefficient voltage corresponding to the reference voltage Vbg reaching the ideal operating voltage value, and the control voltage turns on the second NMOS transistor Q2, so that the power supply terminal Vdd, the first PMOS transistor Q1, the first resistor R1, and the second NMOS transistor Q2 form an on circuit.
For example, in the case where the voltage pull-up capability of the first sub-circuit 131 composed of the first PMOS transistor Q1 and the first resistor R1 is lower than the voltage pull-down capability of the second sub-circuit 132 composed of the second NMOS transistor Q2, the enable generation module 130 may be turned on to make the first node a low, and thus the enable signal BGOK may be generated according to the first node a being low.
It should be noted that the first PMOS transistor Q1 in this embodiment may be replaced by, for example, a PNP transistor, and the second NMOS transistor Q2 may be replaced by, for example, an NPN transistor, which is not particularly limited in the present application. Since the matching of complementary metal oxide semiconductors (complementary metal oxide semiconductor, CMOS) is superior, in this embodiment, the first transistor and the second transistor are implemented using CMOS devices.
As shown in fig. 4, in this embodiment, the driving current module 110 of the reference voltage circuit 100-1 may include: a third transistor (e.g., NMOS transistor) Q3, a fourth transistor (e.g., NMOS transistor) Q4, a current mirror 112, and a master switch transistor Qmc. Wherein the current mirror 112 includes a bias branch 1121 and a first mirror branch 1122 in parallel.
Illustratively, a first terminal (e.g., drain terminal) of the third NMOS transistor Q3 is connected to the second node B, and a second terminal (e.g., source terminal) of the third NMOS transistor Q3 is grounded. A first terminal (e.g., drain terminal) of the fourth NMOS transistor Q4 is connected to the bias branch 1121 in the current mirror 112, a second terminal (e.g., source terminal) of the fourth NMOS transistor Q4 is connected to one input terminal (e.g., an input terminal for receiving a negative temperature coefficient voltage) of the error amplifier 111, and is grounded through the reference generation module 120. A control terminal (e.g., a gate terminal) of the fourth NMOS transistor Q4 is connected to the first node a.
Illustratively, the bias branch 1121 of the current mirror 112 is used to generate the drive current Id, and the first mirror branch 1122 of the current mirror 112 is connected to the second node B. A first terminal (e.g., drain terminal) of the main switch tube Qmc is connected to the bias branch 1121, a second terminal (e.g., source terminal) of the main switch tube Qmc is connected to the reference generating module 120, and a control terminal (e.g., gate terminal) of the main switch tube Qmc is connected to the second node B.
In some embodiments, the first PMOS transistor Q1 in the first sub-circuit 131 in the enable generating module 130 may be configured to generate the mirror current Im flowing through the first PMOS transistor Q1 based on the bias branch 1121 in the current mirror 112. In other words, the first PMOS transistor Q1 in the first sub-circuit 131 may act as another mirror leg in the current mirror 112, mirroring the mirror current Im that generates the drive current Id. The first sub-circuit 131, as another mirror branch in the current mirror 112, can cause a plurality of circuit blocks (e.g., the driving circuit block 110 and the enable generation block 130) in the reference voltage circuit 100-1 to synchronously perform operations.
In some implementations, the bias branch 1121 in the current mirror 112 can include a fifth transistor (e.g., PMOS transistor) Q5 and the first mirror branch 1122 can include a sixth transistor (e.g., PMOS transistor) Q6. Specifically, first terminals (e.g., source terminals) of the fifth PMOS transistor Q5 and the sixth PMOS transistor Q6 are connected to the power supply terminal Vdd, control terminals (e.g., gate terminals) of the fifth PMOS transistor Q5, the sixth PMOS transistor Q6, and the first PMOS transistor Q1 are connected to each other, a gate terminal of the fifth PMOS transistor Q5, a second terminal (e.g., drain terminal) of the fifth PMOS transistor Q5, and a drain terminal of the main control switch transistor Qmc are connected to each other, and a second terminal (e.g., drain terminal) of the sixth PMOS transistor Q6 is connected to the second node B. Illustratively, the main control switch transistor Qmc may comprise an NMOS transistor or an NPN transistor, which is not particularly limited by the present application.
It can be appreciated that the first resistor R1 makes the first node a high in an initial stage of the connection of the reference voltage circuit 100-1 to the power supply terminal Vdd in the process of generating the driving current Id by the driving current module 110. At this time, the reference voltage Vbg does not reach the ideal operating voltage value, and the enable signal BGOK cannot be generated to be high from the first node a. The active enable signal BGOK is generated based on the reference voltage Vbg reaching the ideal operating voltage value, that is, the reference voltage Vbg reaching the ideal operating voltage value can be used to trigger other circuit blocks.
Further, since the drain terminal of the fourth NMOS transistor Q4, the drain terminal of the fifth PMOS transistor Q5, and the gate terminal of the fifth PMOS transistor Q5 are commonly connected to the same node and the source terminal of the fourth NMOS transistor Q4 is grounded through the reference generating module 120, since the first node a connected to the gate terminal of the fourth NMOS transistor Q4 is at a high level, the node commonly connected to the drain terminal of the fifth PMOS transistor Q5 and the gate terminal thereof is at a low level under the action of the fourth NMOS transistor Q4, so that the bias branch 1121 formed by the fifth PMOS transistor Q5 of the current mirror 112 and the first mirror branch 1122 formed by the sixth PMOS transistor Q1 and the first PMOS transistor Q1 in the first sub-circuit 131 are turned on, thereby generating the driving current Id flowing through the fifth PMOS transistor Q5, and simultaneously generating the first mirror current Im' flowing through the sixth PMOS transistor Q6 and the mirror current Im flowing through the first PMOS transistor Q1.
Further, in the case where the current mirror 112 is turned on, since the reference voltage Vbg generated by the reference generating module 120 does not reach the ideal operating voltage value, the output terminal of the error amplifier 111 outputs the control voltage of the low level, thereby turning off the third NMOS transistor Q3 and turning off the second NMOS transistor Q2. The voltage of the first node a is still at a high level, and thus, the enable generation module 130 cannot generate the enable signal BGOK in effect on the condition that the reference voltage Vbg generated by the reference generation module 120 does not reach the ideal operating voltage value.
Meanwhile, since the sixth PMOS transistor Q6 in the current mirror 112 is turned on, the second node B is turned on, so that the gate terminal of the main control switch tube Qmc connected to the second node B is turned on under the voltage control of the second node B, and the driving current Id generated by the fifth PMOS transistor Q5 in the current mirror 112 drives the reference generating module 120 to generate the reference voltage Vbg reaching the desired operating voltage value.
Further, under the condition that the reference voltage Vbg generated by the reference generating module 120 reaches the ideal operating voltage value, the output terminal of the error amplifier 111 outputs a control voltage of high level, so that the third NMOS transistor Q3 is turned on and the second NMOS transistor Q2 is turned on, and the first PMOS transistor Q1 and the second NMOS transistor Q2 form an on circuit. When the voltage pull-up capability of the first sub-circuit 131 composed of the first PMOS transistor Q1 and the first resistor R1 is lower than the pull-down capability of the second sub-circuit 132 composed of the second NMOS transistor Q2, the enable generation module 130 may make the first node a low after being turned on, and further may generate the effective enable signal BGOK according to the first node a being low.
Meanwhile, since the gate terminal of the fourth NMOS transistor Q4 connected to the first node a is at a low level, the fourth NMOS transistor Q4 may be turned off, thereby preventing the turn-on of the fourth NMOS transistor Q4 from interfering with the generation of the reference voltage Vbg by the reference generating module 120.
It is noted that the fifth PMOS transistor Q5 may be replaced by, for example, a PNP type transistor, and the sixth PMOS transistor Q6 may be replaced by, for example, a PNP type transistor, which is not particularly limited in the present application. In this embodiment mode, in order to match the fifth transistor and the sixth transistor with the first transistor, the fifth transistor and the sixth transistor are implemented using a CMOS device. It will be appreciated by those skilled in the art that the "matching" described herein is such that the device parameters (e.g., mobility, gate oxide capacitance, and overdrive voltage) that make up the current mirror remain consistent, thereby performing the function of the current mirror. As an example, the feature sizes of the fifth transistor, the sixth transistor, and the first transistor are the same. Likewise, the third NMOS transistor Q3 and the fourth NMOS transistor Q4 may each be replaced by, for example, NPN transistors, which are not particularly limited in the present application.
In some embodiments, the channel width to length ratio of the second NMOS transistor Q2 is greater than the channel width to length ratio of the third NMOS transistor Q3, thereby providing the second NMOS transistor Q2 with a greater voltage pull-down capability, e.g., such that the pull-down capability of the second NMOS transistor Q2 is greater than the pull-up capability of the first PMOS transistor. Illustratively, when the current flowing through the first resistor R1 is much smaller than the mirror current Im flowing through the first PMOS transistor Q1, the pull-down capability of the first sub-circuit 131 including the second NMOS transistor Q2 can be made larger than the pull-up capability of the first sub-circuit 131 including the first PMOS transistor Q1 and the first resistor R1. By reasonably setting the channel width-to-length ratio of the second transistor of the third transistor, the generated enabling signal BGOK is more accurate.
In some embodiments, the channel width-to-length ratio of the fourth NMOS transistor Q4 is reduced to reduce the switching speed of the fourth NMOS transistor Q4, thereby ensuring that the error amplifier 111 connected to the source terminal of the fourth NMOS transistor Q4 has a sufficient response time. In other words, based on the response time of the error amplifier 111, the channel width-to-length ratio of the fourth NMOS transistor Q4 may be less than a predetermined threshold, for example, less than 0.1. As another example, the fourth NMOS transistor Q4 may be replaced by a plurality of NMOS transistors connected in series, thereby ensuring that the error amplifier 111 has a sufficient response time, which is advantageous in that the generated enable signal BGOK is more accurate.
Fig. 5 is a circuit schematic of a reference voltage circuit 100-2 according to another embodiment of the application. Wherein like reference numerals refer to like circuit modules or elements, and the present application will not be repeated. As shown in fig. 5, in this embodiment, the reference generation module 120 of the reference voltage circuit 100-2 includes: the first switching element group 121, the second switching element group 122, the second resistor R2, the third resistor R3, and the fourth resistor R4.
Illustratively, a first end of the first switching element group 121 is grounded, a second end of the first switching element group 121 is connected to the fourth node D through the second resistor R2, and a control end of the first switching element group 121 and a second end of the second switching element group 122 are connected to the third node C. The first end of the second switching element group 122 is grounded through a third resistor R3, the second end of the second switching element group 122 is connected to a fourth node D through a fourth resistor R4, and the control end of the second switching element group 122 is connected to a third node C. The voltage of the third node C is a negative temperature coefficient voltage, the voltage of the second end of the second switching element group 122 is a positive temperature coefficient voltage, the voltage of the fourth node D is a reference voltage Vbg, and the fourth node D is further connected to the source end of the main control switching tube Qmc.
In this embodiment, the first switching element group 121 may include M first switching tubes Q7 connected in parallel, and the second switching element group 122 may include N second switching tubes Q8 connected in parallel, where M and N are positive integers, and 1+.m < N. Specifically, the first switching tube Q7 and the second switching tube Q8 are NPN transistors, the first ends of the first switching tube Q7 and the second switching tube Q8 are collectors, and the second ends of the first switching tube Q7 and the second switching tube Q8 are emitters. Illustratively, the resistance values of the second resistor R2 and the fourth resistor R4 may be equal.
As can be appreciated, when the main control switching tube Qmc is turned on, the driving current module 110 generates the driving current Id and provides the driving current Id to the reference generating module 120, and the currents flowing through the first and second switching element groups 121 and 122 can be equalized. The second switching element group 122 is connected to the third resistor R3, and generates a voltage difference across the third resistor R3 to form a positive temperature coefficient current. The positive temperature coefficient current flows through the third resistor R3 and the branch where the second switching element group 122 is located, and a positive temperature coefficient voltage is generated at the collector of the second switching element group 122. At the same time, a negative temperature coefficient voltage is generated at the voltage of the collector of the first switching element group 121, thereby generating a zero temperature coefficient reference voltage Vbg at the fourth node D connected to the second resistor R2 and the fourth resistor R4, and generating the reference voltage Vbg of the reference generating module 120 is realized.
In practical applications, the number of the switching tubes in the first switching element group 121 and the second switching element group 122 may be specifically set according to practical requirements, which is not specifically limited in the present application. As an example, the first switching element group 121 may include one first switching tube Q7, and the second switching element group 122 may include eight second switching tubes Q8 (not shown) connected in parallel.
In some embodiments, the reference voltage circuit described in any of the above embodiments may further include an inverter 140, an input terminal of the inverter 140 is connected to the first node a, and an output terminal of the inverter 140 generates the enable signal BGOK according to the voltage of the first node a. Illustratively, when the first node a is low, the enable signal BGOK generated at the output of the inverter 140 is active high.
The above description is only illustrative of the preferred embodiments of the present application and of the principles of the technology employed. It will be appreciated by persons skilled in the art that the scope of the application referred to in the present application is not limited to the specific combinations of the technical features described above, but also covers other technical features formed by any combination of the technical features described above or their equivalents without departing from the inventive concept. Such as the above-mentioned features and the technical features disclosed in the present application (but not limited to) having similar functions are replaced with each other.
Claims (17)
1. A reference voltage circuit, comprising:
a drive current module configured to generate a drive current;
a reference generation module configured to generate a first voltage, a second voltage, and a reference voltage based on the driving current;
an enable generation module comprising a first sub-circuit and a second sub-circuit connected in series;
the two input ends of the error amplifier respectively receive the first voltage and the second voltage, and the output end of the error amplifier generates a control voltage;
the first sub-circuit is configured to generate a mirror current based on the drive current; and
the second sub-circuit is configured to turn on the second sub-circuit and the first sub-circuit based on the control voltage, and generate an enable signal for triggering the reference voltage according to a voltage between the first sub-circuit and the second sub-circuit after being turned on.
2. The reference voltage circuit of claim 1, wherein a voltage pull-up capability of the first sub-circuit is lower than a voltage pull-down capability of the second sub-circuit with the first sub-circuit and the second sub-circuit turned on.
3. The reference voltage circuit of claim 1 or 2, wherein the first sub-circuit comprises a first transistor and a first resistor in parallel, and the second sub-circuit comprises a second transistor, wherein,
a first end of the first transistor is connected with a power supply end, a second end of the first transistor is connected to a first node, a control end of the first transistor is connected with the driving current module, and the control end of the first transistor is used for controlling generation of the mirror current flowing through the first transistor;
the first end of the second transistor is connected to the first node, the second end of the second transistor is grounded, and the control end of the second transistor is used for enabling the second transistor to be turned on or off based on the control voltage, wherein the enabling signal is generated based on the voltage of the first node.
4. A reference voltage circuit according to claim 3, wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor.
5. The reference voltage circuit of claim 4, wherein the drive current module comprises: the current mirror comprises a bias branch and a first mirror branch which are connected in parallel;
a first end of the third transistor is connected to the second node, a second end of the third transistor is grounded, and a control end of the third transistor is connected with an output end of the error amplifier;
a first end of the fourth transistor is connected to the bias branch, a second end of the fourth transistor is connected to one input end of the error amplifier and is grounded through the reference generating module, and a control end of the fourth transistor is connected to the first node;
the bias branch is used for generating a driving current, and the first mirror branch is connected to the second node;
the first end of the main control switch tube is connected to the bias branch, the second end of the main control switch tube is connected to the reference generation module, and the control end of the main control switch tube is connected to the second node.
6. The reference voltage circuit of claim 5, wherein the first transistor is configured to generate the mirror current through the first transistor based on the drive current generated by the bias branch.
7. The reference voltage circuit of claim 6 wherein the bias arm comprises a fifth transistor and the first mirror arm comprises a sixth transistor, wherein,
the first ends of the fifth transistor and the sixth transistor are connected to the power source terminal, the control ends of the fifth transistor, the sixth transistor and the first transistor are connected to each other, the second ends of the fifth transistor, the control end of the fifth transistor and the first end of the main control switch transistor are connected to each other, and the second end of the sixth transistor is connected to the second node.
8. The reference voltage circuit of claim 7, wherein the fifth transistor and the sixth transistor are P-type transistors.
9. The reference voltage circuit of claim 8, wherein the third transistor and the fourth transistor are each N-type transistors.
10. The reference voltage circuit of claim 9, wherein the second transistor has a channel width to length ratio that is greater than a channel width to length ratio of the third transistor.
11. The reference voltage circuit of claim 10, wherein the fourth transistor has a channel width to length ratio of less than 0.1 based on a response time of the error amplifier.
12. The reference voltage circuit of claim 9 or 11, wherein the master switching tube is an N-type transistor.
13. The reference voltage circuit of claim 12, wherein the reference generation module comprises: a first switching element group, a second resistor, a third resistor and a fourth resistor, wherein,
a first end of the first switching element group is grounded, a second end of the first switching element group is connected to a fourth node through the second resistor, and a control end of the first switching element group and the second end of the first switching element group are connected to a third node;
the first end of the second switching element group is grounded through the third resistor, the second end of the second switching element group is connected to the fourth node through the fourth resistor, the control end of the second switching element group is connected to the third node,
the voltage of the third node is the second voltage, the voltage of the second end of the second switching element group is the first voltage, the voltage of the fourth node is the reference voltage, and the fourth node is connected with the second end of the main control switching tube.
14. The reference voltage circuit of claim 13, wherein the first switching element group comprises M first switching tubes connected in parallel, and the second switching element group comprises N second switching tubes connected in parallel, wherein M and N are positive integers, and 1+m < N.
15. The reference voltage circuit of claim 14, wherein the first and second switching transistors are NPN transistors, first ends of the first and second switching transistors are collectors, and second ends of the first and second switching transistors are emitters.
16. A reference voltage circuit as claimed in claim 3, further comprising an inverter, an input of the inverter being connected to a first node, an output of the inverter generating the enable signal in dependence on a voltage of the first node.
17. A three-dimensional memory comprising peripheral circuitry comprising the reference voltage circuit of any one of claims 1 to 16.
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