CN118432027B - Improved generation current-limiting circuit - Google Patents
Improved generation current-limiting circuit Download PDFInfo
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- CN118432027B CN118432027B CN202410897067.3A CN202410897067A CN118432027B CN 118432027 B CN118432027 B CN 118432027B CN 202410897067 A CN202410897067 A CN 202410897067A CN 118432027 B CN118432027 B CN 118432027B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
- H02H9/025—Current limitation using field effect transistors
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Abstract
The invention relates to an improved current limiting circuit, and belongs to the technical field of electronics. The improved current limiting circuit comprises a power tube current sampling circuit, a current comparator and a voltage comparator. In the structure of the improved current limiting circuit, reference current and reference voltage are introduced simultaneously, and the power tube current sampling circuit and the reference current output control voltage through a current comparator, and a switching tube is controlled to obtain sampling voltage; the sampling voltage and the reference comparison voltage output a control signal through a comparator to control the grid voltage of the power tube; therefore, the power consumption of the current circuit is reduced, and the precision of the current limiting circuit is ensured. The improved current limiting circuit has simple structure and low cost, and can be widely applied to various quick charging devices.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to the technical field of integrated circuits, and specifically relates to an improved current limiting circuit.
Background
With the development of semiconductor technology, various mobile devices and vehicle-mounted charging devices with a rapid charging function are becoming more and more popular. With the increase of switching current and charging voltage, the charging power of the power tube is higher and higher, and in some situations, load current needs to be limited, and a current limiting circuit is inevitably needed to be introduced into the circuit.
As shown in FIG. 1, the conventional current limiting circuit obtains equal proportion current through the proportional mirror image of the power tubes N11 and N12; then, the output signal V11 of the sampling tube N12 is compared with the voltage of the output VOUT by using an operational amplifier 11, the switching tube P11 is controlled to be opened and closed by using the output signal of the amplifier 11, the voltage of the sampling current falling on R11 is compared with a reference voltage Vref by using the operational amplifier 12, and the output of the operational amplifier 12 controls the grid voltage GATE of the power tube, so that the current is limited to a preset protection threshold. Since the conventional current limiting circuit requires circuits such as the operational amplifier 11, the operational amplifier 12, the reference voltage, etc., the circuit structure is complex, and the current limiting circuit has high self-power consumption, so that it is difficult to realize the current limiting circuit with extremely low power consumption.
Patent application CN202310192988.5 discloses a current limiting circuit without reference voltage, as shown in fig. 2. The working principle is that when the current on the power transistor QN is smaller, the current on the sampling tube is also smaller in equal proportion, so that the voltage drop on the resistor R21 is smaller than the voltage drop on the resistor R22, the source voltage of the transistor Q1 is higher than the source voltage of the transistor Q2, the gate-source voltage of the transistor Q2 is smaller than the gate-source voltage of the transistor Q1, the pull-up current of the transistor Q2 is smaller than the pull-down current of the transistor Q5, the pull-up capability of the transistor Q2 is smaller than the pull-down capability of the transistor Q5, the drain voltage of the transistor Q2 is reduced, namely the gate voltage of the transistor Q6 is reduced, the pull-down current of the transistor Q6 is reduced, the gate voltages of the power transistor QN and the sampling tube are increased, the resistance of the power transistor QN is reduced, and the current supply capability of the power transistor QN is increased. When the current on the power transistor QN is larger, the current on the sampling tube is also equally proportional, so the voltage drop on the resistor R21 is larger than the voltage drop on the resistor R22, so the source voltage of the transistor Q1 is lower than the source voltage of the transistor Q2, so the gate source voltage of the transistor Q2 is larger than the gate source voltage of the transistor Q1, so the pull-up current of the transistor Q2 is larger than the pull-down current of the transistor Q5, so the pull-up capability of the transistor Q2 is larger than the pull-down capability of the transistor Q5, the drain voltage of the transistor Q2 rises, namely the gate voltage of the transistor Q6 rises, the pull-down current of the transistor Q6 increases, so the gate voltages of the power transistor QN and the sampling tube decrease, so the resistance of the power transistor QN increases, and thus the supply current capability of the power transistor QN decreases. As can be seen from the patent CN202310192988.5, although the current limiting circuit provided by the present invention reduces a part of power consumption because no reference voltage is introduced, the drain terminal of the Q6 switching tube directly controls the gate of the power tube, which is necessarily affected directly by the process angle deviation and the temperature, especially when the current limiting value is very small, the error will be more serious, so that the accuracy of the current limiting value of the whole current limiting circuit is not high.
Therefore, there is a need to develop an improved current limiting circuit that can effectively reduce power consumption and provide stable current limiting accuracy.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide an improved current limiting circuit which can effectively reduce power consumption and provide stable current limiting precision.
In order to achieve the above object, an improved current limiting circuit of the present invention has the following constitution:
It comprises the following steps: the power tube current sampling circuit, the current comparator and the voltage comparator;
The power tube current sampling circuit is used for sampling the load current of the power tube N1 in real time to obtain a sampling current; an input voltage VIN provides a GATE voltage GATE to the power tube N1 and the sampling tube N2 through an output end of a Charge pump (Charge pump); the width-to-length ratio of the power tube N1 to the sampling tube N2 is N:1; the drain end of the power tube N1 is connected with the input voltage VIN, and the source end of the power tube N1 is connected with the source end of the sampling tube N2 and the output voltage VOUT;
The drain end of the sampling tube N2 is connected with one input end of the current comparator, and the other input end of the current comparator is connected with reference current;
the voltage comparator comprises an input voltage comparator M1 and a base reference voltage Vref; the reference voltage Vref is connected with the positive input end of the input voltage comparator M1; the negative input end of the input voltage comparator M1 is connected with the output end of the current comparator; the output end of the input voltage comparator M1 is connected with the gate end of the power tube N1.
In the improved current limiting circuit, the output end of the current comparator is connected with the negative input end of the input voltage comparator M1 through a first switching tube S1; the negative input end of the input voltage comparator M1 is also connected with the upper end of a third resistor R3, the lower end of the third resistor R3 is grounded to GND, and the output end of the input voltage comparator M1 is connected with the gate end of the power tube N1 through a second switch tube S2.
In the improved current limiting circuit, the current comparator comprises a reference current source ibias as the reference current;
The reference comparison current ibias is connected with the drain end of the NMOS current mirror;
The gate end and the drain end of a fifth NMOS tube N5 in the NMOS current mirror are short-circuited together, and meanwhile, the gate ends of a third NMOS tube N3 and a fourth NMOS tube N4 are connected, and the source end of the fifth NMOS tube N5 is grounded;
The width-to-length ratio of the third NMOS tube N3 to the fourth NMOS tube N4 is 1:1, the source ends are all grounded, the drain end of the third NMOS tube N3 is connected with the input end of the first switch tube S1 and is connected with the lower end of the voltage stabilizing tube D1 and the drain end of the first PMOS tube P1;
The gate end and the drain end of the first PMOS tube are in short circuit and connected with the gate end of the second PMOS tube P2 to form a current mirror, and the width-to-length ratio of the first PMOS tube to the second PMOS tube is 1:1; the source end of the first PMOS tube P1 is connected with the drain end of the sampling tube N2 and is connected with the lower end of the first resistor R1;
The drain end of the second PMOS tube P2 is connected with the drain end of the fourth NMOS tube N4; the source end of the second PMOS tube P2 is connected with the upper end of the voltage stabilizing tube D1 and the lower end of the second resistor R2;
the upper end of the voltage stabilizing tube D1 is also connected with the upper end of the first switching tube S1;
the upper end of the first resistor R1 and the upper end of the second resistor R2 are both connected with an input VIN; the lower end of the first resistor R1 is also connected with the drain end of the sampling tube N2; and the first resistor and the second resistor have equal resistance values.
The improved current limiting circuit comprises a power tube current sampling circuit, a current comparator and a voltage comparator. In the structure of the improved current limiting circuit, reference current and reference voltage are introduced simultaneously, and the power tube current sampling circuit and the reference current output control voltage through a current comparator, and a switching tube is controlled to obtain sampling voltage; the sampling voltage and the reference comparison voltage output a control signal through a comparator to control the grid voltage of the power tube; therefore, the power consumption of the current circuit is reduced, and the precision of the current limiting circuit is ensured. The improved current limiting circuit has simple structure and low cost, and can be widely applied to various quick charging devices.
Drawings
FIG. 1 is a schematic diagram of a conventional current limiting circuit;
FIG. 2 is a schematic diagram of a current limiting circuit without reference voltage in the prior art;
FIG. 3 is a schematic block diagram of an improved current limiting circuit of the present invention;
FIG. 4 is a schematic diagram of an improved current limiting circuit according to the present invention;
FIG. 5 is a circuit diagram of an embodiment of an improved current limiting circuit according to the present invention;
FIG. 6 is a schematic diagram of the current limiting circuit structure of FIG. 3 for simulating the current limiting value variation at different process angles and temperatures during 50mA current limiting;
FIG. 7 is a schematic diagram of the current limiting value change at different process angles and temperatures at 50mA current limiting according to the invention.
Detailed Description
In order to make the technical contents of the present invention more clearly understood, the following examples are specifically described.
Referring to fig. 3, a schematic block diagram of an improved current limiting circuit according to the present invention is shown.
In one embodiment, the improved current limiting circuit of the present invention, as shown in fig. 3, comprises: the power tube current sampling circuit, the current comparator and the voltage comparator.
As shown in fig. 4, the power tube current sampling circuit is configured to sample the load current of the power tube N1 in real time to obtain a sampling current; an input voltage VIN provides a GATE voltage GATE to the power tube N1 and the sampling tube N2 through an output end of a Charge pump (Charge pump); the width-to-length ratio of the power tube N1 to the sampling tube N2 is N:1; the drain end of the power tube N1 is connected with the input voltage VIN, and the source end of the power tube N1 is connected with the source end of the sampling tube N2 and the output voltage VOUT;
The drain end of the sampling tube N2 is connected with one input end of the current comparator, and the other input end of the current comparator is connected with reference current;
the voltage comparator comprises an input voltage comparator M1 and a base reference voltage Vref; the reference voltage Vref is connected with the positive input end of the input voltage comparator M1; the negative input end of the input voltage comparator M1 is connected with the output end of the current comparator; the output end of the input voltage comparator M1 is connected with the gate end of the power tube N1.
In a preferred embodiment, the output terminal of the current comparator is connected to the negative input terminal of the input voltage comparator M1 through a first switching tube S1; the negative input end of the input voltage comparator M1 is also connected with the upper end of a third resistor R3, the lower end of the third resistor R3 is grounded to GND, and the output end of the input voltage comparator M1 is connected with the gate end of the power tube N1 through a second switch tube S2.
In a more preferred embodiment, the current comparator includes a reference current source ibias as the reference current;
The reference comparison current ibias is connected with the drain end of the NMOS current mirror;
The gate end and the drain end of a fifth NMOS tube N5 in the NMOS current mirror are short-circuited together, and meanwhile, the gate ends of a third NMOS tube N3 and a fourth NMOS tube N4 are connected, and the source end of the fifth NMOS tube N5 is grounded;
The width-to-length ratio of the third NMOS tube N3 to the fourth NMOS tube N4 is 1:1, the source ends are all grounded, the drain end of the third NMOS tube N3 is connected with the input end of the first switch tube S1 and is connected with the lower end of the voltage stabilizing tube D1 and the drain end of the first PMOS tube P1;
The gate end and the drain end of the first PMOS tube are in short circuit and connected with the gate end of the second PMOS tube P2 to form a current mirror, and the width-to-length ratio of the first PMOS tube to the second PMOS tube is 1:1; the source end of the first PMOS tube P1 is connected with the drain end of the sampling tube N2 and is connected with the lower end of the first resistor R1;
The drain end of the second PMOS tube P2 is connected with the drain end of the fourth NMOS tube N4; the source end of the second PMOS tube P2 is connected with the upper end of the voltage stabilizing tube D1 and the lower end of the second resistor R2;
the upper end of the voltage stabilizing tube D1 is also connected with the upper end of the first switching tube S1;
the upper end of the first resistor R1 and the upper end of the second resistor R2 are both connected with an input VIN; the lower end of the first resistor R1 is also connected with the drain end of the sampling tube N2; and the first resistor and the second resistor have equal resistance values.
In practical applications, the improved current limiting circuit of the present invention may be implemented using the specific circuit shown in fig. 5.
The N1 tube of the current sampling circuit is a power tube, the N2 tube is a sampling tube, the sampling ratio of the N1 tube and the N2 tube is N:1, the width-length ratio=the current sampling ratio, and the current flowing through the N1 tube and the N2 tube is N:1. The specific ratio may be adjusted as desired. MOS pipe N3, N4, N5 constitute the current mirror, wherein N3: n4: n5=1:1:1, i.e. i1:i2=1:1 in the figure. According to kirchhoff's current law, the sum of the inflow currents flowing through the same node is equal to the sum of the outflow currents, i5=i4+i1, i6=i2+i3 in the circuit. Since i1=i2, P1 and P2 constitute a 1:1 current mirror, v1=v2. The resistance r1=r2, i5=i6. The first switching tube S1 shown in fig. 4 is replaced with a PMOS switching tube P3, and the second switching tube S2 is replaced with an NMOS switching tube N6. The voltage stabilizing tube D1 ensures that the gate-source voltage difference of the switching tube P3 is within the range of the voltage stabilizing value, and protects the switching tube P3 from being damaged. The reference current ibias can be set to be very small within 1uA, which can effectively reduce the overall power consumption of the circuit.
When the load current is smaller than the set current limit value, the sampling current I4 flowing through the N2 pipe decreases, and since i5=i4+i1, i6=i2+i3, and i1=i2, i5=i6, I3 decreases. Since v3=i3×r3, V3 decreases and is smaller than Vref, the comparator M1 outputs a low level, the GATE voltage of the NMOS switching transistor N6 is controlled, N6 is turned off, GATE is not affected, and the load current is not limited.
Conversely, when the load current is greater than the set current limit value, the sampling current I4 flowing through the N2 pipe increases, and since i5=i4+i1, i6=i2+i3, and i1=i2, i5=i6, I3 increases. Since v3=i3×r3, V3 is raised and greater than Vref, the comparator M1 is turned over, the GATE voltage of the NMOS switching transistor N6 is controlled, N6 is turned on, GATE falls, and as GATE falls, the output current decreases until it falls to a current limit value, functioning as a protection circuit.
The improved circuit of the invention is adopted, and the reference current and the reference voltage are introduced at the same time, so that the power consumption of the current circuit is reduced, and the precision of the current-limiting circuit is ensured. Fig. 6 is a simulation result of a current limiting circuit without reference voltage applied by prior art patent CN202310192988.5, from which we can see that when the current limiting value of this structure is set at a small current limit of 50mA, the current limiting accuracy deviation is large under the process angle and temperature changes. Fig. 7 is a simulation result of an improved current limiting circuit according to the present invention, and it can be seen from the figure that when the current limiting value of the structure is set at a smaller current limit of 50mA, the current limiting accuracy is significantly improved under the process angle and temperature variation.
In addition, in fig. 4, the switching transistors S1 and S2 may be, but are not limited to, devices that perform switching functions, such as MOS transistors and BJTs; in the figure, a MOS transistor, a BJT transistor and the like can be adopted as the current mirror, and the ratio of the currents can be 1:1 but is not limited to 1:1; the module for supplying power to the GATE voltage GATE in the figure can be, but not limited to, a charge pump or a pull-up resistor.
The improved current limiting circuit comprises a power tube current sampling circuit, a current comparator and a voltage comparator. In the structure of the improved current limiting circuit, reference current and reference voltage are introduced simultaneously, and the power tube current sampling circuit and the reference current output control voltage through a current comparator, and a switching tube is controlled to obtain sampling voltage; the sampling voltage and the reference comparison voltage output a control signal through a comparator to control the grid voltage of the power tube; therefore, the power consumption of the current circuit is reduced, and the precision of the current limiting circuit is ensured. The improved current limiting circuit has simple structure and low cost, and can be widely applied to various quick charging devices.
In this specification, the invention has been described with reference to specific embodiments thereof. It will be apparent that various modifications and variations can be made without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (1)
1. An improved current limiting circuit, comprising: the power tube current sampling circuit, the current comparator and the voltage comparator;
The power tube current sampling circuit is used for sampling the load current of the power tube N1 in real time to obtain a sampling current; the input voltage VIN provides a grid voltage GATE to the power tube N1 and the sampling tube N2 through the output end of the charge pump; the width-to-length ratio of the power tube N1 to the sampling tube N2 is N:1; the drain end of the power tube N1 is connected with the input voltage VIN, and the source end of the power tube N1 is connected with the source end of the sampling tube N2 and the output voltage VOUT;
The drain end of the sampling tube N2 is connected with one input end of the current comparator, and the other input end of the current comparator is connected with reference current;
The voltage comparator comprises an input voltage comparator M1 and a base reference voltage Vref; the reference voltage Vref is connected with the positive input end of the input voltage comparator M1; the negative input end of the input voltage comparator M1 is connected with the output end of the current comparator; the output end of the input voltage comparator M1 is connected with the gate end of the power tube N1;
The output end of the current comparator is connected with the negative input end of the input voltage comparator M1 through a first switching tube S1; the negative input end of the input voltage comparator M1 is also connected with the upper end of a third resistor R3, and the lower end of the third resistor R3 is grounded to GND;
The output end of the input voltage comparator M1 is connected with the gate end of the power tube N1 through a second switching tube S2;
the current comparator comprises a reference current source ibias as the reference current;
The reference comparison current ibias is connected with the drain end of the NMOS current mirror;
The gate end and the drain end of a fifth NMOS tube N5 in the NMOS current mirror are short-circuited together, and meanwhile, the gate ends of a third NMOS tube N3 and a fourth NMOS tube N4 are connected, and the source end of the fifth NMOS tube N5 is grounded;
The width-to-length ratio of the third NMOS tube N3 to the fourth NMOS tube N4 is 1:1, the source ends are all grounded, the drain end of the third NMOS tube N3 is connected with the input end of the first switch tube S1 and is connected with the lower end of the voltage stabilizing tube D1 and the drain end of the first PMOS tube P1;
The gate end and the drain end of the first PMOS tube are in short circuit and connected with the gate end of the second PMOS tube P2 to form a current mirror, and the width-to-length ratio of the first PMOS tube to the second PMOS tube is 1:1; the source end of the first PMOS tube P1 is connected with the drain end of the sampling tube N2 and is connected with the lower end of the first resistor R1;
The drain end of the second PMOS tube P2 is connected with the drain end of the fourth NMOS tube N4; the source end of the second PMOS tube P2 is connected with the upper end of the voltage stabilizing tube D1 and the lower end of the second resistor R2;
the upper end of the voltage stabilizing tube D1 is also connected with the upper end of the first switching tube S1;
The upper end of the first resistor R1 and the upper end of the second resistor R2 are both connected with an input VIN; the resistance values of the first resistor and the second resistor are equal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410897067.3A CN118432027B (en) | 2024-07-05 | 2024-07-05 | Improved generation current-limiting circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410897067.3A CN118432027B (en) | 2024-07-05 | 2024-07-05 | Improved generation current-limiting circuit |
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| CN118432027A CN118432027A (en) | 2024-08-02 |
| CN118432027B true CN118432027B (en) | 2024-10-01 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117783643A (en) * | 2024-02-27 | 2024-03-29 | 无锡力芯微电子股份有限公司 | Load current detection system |
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| CN105548672B (en) * | 2016-01-27 | 2023-10-27 | 深圳市瑞之辰科技有限公司 | Overcurrent detection circuit of power switch |
| CN115864343B (en) * | 2023-03-03 | 2023-05-23 | 珠海智融科技股份有限公司 | Current limiting circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117783643A (en) * | 2024-02-27 | 2024-03-29 | 无锡力芯微电子股份有限公司 | Load current detection system |
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