CN114285400A - Level switching circuit, adapter plate and signal generating equipment - Google Patents
Level switching circuit, adapter plate and signal generating equipment Download PDFInfo
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Abstract
The embodiment of the invention provides a level switching circuit, a patch panel and signal generating equipment. The level switching circuit comprises a switching module and a level conversion module, wherein the switching module comprises two paths, and the output end of the first path is connected with the input end of the level conversion module; a node of which the output end of the second path is connected with the output end of the level conversion module is used as a GPIO port; the switching module is used for receiving the control signal and the initial data signal, and selecting one of the two paths to be conducted under the control of the control signal to output the initial data signal; the level conversion module is used for converting the initial data signal output by the first path into a conversion data signal of a required voltage domain and outputting the conversion data signal from a corresponding GPIO port. The level switching circuit is simple in structure, and level switching can be achieved without a relay, so that the problem that the service life of a circuit is shortened due to the relay can be effectively solved.
Description
Technical Field
The invention relates to the technical field of circuit electronics, in particular to a level switching circuit, a patch panel and signal generating equipment.
Background
In embedded systems, it is often necessary to control a number of external devices or circuits, some of which require control signals to be sent to them via a Central Processing Unit (CPU) and some of which require signals to be input to the CPU. Also, many devices or circuits require only two on/off states, such as on and off of a Light Emitting Diode (LED). The control of these devices is complicated by the use of conventional serial or parallel ports. Therefore, a "general purpose programmable I/O port," i.e., a GPIO, is typically provided on an embedded microprocessor.
One GPIO port needs at least two registers, one is used as a GPIO port control register for control, and the other is used as a GPIO port data register for storing data. Each bit of the data register corresponds to a hardware pin of the GPIO, the data transmission direction is set through the control register, and the data flow direction of each bit pin can be set through the control register.
GPIO signals on both sides of the GPIO port may require the use of different voltage domains. For example, the CPU may output a data signal having a voltage domain of 1.8V (i.e., 0 at a low level and 1.8V at a high level), while the external device may require a data signal having a voltage domain of 3.3V (i.e., 0 at a low level and 3.3V at a high level). In this case, level switching is required. The conventional method is to switch the level by using a relay. As is well known, the service life of a relay is calculated by the number of times of opening and closing contacts, and in a frequently applied scenario, the failure of the relay is accelerated, which may reduce the service life of the entire level switching circuit.
Disclosure of Invention
The present invention has been made in view of the above problems. The invention provides a level switching circuit, a patch panel and signal generating equipment.
According to an aspect of the present invention, a level switching circuit is provided, which includes a switching module and a level converting module, wherein the switching module includes two paths, and an output terminal of a first path is connected to an input terminal of the level converting module; a node of which the output end of the second path is connected with the output end of the level conversion module is used as a GPIO port; the switching module is used for receiving the control signal and the initial data signal, and selecting one of the two paths to be conducted under the control of the control signal to output the initial data signal; the level conversion module is used for converting the initial data signal output by the first path into a conversion data signal of a required voltage domain and outputting the conversion data signal from a corresponding GPIO port.
Illustratively, the first path includes a first output control module, wherein the first output control module is configured to receive the control signal and the initial data signal, output the initial data signal when the control signal is at a first level, and stop outputting the initial data signal when the control signal is at a second level.
Illustratively, the first output control module comprises an inverter and a first buffer, wherein an input end of the inverter is used for receiving the control signal with a first level, and an output end of the inverter is used for outputting the inverted control signal with a second level; or the input end of the inverter is used for receiving the control signal with the second level, and the output end of the inverter is used for outputting the inverted control signal with the first level; the enable terminal of the first buffer is connected with the output terminal of the inverter, the data input terminal of the first buffer is used for receiving the initial data signal, and the output terminal of the first buffer is used for outputting the initial data signal under the control that the inverted control signal is at the second level or stopping outputting the initial data signal under the control that the inverted control signal is at the first level.
Illustratively, the second path includes a second output control module, wherein the second output control module is configured to receive the control signal and the initial data signal, output the initial data signal when the control signal is at the second level, and stop outputting the initial data signal when the control signal is at the first level.
Illustratively, the second output control module includes a second buffer, wherein an enable terminal of the second buffer is configured to receive a control signal at a first level or a second level, a data input terminal of the second buffer is configured to receive an initial data signal, and an output terminal of the second buffer is configured to output the initial data signal under the control of the control signal at the second level or stop outputting the initial data signal under the control of the control signal at the first level.
According to another aspect of the invention, there is provided a patch panel, characterized in that it comprises a level switching circuit according to any one of claims 1 to 5.
Illustratively, the level switching circuit comprises two level switching circuits, wherein, the first level switching circuit is used for realizing the switching of the initial data signal from the first voltage domain to the second voltage domain, and the second level switching circuit is used for realizing the switching of the initial data signal from the second voltage domain to the first voltage domain.
According to another aspect of the present invention, there is provided a signal generating apparatus comprising: the adapter plate is realized by adopting the adapter plate, the adapter plate further comprises a connector used for being connected with the signal generator and the screen to be tested, and the signal generator can be connected with the screen to be tested through the adapter plate.
Illustratively, the number of the adapter plates corresponds to the number of the types of the screens to be tested one by one, and each adapter plate is used for realizing data signal conversion of different voltage domains between the signal generator and the corresponding type of the screens to be tested.
Illustratively, the signal generator includes: a controller for outputting a first control signal and a first initial data signal; the screen to be tested is used for outputting a second control signal and a second initial data signal; the adapter plate is used for transmitting the first initial data signal or a first conversion data signal converted from the first initial data signal to the screen to be tested under the control of the first control signal; and/or transmitting the second initial data signal or a second converted data signal converted from the second initial data signal to the controller under the control of the second control signal.
According to the level switching circuit, the adapter plate and the signal generating device provided by the embodiment of the invention, the switching module and the level conversion module are adopted, the switching module comprises two selectable paths, one of the two selectable paths is connected with the level conversion module, the level conversion can be carried out on the initial data signal, and the other path can directly output the initial data signal. The output end of the level conversion module can be connected with the output end of the second path to be used as a GPIO port. In this way, it is possible to select whether to hold or level-shift the voltage domain of the original data signal as desired. The level switching circuit is simple in structure, and level switching can be achieved without a relay, so that the problem that the service life of a circuit is shortened due to the relay can be effectively solved.
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The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail embodiments of the present invention with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings, like reference numbers generally represent like parts or steps.
FIG. 1 shows a schematic block diagram of a level switching circuit according to one embodiment of the present invention;
FIG. 2 shows a schematic block diagram of a level switching circuit and other external circuits or devices associated with the level switching circuit, according to one embodiment of the present invention; and
fig. 3 shows a schematic circuit diagram of a switching module according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, exemplary embodiments according to the present invention will be described in detail below with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a subset of embodiments of the invention and not all embodiments of the invention, with the understanding that the invention is not limited to the example embodiments described herein. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the invention described herein without inventive step, shall fall within the scope of protection of the invention.
To at least partially solve the above problems, embodiments of the present invention provide a level switching circuit, a patch panel, and a signal generating apparatus.
Fig. 1 shows a schematic block diagram of a level switching circuit according to an embodiment of the invention. FIG. 2 shows a schematic block diagram of a level switching circuit and other external circuits or devices associated with the level switching circuit, according to one embodiment of the present invention. It should be noted that the hardware configuration shown in fig. 2 is only an example and not a limitation of the present invention, and the present invention may have other reasonable hardware implementations. For example, the output of the level shifting circuit 100 may be connected to other circuits or devices rather than connectors. Also for example, the connector may be connected to other circuits or devices other than the screen to be tested. Alternatively, the controller in fig. 2 may be any suitable control device, including but not limited to an embedded (arm) control system, a Field Programmable Gate Array (FPGA), or the like.
As shown in fig. 1 and 2, the level switching circuit 100 may include a switching module 120 and a level converting module 140. Illustratively, the level shift module 140 may be implemented by a designed level shift chip.
The switching module 120 may include two paths, wherein an output terminal of a first path is connected to an input terminal of the level shifting module 140; the node at which the output terminal of the second path is connected to the output terminal of the level shifter module 140 serves as a GPIO port.
The switching module 120 may be configured to receive a control signal and an initial data signal, and output the initial data signal by conducting one of two paths under the control of the control signal.
The level conversion module 140 may be configured to convert the initial data signal output by the first path into a conversion data signal of a desired voltage domain and output the conversion data signal from the corresponding GPIO port.
Fig. 3 shows a schematic circuit diagram of the switching module 120 according to one embodiment of the present invention. For ease of understanding, fig. 3 also shows a level shift module 140 and a connector. It should be noted that the circuit structure shown in fig. 3 is only an example and not a limitation of the present invention, and the present invention may have other reasonable circuit implementations.
Referring to fig. 3, two paths of the switching module 120 are shown, a first path line1 and a second path line 2. It is noted that the terms "first," "second," and the like, as used herein, are used for distinguishing between similar elements and not necessarily for describing a sequential or other special purpose.
Referring to fig. 3, an output terminal of the first path line1 is connected to an input terminal of the level shift module 140. The output end of the second path line2 and the output end of the level conversion module 140 converge together to form an output port, i.e., a GPIO port. The GPIO port may be connected to a connector or other circuit or device. The connector shown herein may be connected to the screen to be tested, and configured to transmit a signal output by the controller of the signal generation device to the screen to be tested and/or transmit a signal of the screen to be tested to the controller of the signal generation device.
The first lane line1 and the second lane line2 are used to guide the initial data signal to two different lanes, a level shift lane and a lane holding the original initial data signal, respectively. The first path line1 and the level conversion module 140 may integrally form a module having a level conversion function for level-converting an initial data signal (shown in fig. 3 as Sdata) to obtain a converted data signal. The initial data signal has a first voltage domain and the converted data signal has a second voltage domain. The first voltage domain and the second voltage domain are different. For example, the initial data signal and the converted data signal may be both digital signals including a high level and a low level, the high level of the initial data signal being a level of 1.8V, the low level being 0V; and the high level of the converted data signal may be a level of 3.3V and the low level may be 0V.
The second path line2 may retain the original data signal, i.e., not level-convert the original data signal.
The signals output by both the first path line1 and the second path line2 are staggered in time from each other, i.e., occur in different time periods, respectively. Therefore, the output of the GPIO port may be either the converted data signal obtained through level conversion or the original initial data signal.
With continued reference to fig. 3, the switching module 120 may receive the control signal Sctrl and the initial data signal Sdata. The control signal Sctrl and the data initialization signal Sdata may be from the controller described above. Alternatively, the output terminal of the control signal of the controller may be connected to the control terminal (the input terminal for receiving the control signal) of the switching module 120 to transmit the control signal Sctrl to the control terminal of the switching module 120. Of course, other additional modules, such as a communication module, may be optionally connected between the controller and the switching module 120. The controller may transmit the control signal to the control terminal of the switching module 120 via the additional module. Further, an output of the data signal of the controller may be connected with a data input (an input for receiving the initial data signal) of the switching module 120 to transmit the initial data signal Sdata to the data input of the switching module 120.
The above-mentioned embodiment of outputting the control signal Sctrl and the data initial signal Sdata by the controller is only an example and not a limitation of the present invention, and for example, the control signal Sctrl and the data initial signal Sdata may also be output to the switching module 120 by a connector, a screen to be tested, or other circuits or devices. In the case that the controller or the screen to be tested outputs the control signal Sctrl and the data initial signal Sdata to the switching module 120, the GPIO port may be connected to the controller to transmit the initial data signal or the converted data signal to the controller.
As can be seen from fig. 3, whether the initial data signal Sdata is transmitted from the first path line1 or the second path line2 may be controlled by the control signal Sctrl, wherein the level conversion may be performed via the level conversion module 140 when the initial data signal Sdata is transmitted from the first path line 1.
According to the level switching circuit provided by the embodiment of the invention, the switching module and the level conversion module are adopted, the switching module comprises two selectable paths, one of the two selectable paths is connected with the level conversion module and can be used for carrying out level conversion on the initial data signal, and the other one of the selectable paths can be used for directly outputting the initial data signal. The output end of the level conversion module can be connected with the output end of the second path to be used as a GPIO port. In this way, it is possible to select whether to hold or level-shift the voltage domain of the original data signal as desired. The level switching circuit is simple in structure, and level switching can be achieved without a relay, so that the problem that the service life of a circuit is shortened due to the relay can be effectively solved.
According to an embodiment of the present invention, the first path includes a first output control module, wherein the first output control module is configured to receive the control signal and the initial data signal, output the initial data signal when the control signal is at a first level, and stop outputting the initial data signal when the control signal is at a second level.
The first level and the second level are two levels of different sizes. Preferably, the first level and the second level are each one of a high level and a low level, i.e., the first level is a high level and the second level is a low level, or the first level is a low level and the second level is a high level. The high level here may be any suitable level, such as a common power supply level of 1.8V, 3.3V, 5V, etc. The low level here may be 0V.
In one example, the first level is a level corresponding to a digital signal "1", and the second level is a level corresponding to a digital signal "0". In this way, when the control signal is the digital signal 1, the first line1 is on, whereas when the control signal is the digital signal 0, the first line1 is off.
The first output control module may be any suitable module that enables control of the output of the initial data signal. For example, the first output control module may include an inverter, a buffer.
Whether the initial data is output or not can be simply and conveniently controlled through the first output control module, and then the gating function of the first path is conveniently realized, and the hardware cost of the scheme is lower.
According to the embodiment of the invention, the first output control module comprises an inverter and a first buffer, wherein the input end of the inverter is used for receiving the control signal with the first level, and the output end of the inverter is used for outputting the inverted control signal with the second level; or the input end of the inverter is used for receiving the control signal with the second level, and the output end of the inverter is used for outputting the inverted control signal with the first level; the enable terminal of the first buffer is connected with the output terminal of the inverter, the data input terminal of the first buffer is used for receiving the initial data signal, and the output terminal of the first buffer is used for outputting the initial data signal under the control that the inverted control signal is at the second level or stopping outputting the initial data signal under the control that the inverted control signal is at the first level.
With continued reference to fig. 3, the first path line1 is shown to include an inverter U1 and a first buffer B1. The output signal of inverter U1 is inverted from the input signal. Therefore, the control signal Sctrl is input to the input terminal of the inverter, and the inverter can output the inverted control signal inverted thereto. That is, when the control signal Sctrl is at a high level, the inverted control signal is at a low level, and when the control signal Sctrl is at a low level, the inverted control signal is at a high level.
The inverter U1 outputs an inverted control signal to the enable terminal of the first buffer B1 while the data input terminal of the first buffer B1 receives the initial data signal Sdata. As shown in fig. 3, it can be understood that the first buffer B1 can output the initial data signal when the inverted control signal is low, whereas the first buffer B1 stops outputting the initial data signal when the inverted control signal is high.
The buffer has certain signal enhancement function, and in the application that the circuit is longer, can effectively strengthen the driving capability of GPIO port through the buffer to make GPIO signal's transmission more reliable and stable. According to the embodiment of the invention, a buffer with an enabling pin and an inverter are adopted for circuit construction, and the level conversion module is combined to realize the function of level variation of the GPIO port, so that the level switching circuit is suitable for being used as high-level peripherals with different levels.
According to an embodiment of the present invention, the second path includes a second output control module, wherein the second output control module is configured to receive the control signal and the initial data signal, output the initial data signal when the control signal is at the second level, and stop outputting the initial data signal when the control signal is at the first level.
The second path has the opposite signal transmission timing to the first path, that is, the first path outputs the initial data signal when the control signal is at the first level, and the second path outputs the initial data signal when the control signal is at the second level. As for the setting manner of the first level and the second level, the above description may be referred to, and the detailed description is omitted here.
The second output control module may be any suitable module that enables control of the output of the initial data signal. For example, the second output control module may include a buffer.
Whether the initial data is output or not can be simply and conveniently controlled through the second output control module, and then the gating function of the second channel is conveniently realized, and the hardware cost of the scheme is lower.
According to an embodiment of the present invention, the second output control module includes a second buffer, wherein an enable terminal of the second buffer is configured to receive a control signal at a first level or a second level, a data input terminal of the second buffer is configured to receive an initial data signal, and an output terminal of the second buffer is configured to output the initial data signal under the control of the control signal at the second level or stop outputting the initial data signal under the control of the control signal at the first level.
In the case where the first output control block includes an inverter, the second output control block may not include an inverter. However, this is only one example. For example, the second output control module may also include an inverter, in which case the first output control module may not include an inverter.
With continued reference to fig. 3, the second lane line2 is shown to include a second buffer B2. The enable terminal of the second buffer B2 may receive the control signal Sctrl while the data input terminal of the second buffer B2 receives the initial data signal Sdata. As shown in fig. 3, it can be understood that the second buffer B2 can output the initial data signal when the control signal is low, whereas the second buffer B2 stops outputting the initial data signal when the control signal is high.
As mentioned above, the buffer has a certain signal enhancement function, and in the application of longer line, the buffer can effectively enhance the driving capability of the GPIO port, so that the transmission of the GPIO signal is more stable and reliable.
According to another aspect of the present invention, an interposer is provided. The interposer may include the level switching circuit 100 described above.
Due to the adoption of the level switching circuit 100, the adapter board according to the embodiment of the invention can realize the level switching function through a very simple circuit, so that the problem of circuit service life reduction caused by a relay can be effectively solved.
According to the embodiment of the present invention, the level switching circuit may include two level switching circuits, wherein the first level switching circuit is used for realizing the switching of the initial data signal from the first voltage domain to the second voltage domain, and the second level switching circuit is used for realizing the switching of the initial data signal from the second voltage domain to the first voltage domain.
For example, on the patch panel, 6 pieces of level switching circuits may be provided, wherein 3 pieces may be from a 1.8V voltage domain to a 3.3V voltage domain, and the other 3 pieces may be from a 3.3V voltage domain to a 1.8V voltage domain. The first 3 level switching circuits may be used to transmit signals of the controller to the peripheral (for example, the connector mentioned above), and the last 3 level switching circuits may be used to transmit signals of the peripheral to the controller, that is, the signal transmission directions of the two level switching circuits may be opposite.
Of course, since the number of the required two GPIO ports is 3, the two level switching circuits each include 3 GPIO ports; in practical applications, the number of each level switching circuit may be set to any suitable number according to the required number of GPIO ports.
According to another aspect of the present invention, there is provided a signal generating apparatus comprising: the adapter plate comprises a signal generator and an adapter plate, wherein the adapter plate is used for being connected with the signal generator and a screen to be tested, and the signal generator can be connected with the screen to be tested through the adapter plate.
The connection relationship between the connector and the screen to be tested and the level switching circuit in the adapter board can be understood by referring to fig. 2 and 3, and the details are not described herein.
The signal generator may generate various signals required for a screen test, such as a power supply signal, a control signal, a gamma correction signal, and the like. Through the adapter plate, certain signals generated by the signal generator can be transmitted to the screen to be tested, and signals fed back by the screen to be tested are transmitted back to the signal generator. During signal transmission, the signal voltage domain can be switched by the level switching circuit when needed.
For example, when a screen to be tested is tested, a reset signal is often required to be input into the screen to be tested to control the overall reset of the screen to be tested. If the reset signal of the screen to be tested is required to be 3.3V level, the output signal of the GPIO port corresponding to the reset signal needs to be switched to 3.3V for matching. If the reset signal of the screen to be tested is 3.3V and the reset signal output by the connector is 1.8V, the screen to be tested can possibly recognize the 1.8V as a reset state, so that the reset work cannot be normally carried out. On the contrary, if the reset signal required by the screen to be tested is 1.8V and the reset signal output by the connector is 3.3V, the reset circuit of the screen to be tested is likely to be damaged by high level. Therefore, a simple and effective level switching circuit is needed to implement level switching before a signal is input into a screen to be tested. The level switching circuit 100 is applied to the signal generating equipment, and can effectively meet the level switching requirement between the screen to be tested and the PG signal generator.
According to the signal generating device of the embodiment of the invention, because the level switching circuit 100 is adopted, the signal generating device can also realize the level switching function through a very simple circuit, so that the problem of circuit service life reduction caused by a relay can be effectively solved.
According to the embodiment of the invention, the number of the adapter plates corresponds to the number of the screens to be tested in multiple types one by one, and each adapter plate is used for realizing data signal conversion of different voltage domains between the signal generator and the screen to be tested in the type corresponding to the signal generator.
Different types of screens to be tested may have different voltage domain conversion requirements, and therefore, a plurality of adapter plates may be provided, and different adapter plates are used for realizing the voltage domain conversion requirements of the different types of screens to be tested. Therefore, when a new screen to be tested needs to be tested each time, the adaptive level switching can be realized only by connecting the new screen to be tested with the corresponding adapter plate. The realization scheme ensures that the same signal generating equipment can be effectively adapted to various types of screens to be tested, and has wide application range and low hardware cost.
According to an embodiment of the present invention, the signal generator may include: a controller for outputting a first control signal and a first initial data signal; the screen to be tested is used for outputting a second control signal and a second initial data signal; the adapter plate is used for transmitting the first initial data signal or a first conversion data signal converted from the first initial data signal to the screen to be tested under the control of the first control signal; and/or transmitting the second initial data signal or a second converted data signal converted from the second initial data signal to the controller under the control of the second control signal.
The above description has described the embodiment of implementing level switching in two opposite directions between the controller and the screen to be tested, and the embodiment can be understood by referring to the above description, and is not described herein again.
Although the illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the foregoing illustrative embodiments are merely exemplary and are not intended to limit the scope of the invention thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention. All such changes and modifications are intended to be included within the scope of the present invention as set forth in the appended claims.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
The above description is only for the specific embodiment of the present invention or the description thereof, and the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the protection scope of the present invention. The protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A level switching circuit comprises a switching module and a level conversion module, wherein,
the switching module comprises two paths, wherein the output end of the first path is connected with the input end of the level conversion module; the node of the output end of the second path connected with the output end of the level conversion module is used as a GPIO port;
the switching module is used for receiving a control signal and an initial data signal, and outputs the initial data signal by conducting one of the two paths under the control of the control signal;
the level conversion module is used for converting the initial data signal output by the first path into a conversion data signal of a required voltage domain and outputting the conversion data signal from the corresponding GPIO port.
2. The level shifting circuit of claim 1, wherein the first path comprises a first output control block, wherein,
the first output control module is configured to receive the control signal and the initial data signal, output the initial data signal when the control signal is at a first level, and stop outputting the initial data signal when the control signal is at a second level.
3. The level switching circuit of claim 2, wherein the first output control block comprises an inverter and a first buffer, wherein,
the input end of the inverter is used for receiving the control signal with a first level, and the output end of the inverter is used for outputting an inverted control signal with a second level; or, the input end of the inverter is used for receiving the control signal with the second level, and the output end of the inverter is used for outputting the inverted control signal with the first level;
the enable terminal of the first buffer is connected with the output terminal of the inverter, the data input terminal of the first buffer is used for receiving the initial data signal, and the output terminal of the first buffer is used for outputting the initial data signal under the control that the phase-reversal control signal is at the second level or stopping outputting the initial data signal under the control that the phase-reversal control signal is at the first level.
4. The level shifting circuit of claim 1, wherein the second path comprises a second output control block, wherein,
the second output control module is configured to receive the control signal and the initial data signal, output the initial data signal when the control signal is at a second level, and stop outputting the initial data signal when the control signal is at a first level.
5. The level shifting circuit of claim 4, wherein the second output control block comprises a second buffer, wherein,
the enable terminal of the second buffer is configured to receive the control signal at a first level or a second level, the data input terminal of the second buffer is configured to receive the initial data signal, and the output terminal of the second buffer is configured to output the initial data signal under the control that the control signal is at the second level or stop outputting the initial data signal under the control that the control signal is at the first level.
6. An adapter board comprising a level switching circuit according to any one of claims 1 to 5.
7. The patch panel of claim 6, wherein the level switching circuit comprises two level switching circuits, wherein a first level switching circuit is used to switch the initial data signal from the first voltage domain to the second voltage domain, and a second level switching circuit is used to switch the initial data signal from the second voltage domain to the first voltage domain.
8. A signal generating device comprising: a signal generator and a patch panel, the patch panel being implemented using the patch panel of claim 6, wherein,
the adapter plate is provided with a connector used for connecting the signal generator and the screen to be tested, and the signal generator can be connected with the screen to be tested through the adapter plate.
9. The signal generating device as claimed in claim 8, wherein the number of the switch boards corresponds to a number of types of screens to be tested, and each of the switch boards is used for realizing data signal conversion between the signal generator and the corresponding type of screen to be tested in different voltage domains.
10. The signal generating apparatus of claim 8,
the signal generator includes: a controller for outputting a first control signal and a first initial data signal;
the screen to be tested is used for outputting a second control signal and a second initial data signal;
the adapter plate is used for transmitting the first initial data signal or a first conversion data signal converted from the first initial data signal to the screen to be tested under the control of the first control signal; and/or transmitting the second initial data signal or a second converted data signal converted from the second initial data signal to the controller under the control of the second control signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202111530107.3A CN114285400A (en) | 2021-12-10 | 2021-12-10 | Level switching circuit, adapter plate and signal generating equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111530107.3A CN114285400A (en) | 2021-12-10 | 2021-12-10 | Level switching circuit, adapter plate and signal generating equipment |
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| Publication Number | Publication Date |
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| CN114285400A true CN114285400A (en) | 2022-04-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202111530107.3A Pending CN114285400A (en) | 2021-12-10 | 2021-12-10 | Level switching circuit, adapter plate and signal generating equipment |
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| CN102419415A (en) * | 2011-08-31 | 2012-04-18 | 北京时代民芯科技有限公司 | TAP (Test Access Port) interface optimization circuit based on boundary scanning circuit |
| CN103916116A (en) * | 2013-01-05 | 2014-07-09 | 鸿富锦精密工业（深圳）有限公司 | Interface level switch device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1722032A (en) * | 2004-03-02 | 2006-01-18 | 索尼株式会社 | Portable photographing apparatus and power switching control method |
| CN101873032A (en) * | 2009-04-23 | 2010-10-27 | 深圳迈瑞生物医疗电子股份有限公司 | Power supply switching device and method thereof, power supply system and medical device |
| CN102419415A (en) * | 2011-08-31 | 2012-04-18 | 北京时代民芯科技有限公司 | TAP (Test Access Port) interface optimization circuit based on boundary scanning circuit |
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