CN110310590B - A control chip for LED display screen drive system - Google Patents
A control chip for LED display screen drive system Download PDFInfo
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- CN110310590B CN110310590B CN201910523013.XA CN201910523013A CN110310590B CN 110310590 B CN110310590 B CN 110310590B CN 201910523013 A CN201910523013 A CN 201910523013A CN 110310590 B CN110310590 B CN 110310590B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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Abstract
本发明实施例公开了一种LED显示屏驱动系统的控制芯片，属于LED驱动技术领域。控制芯片设有组合移位寄存器，该组合移位寄存器包括电平信号输入引脚、至少两个2‑bit移位寄存器、时钟信号输入引脚及数据输入引脚：该2‑bit移位寄存器设有DIR引脚、CLK引脚、DIN引脚及第一控制信号输出引脚和第二控制信号输出引脚，各2‑bit移位寄存器的DIR引脚并联并与该电平输入引脚接通，该电平信号输入引脚用于通过接收高电平或低电平信号控制该第一控制信号输出引脚和第二控制信号输出引脚输出的控制信号是否相同，从而实现控制芯片的工作模式的选择。采用本发明实施例，实现了一个控制芯片可以支持不同工作模式的目的。
The embodiment of the present invention discloses a control chip of an LED display screen driving system, belonging to the field of LED driving technology. The control chip is provided with a combined shift register, which includes a level signal input pin, at least two 2-bit shift registers, a clock signal input pin and a data input pin: the 2-bit shift register is provided with a DIR pin, a CLK pin, a DIN pin and a first control signal output pin and a second control signal output pin, and the DIR pins of each 2-bit shift register are connected in parallel and connected to the level input pin, and the level signal input pin is used to control whether the control signals output by the first control signal output pin and the second control signal output pin are the same by receiving a high level or a low level signal, thereby realizing the selection of the working mode of the control chip. By adopting the embodiment of the present invention, the purpose of a control chip supporting different working modes is achieved.
Description
Technical Field
The embodiment of the invention relates to the technical field of LED driving, in particular to a control chip of an LED display screen driving system.
Background
An LED (LIGHT EMITTING diode) is a new type of solid-state semiconductor light source, and is widely used in lighting circuits, backlight modules or display panels. The LED driving chip is a power supply adjusting electronic device for driving the LED to emit light or the LED module component to work normally. According to different application requirements, control chips with different versions of LED driving systems, such as a common 4-channel control chip and an 8-channel control chip, are required, and in the prior art, a control chip with a specific version can only support one working mode, such as a 4-channel mode or an 8-channel mode, so that the design cost and the production cost of the control chip are higher.
Disclosure of Invention
In view of the above, an object of the embodiments of the present invention is to provide a control chip of an LED display screen driving system, so as to solve the problem that a specific version of the control chip in the prior art can only support one working mode, so that the design cost and the production cost of the control chip of the LED display screen driving system are high.
The technical scheme adopted by the embodiment of the invention for solving the technical problems is as follows:
The control chip of the LED display screen driving system is provided with a combined shift register, and the combined shift register comprises a level signal input pin, at least two 2-bit shift registers, a clock signal input pin and a data input pin:
The 2-bit shift registers are provided with DIR pins, CLK pins, DIN pins, first control signal output pins and second control signal output pins, the DIR pins of each 2-bit shift register are connected in parallel and communicated with the level input pins, the CLK pins of each 2-bit shift register are connected in parallel and communicated with the clock signal input pins, and the DIN pins of each 2-bit shift register are connected in series and communicated with the data input pins;
The level signal input pin is used for controlling whether the control signals output by the first control signal output pin and the second control signal output pin are the same or not by receiving the high level signal or the low level signal, so that the selection of the working mode of the control chip is realized.
Preferably, the 2-bit shift register includes a first D flip-flop and a second D flip-flop, and each D flip-flop is provided with a D pin, a ck pin, a Q pin, and a set pin:
The set pin of the first D flip-flop 201 is connected in parallel with the set pin of the second D flip-flop 202 and then connected with the DIR pin of the 2-bit shift register;
The ck pin of the first D flip-flop 201 is connected in parallel with the ck pin of the second D flip-flop 202 and then connected with the CLK pin of the 2-bit shift register;
the D pin of the first D trigger 201 is connected with the DIN pin of the 2-bit shift register;
the Q pin of the first D flip-flop 201 is connected to the D pin of the second D flip-flop 202 and the first control signal output pin of the 2-bit shift register, respectively;
The Q pin of the second D flip-flop 202 is connected to the second control signal output pin and the data output pin of the 2-bit shift register, respectively.
Preferably, the combined shift register is provided with four 2-bit shift registers.
Preferably, the level signal input pin receives a high level signal, the first control signal output pin and the second control signal output pin of each 2-bit shift register are different, and the working mode of the control chip is an 8-channel working mode.
5. The control chip of the LED display driving system according to claim 4, wherein the level signal input pin receives a high level signal by turning on a power supply voltage.
Preferably, the level signal input pin receives a low level signal, the first control signal output pin and the second control signal output pin of each 2-bit shift register output control signals the same, and the working mode of the control chip is a 4-channel working mode.
Preferably, the level signal input pin receives a low level signal through ground.
Preferably, the control chip further comprises a buffer, a multi-path timing generation and control unit and a gate control unit:
the shift register is communicated with the buffer and the multi-path time sequence generation and control unit through bit lines;
The multi-path time sequence generation and control unit is communicated with the gate control unit through a bit line;
the multi-path time sequence generating and controlling unit is provided with a chip selection function multiplexing pin which is used for receiving high-level or low-level signals so as to select the working mode of the control chip.
Preferably, the LED display driving circuit is further provided with a protection circuit, and the protection circuit is respectively connected with the buffer, the multi-path timing sequence generating and controlling unit and the gate control unit.
The control chip of the LED display screen driving system is provided with the combined shift register capable of supporting channel selection, the shift register is provided with a level signal input pin, at least two 2-bit shift registers, a clock signal input pin and a data input pin, the level signal received by the level signal input pin and the clock signal received by the clock signal input pin are input into each 2-bit shift register in parallel, the data signal received by the data input pin is input into each 2-bit shift register in series, the first control signal output pin and the second control signal output pin of each 2-bit shift register output control signals in parallel according to the level signal, the clock signal and the data signal received by each 2-bit shift register, when the level signal input pin receives a high level signal, the control signals output by the first control signal output pin and the second control signal output pin are different, and when the level signal is received, the control signals output by the first control signal output pin and the second control signal output pin are the same, so that the control chip can support different working modes and the production cost is reduced.
Drawings
Fig. 1 is a schematic block diagram of a control chip of an LED display driving system according to a first embodiment of the present invention;
FIG. 2 is a schematic block diagram of the combined shift register of FIG. 1;
FIG. 3 is a schematic block diagram of the 2-bit shift register of FIG. 2.
The achievement of the objects, functional features and advantages of the embodiments of the present invention will be further described with reference to the drawings in conjunction with the embodiments.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved by the embodiments of the present invention more clear and obvious, the embodiments of the present invention are further described in detail below with reference to the accompanying drawings and the embodiments. It should be understood that the detailed description and specific examples, while indicating the embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 1, the control chip includes a combination shift register 101, a buffer 102, a multi-path timing generation and control unit 103, a gate control unit 104 and a protection circuit 105.
The combined shift register 101 includes a level signal input pin, at least two 2-bit shift registers, a clock signal input pin, and a data input pin:
The 2-bit shift registers are provided with DIR pins, CLK pins, DIN pins, first control signal output pins and second control signal output pins, the DIR pins of each 2-bit shift register are connected in parallel and communicated with the level input pins, the CLK pins of each 2-bit shift register are connected in parallel and communicated with the clock signal input pins, and the DIN pins of each 2-bit shift register are connected in series and communicated with the data input pins;
The level signal input pin is used for controlling whether the control signals output by the first control signal output pin and the second control signal output pin are the same or not by receiving the high level signal or the low level signal, so that the selection of the working mode of the control chip is realized.
In practical application, the data transmission of each 2-bit shift register is realized by receiving the CLOCK signal from the CLOCK signal input pin and then transmitting the CLOCK signal to each 2-bit shift register in parallel, and when a CLOCK signal (CLK) with a certain frequency is sequentially input, the data is sequentially sent into the register from the DIN pin.
Referring to fig. 2, a possible scheme of combining shift registers is shown in this embodiment. The combined shift register 200 in the described scheme comprises 4 2-bit shift registers. Every 2-bit shift register all is equipped with DIR pin, CLK pin, DIN pin and first control signal output pin CTRL0 and second control signal output pin CTRL1, wherein:
the DIR pins of the 2-bit shift register 201, the 2-bit shift register 202, the 2-bit shift register 203 and the 2-bit shift register 204 are connected with the level signal input pins, so that parallel input of level signals is realized;
CLK pins of the 2-bit shift register 201, the 2-bit shift register 202, the 2-bit shift register 203 and the 2-bit shift register 204 are connected with clock signal input pins, so that parallel input of clock signals is realized;
the DIN pins of the 2-bit shift register 201, the 2-bit shift register 202, the 2-bit shift register 203 and the 2-bit shift register 204 are connected in series and communicated with the data input pins, so that serial input of data is realized.
The DIN pins of the 2-bit shift register 201, the 2-bit shift register 202, the 2-bit shift register 203 and the 2-bit shift register 204 are connected in series and are connected with the data input pins, which means that:
The DIN pin of the 2-bit shift register 201 is connected with the on-data input pin of the shift register 200, the data output pin is connected with the DIN pin of the 2-bit shift register 202, the data output pin of the 2-bit shift register 202 is connected with the DIN pin of the 2-bit shift register 203, and the data output pin of the 2-bit shift register 203 is connected with the DIN pin of the 2-bit shift register 204.
Please refer to fig. 3, which is a schematic diagram illustrating a block structure of each of the 2-bit shift registers in fig. 2.
The 2-bit shift register 300 includes a first D flip-flop 301 and a second D flip-flop 302, each of which is provided with a D pin, a ck pin, a Q pin, and a set pin:
The set pin of the first D flip-flop 301 is connected in parallel with the set pin of the second D flip-flop 302 and then connected with the DIR pin of the 2-bit shift register;
the ck pin of the first D flip-flop 301 is connected in parallel with the ck pin of the second D flip-flop 302 and then connected with the CLK pin of the 2-bit shift register;
The D pin of the first D trigger 301 is connected with the DIN pin of the 2-bit shift register;
The Q pin of the first D flip-flop 301 is connected to the D pin of the second D flip-flop 302 and the first control signal output pin of the 2-bit shift register, respectively;
The Q pin of the second D flip-flop 302 is connected to the second control signal output pin and the data output pin of the 2-bit shift register, respectively.
Thus, when the D pin of the first flip-flop 301 receives the high level signal, the control signal CTRL0 output by the Q pin of the first flip-flop 301 is different from the control signal CTRL1 output by the Q pin of the second flip-flop 302, that is, the control signals output by the first control signal output pin and the second control signal output pin of the 2-bit shift register are different.
When the D pin of the first flip-flop 301 receives the low level signal, the control signal CTRL0 output by the Q pin of the first flip-flop 301 is the same as the control signal CTRL1 output by the Q pin of the second flip-flop 302, i.e. the control signals output by the first control signal output pin and the second control signal output pin of the 2-bit shift register are the same.
Taking the combined shift register of fig. 2 as an example, 4 2-bit shift registers are provided, when the level signal input pins of the combined shift register receive high level signals, the first control signal output pins and the second control signal output pins of the 2-bit shift registers output different control signals, the control chip working mode is an 8-channel working mode, when the level signal input pins of the combined shift register receive low level signals, the first control signal output pins and the second control signal output pins of the 2-bit shift registers output the same control signals, and the control chip working mode is a 4-channel working mode.
In practical application, the level signal input pin of the control chip can receive a high level signal by switching on the power supply voltage and receive a low level signal by grounding.
With continued reference to fig. 1, the combined shift register 101 is connected to the buffer 102 and the multi-path timing generation and control unit 103 through a bit line;
the multi-path time sequence generation and control unit 103 is communicated with the gate control unit 104 through a bit line;
the multi-path time sequence generating and controlling unit 103 is provided with a chip selection function multiplexing pin which is used for receiving a high-level or low-level signal so as to select the working mode of the driving circuit;
The protection circuit 105 is connected to the buffer 102, the multi-path timing generation and control unit 103, and the gate control unit 102, respectively.
The protection circuit 105 of the present embodiment may include:
the abnormality detection subcircuit is used for short-circuit protection of output channel voltage and chip over-temperature protection;
The output channel voltage short-circuit protection sub-circuit is used for detecting the voltage of an output channel (OUT 0-OUT 7) in real time, when the voltage is lower than 0.1V, the channel is considered to enter a short-circuit state, the channel is immediately turned off and locked, and the release can be realized only by restarting a power supply;
And the chip over-temperature protection sub-circuit is used for triggering the over-temperature protection module to output a high level (kept as a low level in normal operation) when the temperature of the chip exceeds 135 ℃ and turning off an output channel so as to reduce the temperature. When the temperature drops to 115 ℃, the output channel is restarted;
The delay protection subcircuit is used for realizing a delay protection mechanism and has the function of shielding instant voltage overshoots of 8 paths (or 4 paths) of output channels when the output channels are turned on and turned off so as to prevent the protection circuit from misjudging. Delay decisions of about 50nm are typically achieved with cascaded directors. That is, the state detected by the protection module is considered as an active state after the output channel is turned on or off by 50 nm.
In this embodiment, the abnormality detection sub-circuit and the delay protection sub-circuit are combined, and output an enable signal after internal logic operation, which is used to control both the output channel and the cascade signal (DOUT).
The specific circuit of the protection circuit 105 in this embodiment may be related to according to actual needs, or an existing protection circuit may be adopted, which is not described herein.
With continued reference to fig. 1, the main pins of the control chip are described as follows:
DIN receives external input data and is connected with a data input pin of the combined shift register 101, BK is an enabling end, high level is effective, low level is used for cutting off an output channel, CLK pin receives an external clock signal and a clock signal input pin of the combined shift register 101 to realize shift number sending and time sequence generation, and DIR pin is a mode selection (chip selection) pin and is connected with a level signal input pin of the combined shift register 101 and used for selecting an 8-channel or 4-channel output mode.
The control chip of the embodiment is provided with a combined shift register capable of supporting channel selection, the shift register is provided with a level signal input pin, at least two 2-bit shift registers, a clock signal input pin and a data input pin, the level signal received by the level signal input pin and the clock signal received by the clock signal input pin are input into each 2-bit shift register in parallel, the data signal received by the data input pin is input into each 2-bit shift register in series, a first control signal output pin and a second control signal output pin of each 2-bit shift register output control signals in parallel according to the level signal, the clock signal and the data signal received by each 2-bit shift register, when the level signal input pin receives a high level signal, the control signals output by the first control signal output pin and the second control signal output pin are different, and when the level signal is received, the control signals output by the first control signal output pin and the second control signal output pin are the same, so that the purpose of supporting different working modes of the control chip is realized, and the design cost and the production cost are reduced.
The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, and are not thereby limiting the scope of the claims of the embodiments of the present invention. Any modifications, equivalent substitutions and improvements made by those skilled in the art without departing from the scope and spirit of the embodiments of the present invention shall fall within the scope of the claims of the embodiments of the present invention.
Claims (5)
1. The control chip of the LED display screen driving system is characterized in that the control chip is provided with a combined shift register, the combined shift register comprises a level signal input pin, four 2-bit shift registers, a clock signal input pin and a data input pin, wherein the 2-bit shift register is provided with a DIR pin, a CLK pin, a DIN pin, a first control signal output pin and a second control signal output pin, the DIR pin of each 2-bit shift register is connected in parallel and communicated with the level input pin, the CLK pin of each 2-bit shift register is connected in parallel and communicated with the clock signal input pin, the DIN pin of each 2-bit shift register is connected in series and communicated with the data input pin, and the level signal input pin is used for controlling the control signals output by the first control signal output pin and the second control signal output pin to be the same or different through receiving high-level or low-level signals, so that the working mode of the control chip is selected;
The control chip comprises a DIN pin, a CLK pin and a DIR pin, wherein the DIN pin is connected with a data input pin of the combined shift register, the CLK pin is connected with a clock signal input pin of the combined shift register, and the DIR pin is connected with a level signal input pin of the combined shift register;
The level signal input pin is used for controlling the control signals output by the first control signal output pin and the second control signal output pin to be the same or different by receiving high level or low level signals, so that the selection of the working mode of the control chip is realized, and the level signal input pin comprises:
The level signal input pins receive high level signals, the first control signal output pins and the second control signal output pins of the 2-bit shift registers are different in output control signals, and the working mode of the control chip is an 8-channel working mode, or
The level signal input pins receive low level signals, the first control signal output pins and the second control signal output pins of the 2-bit shift registers output control signals which are identical, and the working mode of the control chip is a 4-channel working mode.
2. The control chip of the LED display screen driving system according to claim 1, wherein the 2-bit shift register comprises a first D trigger and a second D trigger, each D trigger is provided with a D pin, a ck pin, a Q pin and a set pin, the set pin of the first D trigger is connected with the DIR pin of the 2-bit shift register after being connected in parallel with the set pin of the second D trigger, the ck pin of the first D trigger is connected with the CLK pin of the 2-bit shift register after being connected in parallel with the ck pin of the second D trigger, the D pin of the first D trigger is connected with the DIN pin of the 2-bit shift register, the Q pin of the first D trigger is connected with the D pin of the second D trigger and the first control signal output pin of the 2-bit shift register respectively, and the Q pin of the second D trigger is connected with the second control signal output pin of the 2-bit shift register and the data output respectively.
3. The control chip of the LED display driving system according to claim 1, wherein the level signal input pin receives a high level signal by turning on a power supply voltage.
4. The control chip of the LED display driving system according to claim 1, wherein the level signal input pin receives a low level signal through a ground.
5. The control chip of the LED display screen driving system according to claim 1, wherein the control chip further comprises a buffer, a multi-path time sequence generating and controlling unit, a grid controlling unit and a protection circuit, wherein the combined shift register is respectively communicated with the buffer and the multi-path time sequence generating and controlling unit, the multi-path time sequence generating and controlling unit is communicated with the grid controlling unit, and the protection circuit is respectively connected with the buffer, the multi-path time sequence generating and controlling unit and the grid controlling unit.
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| CN112666444B (en) * | 2020-12-03 | 2024-06-04 | 思瑞浦微电子科技（苏州）股份有限公司 | Chip FT test method and system |
| CN113539343B (en) * | 2021-07-28 | 2022-04-26 | 北京微纳星空科技有限公司 | Multi-path output method, device and equipment of shift register and storage medium |
| CN114974106B (en) * | 2022-08-02 | 2022-10-18 | 深圳英集芯科技股份有限公司 | LED display device, LED display method and electronic equipment |
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| CN201868079U (en) * | 2010-09-19 | 2011-06-15 | 无锡力芯微电子股份有限公司 | LED drive circuit and output circuit therein |
| CN102622978A (en) * | 2012-02-15 | 2012-08-01 | 深圳市华星光电技术有限公司 | Method for implementing liquid crystal display with two operation modes |
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| CN105390106B (en) * | 2015-12-07 | 2018-12-21 | 深圳市华星光电技术有限公司 | The level shifting circuit and level conversion method of liquid crystal display panel of thin film transistor |
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