CN105390106B - The level shifting circuit and level conversion method of liquid crystal display panel of thin film transistor - Google Patents
The level shifting circuit and level conversion method of liquid crystal display panel of thin film transistor Download PDFInfo
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- CN105390106B CN105390106B CN201510893677.7A CN201510893677A CN105390106B CN 105390106 B CN105390106 B CN 105390106B CN 201510893677 A CN201510893677 A CN 201510893677A CN 105390106 B CN105390106 B CN 105390106B
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Abstract
The invention discloses a kind of level shifting circuits of liquid crystal display panel of thin film transistor, including sequence controller and the level translator being electrically connected with the sequence controller.The sequence controller includes the first pin, and the sequence controller sends control signal to the level translator by first pin.The level translator includes the second pin being electrically connected with first pin, the level translator receives the control signal by the second pin, and the control signal is handled, output can drive n driving signal of liquid crystal display panel of thin film transistor, and n is the positive integer more than or equal to 1.The invention also discloses a kind of level conversion methods of liquid crystal display panel of thin film transistor.Level shifting circuit and level conversion method of the invention, can reduce the number of pins between sequence controller and level translator, and then simplify circuit structure, reduce costs.
Description
Technical field
The present invention relates to technical field of liquid crystal display more particularly to a kind of level of liquid crystal display panel of thin film transistor to turn
Change circuit and a kind of level conversion method.
Background technique
TFT (Thin Film Transistor, thin film transistor (TFT)) liquid crystal display includes TFT LCD panel, with
And the driving circuit for driving TFT LCD panel.Driving circuit includes the grid for driving TFT LCD panel
The data driver of the gate drivers of line, data line for driving TFT LCD panel, and for controlling gate driving
The sequence controller of the driver' s timing of device and data driver.
A kind of TFT LCD panel is using GOA (Gate Drive OnArray, the driving of array substrate row) framework.I.e.
Gate drivers are incorporated on thin-film transistor array base-plate, to realize the progressive scan to liquid crystal display panel.Using GOA
Framework needs to increase electrical level transferring chip on circuit drives plate to carry out the level conversion of signal, to drive liquid crystal display panel
In TFT work.The existing level shifting circuit for GOA framework liquid crystal display panel generally includes: one is set to electricity
Sequence controller in the driving plate of road, the sequence controller is for generating and sending control signal；One is set to circuit drives plate
On electrical level transferring chip, the electrical level transferring chip be used for convert by sequence controller send control signal level.Through
Control signal after level conversion is input to gate drivers, and gate drivers are in GOA framework liquid crystal display panel later
TFT is driven.However, needing multiple controls to enable the TFT in GOA framework liquid crystal display panel normally to open line by line
Signal processed is just able to achieve the display effect of progressive scan；And wherein each control signal is required through sequence controller and level
The corresponding pin of conversion chip carries out communications.Therefore, this number of pins that will increase sequence controller and electrical level transferring chip
Mesh makes the structure of level shifting circuit become complicated, leads to increased costs.
Summary of the invention
In view of this, the present invention provides a kind of level shifting circuits of liquid crystal display panel of thin film transistor and level to turn
Method is changed, the number of pins between sequence controller and level translator can be reduced.
A kind of level shifting circuit of liquid crystal display panel of thin film transistor, including sequence controller and with the timing control
The level translator of device electrical connection processed, the sequence controller include the first pin, and the sequence controller passes through described first
Pin sends control signal to the level translator, and first control signal of the control signal within a signal period is high
Level duration or first control signal the low level duration are T1, and the second control signal within a signal period is high
Level duration or second control signal the low level duration are T2, and the third control signal within a signal period is high
Level duration or third control signal the low level duration are T3；The level translator includes and first pin
The second pin of electrical connection, the level translator receive the control that the sequence controller is sent by the second pin
Signal processed, and n driving signal is generated according to the control signal, i-th of driving signal in the n driving signals is one
Driving signal high level lasting time in a signal period is equal to the T1, the low electricity of driving signal within a signal period
The flat duration is equal to the T2, or driving signal high level lasting time within a signal period be equal to the T2,
Driving signal the low level duration within a signal period is equal to the T1, the high level of i-th of driving signal
For the conducting voltage of the thin film transistor (TFT), the low level of i-th of driving signal is the cut-off electricity of the thin film transistor (TFT)
Pressure is divided into (i- between the rising edge initial time of i-th of driving signal and the rising edge initial time of the control signal
1) * T3, wherein n is the positive integer more than or equal to 1, i=1,2 ... n.
Wherein, the level translator includes logical transition circuit, and the logical transition circuit passes through the second pin
It receives the control signal that the sequence controller is sent and decodes described T1, T2 and T3 in the control signal；Root
The first indication signal of the information comprising described T1, T2 and T3 is generated according to described T1, T2 and T3.
Wherein, the level translator further includes logic control circuit, the logic control circuit and the logical transition
Circuit is electrically connected, and the logic control circuit receives first indication signal that the logical transition circuit is sent, and root
N the second indication signals are generated according to the information of described T1, T2 and T3 in first indication signal.
Wherein, second finger of i-th of second indication signals in n second indication signals within a signal period
Show that signal high level lasting time is equal to the T1, second indication signal the low level duration within a signal period etc.
The second indication signal high level lasting time in the T2, or within a signal period is equal to the T2, believes at one
The second indication signal the low level duration in number period is equal to the T1, the high level of i-th of second indication signals
Absolute value is less than the absolute value of the conducting voltage of the thin film transistor (TFT), and the low level of i-th of second indication signals is absolute
Value is less than the absolute value of the blanking voltage of the thin film transistor (TFT), the rising edge initial time of i-th of second indication signals
(i-1) * T3 is divided between the rising edge initial time of the control signal.
Wherein, the level translator further includes signal amplification circuit, the signal amplification circuit and the logic control
Circuit is electrically connected, and the signal amplification circuit receives n second indication signals that the logic control circuit is sent, and
N second indication signals are amplified, the n driving signals are generated.
A kind of level conversion method of liquid crystal display panel of thin film transistor, comprising: sequence controller passes through the timing
The first pin on controller sends control signal to level translator, the control signal within a signal period first
Controlling signal high level lasting time or first control signal the low level duration is T1, second within a signal period
It controls signal high level lasting time or second control signal the low level duration is T2, the third within a signal period
Controlling signal high level lasting time or third control signal the low level duration is T3；The level translator passes through described
Second pin on level translator receives the control signal that the sequence controller is sent, and according to the control signal
N driving signal is generated, driving signal of i-th of driving signal within a signal period in the n driving signals is high
Level duration is equal to the T1, the driving signal the low level duration within a signal period is equal to the T2, or
Person is equal to the T2, the driving letter within a signal period in the driving signal high level lasting time in a signal period
Number the low level duration is equal to the T1, and the high level of i-th of driving signal is the electric conduction of the thin film transistor (TFT)
Pressure, the low level of i-th of driving signal are the blanking voltage of the thin film transistor (TFT), i-th of driving signal it is upper
It rises and is divided into (i-1) * T3 between initial time and the rising edge initial time of the control signal, wherein n is more than or equal to 1
Positive integer, i=1,2 ... n.
Wherein, the level translator generates the n driving signals according to the control signal, comprising: the level
Converter decodes described T1, T2 and T3 in the control signal；The level translator is generated according to described T1, T2 and T3
First indication signal of the information comprising described T1, T2 and T3；The level translator generates n according to first indication signal
A driving signal.
Wherein, the level translator generates the n driving signals according to first indication signal, comprising: described
Level translator generates n the second indication signals according to the information of described T1, T2 and T3 in first indication signal；It is described
Level translator generates the n driving signals according to n second indication signals.
Wherein, second finger of i-th of second indication signals in n second indication signals within a signal period
Show that signal high level lasting time is equal to the T1, second indication signal the low level duration within a signal period etc.
The second indication signal high level lasting time in the T2, or within a signal period is equal to the T2, believes at one
The second indication signal the low level duration in number period is equal to the T1, the high level of i-th of second indication signals
Absolute value is less than the absolute value of the conducting voltage of the thin film transistor (TFT), and the low level of i-th of second indication signals is absolute
Value is less than the absolute value of the blanking voltage of the thin film transistor (TFT), the rising edge initial time of i-th of second indication signals
(i-1) * T3 is divided between the rising edge initial time of the control signal.
Wherein, the level translator generates the n driving signals according to n second indication signals, comprising: institute
It states level translator and receives n second indication signals；The level translator puts n second indication signals
Greatly, the n driving signals are generated.
Detailed description of the invention
In order to illustrate more clearly of technical solution of the present invention, attached drawing needed in embodiment will be made below
Simply introduce, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, general for this field
For logical technical staff, without creative efforts, other attached drawings can also be obtained such as these attached drawings.
Fig. 1 is the schematic diagram of the level shifting circuit of liquid crystal display panel of thin film transistor provided in an embodiment of the present invention.
Fig. 2 is a kind of timing diagram of embodiment of level shifting circuit shown in FIG. 1.
Fig. 3 is the timing diagram of the another embodiment of level shifting circuit shown in FIG. 1.
Fig. 4 is the circuit module schematic diagram of level translator shown in FIG. 1.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
For ease of description, may be used herein such as " ... under ", " ... below ", "lower", " ... on ", "upper"
Spaces relative terms are waited to describe the relationship of an elements or features and another (a little) elements or features as illustrated in the drawing.
It is appreciated that be referred to as in another element or layer "upper", " being connected to " or " being couple to " another element when an element or layer or
When layer, it can directly on another element or layer, be directly connected to or be couple to another element or layer, or there may be occupy
Between element or layer.
It is appreciated that terminology used here is merely to description specific embodiment, is not intended to limit the present invention.Herein
In use, clearly stating unless the context otherwise, otherwise singular " one " and "the" are also intended to including plural form.Further
Ground, when used in this manual, term " includes " and/or "comprising" show the feature, entirety, step, element and/or
The presence of component, but the presence that is not excluded for other one or more features, entirety, step, element, component and/or combination thereof or
Increase.Specification subsequent descriptions are to implement better embodiment of the invention, and so the description is of the invention general to illustrate
For the purpose of principle, the range that is not intended to limit the invention.Protection scope of the present invention is when view appended claims institute defender
Subject to.
As shown in Figure 1, the level shifting circuit 200 of the embodiment of the present invention include sequence controller 210 and with the timing control
The level translator 220 that device 210 processed is electrically connected.
Sequence controller 210 includes the first pin 212, and sequence controller 210 is turned by first pin 212 to level
Parallel operation 220 sends control signal CK1.Level translator 220 includes the second pin 226 being electrically connected with first pin 212,
Level translator 220 receives control signal CK1 by the second pin 226, and carries out level conversion to control signal CK1,
It generates and exports the n driving signal CKV1~CKVn that can drive TFT LCD panel, wherein n is more than or equal to 1
Positive integer.In the present embodiment, n is equal to 4.It is understood that present invention is naturally not limited to this, for example, n can be with
For 5,6,7,8 or other numerical value.
Therefore, the level shifting circuit in the embodiment of the present invention, the sequence controller and the level translator are distinguished
Be provided with first pin and a second pin, first pin and second pin electrical connection, by it is described when
Sequence controller sends a control signal to the level translator, can control the level translator and generate multiple driving letters
Number, to reduce the number of pins between sequence controller and level translator, circuit structure is thereby simplified, is reduced into
This.
As shown in Fig. 2, in a kind of embodiment of the embodiment of the present invention, specifically, the sequence controller 210 is sent
First control signal high level lasting time of the control signal CK1 within a signal period be T1, control signal CK1 one
Second control signal high level lasting time in a signal period is T2, controls the of signal CK1 within a signal period
Three control signal high level lasting times are T3.For the drive circuit structure and/or TFT of specific TFT LCD panel
The specific value of the resolution of liquid crystal display panel, described T1, T2 and T3 can be accordingly arranged, and in T1, T2 and T3
Any one can be zero.
The level translator 220 handles received control signal CK1, generates one group of driving signal, for example, raw
At 4 driving signal CKV1~CKV4.Wherein, the high electricity of driving signal of i-th of driving signal CKVi within a signal period
The flat duration is equal to the T1, and driving signal low level of i-th of driving signal CKVi within a signal period is held
The continuous time is equal to the T2.The conducting voltage VGH that the high level of i-th of driving signal CKVi is TFT, i-th of drive
The blanking voltage VGL that the low level of dynamic signal CKVi is TFT.The rising edge initial time of i-th of driving signal CKVi with
(i-1) * T3, i=1,2 ... n is divided between the rising edge initial time of the control signal CK1.Specifically, for example, working as i=1
When, driving signal high level lasting time of the 1st driving signal CKV1 within a signal period is equal to the T1, and described the
Driving signal the low level duration of 1 driving signal CKV1 within a signal period is equal to the T2.1st drive
The cut-off that the low level of conducting voltage VGH, the 1st driving signal CKV1 that the high level of dynamic signal CKV1 is TFT are TFT
Voltage VGL.When the rising edge of the rising edge initial time of the 1st driving signal CKV1 and the control signal CK1 originate
Between between be divided into 0.Level translator 220 can generate 4 according to signal parameter T1, T2 and T3 in control signal CK1 as a result,
Driving signal CKV1~CKV4.
As shown in figure 3, in the another embodiment of the embodiment of the present invention, different from the embodiment described above, institute
State first control signal the low level duration of the control signal CK1 of the transmission of sequence controller 210 within a signal period
For T1, controlling second control signal the low level duration of the signal CK1 within a signal period is T2, controls signal CK1
Third control signal the low level duration within a signal period is T3.Likewise, being directed to specific TFT liquid crystal display
The specific value of the drive circuit structure of panel and/or the resolution of TFT LCD panel, T1, T2 and T3 can carry out phase
It should be arranged, and any one of T1, T2 and T3 can be zero.
It in the present embodiment, as shown in Figures 2 and 3, is simultaneously control signal CK1 with T1, T2 and T3 in a signal
High level lasting time in period is simultaneously control signal CK1 for the low level duration in a signal period
Illustrated, but actually the present invention is not limited thereto.For example, T1 can also be control signal CK1 within a signal period
High level lasting time, T2 can also be that the low level duration of the control signal CK1 within a signal period, T3 may be used also
To be the high level lasting time for controlling signal CK1 within a signal period；Alternatively, T1 can also be that control signal CK1 exists
High level lasting time, T2 in one signal period can also be low level of the control signal CK1 within a signal period
Duration, T3 can also be the low level duration of the control signal CK1 within a signal period；Alternatively, T1 can be with
Be control the low level duration of the signal CK1 within a signal period, T2 can also be control signal CK1 in a signal
High level lasting time, T3 in period can also be high level lasting time of the control signal CK1 within a signal period；
Alternatively, T1 can also be that the low level duration controlled signal CK1 within a signal period, T2 can also be control signal
CK1 can also be that control signal CK1 is low within a signal period in high level lasting time, the T3 in a signal period
Level duration.
In the present embodiment, as shown in Figures 2 and 3, with i-th of driving signal CKVi within a signal period
High level lasting time be T1, the low level duration T2, i-th of driving signal CKVi and i+1 driving signal
Initial time delay between CKVi+1 is illustrated for being T3, but present invention is naturally not limited to this.For example, described
High level lasting time of the i driving signal CKVi within a signal period can also may be used also for T2, the low level duration
Think that the initial time delay between T1, i-th of driving signal CKVi and i+1 driving signal CKVi+1 is T3；Alternatively, institute
Stating high level lasting time of i-th of driving signal CKVi within a signal period can also be T2, the low level duration
Can also be between T3, i-th of driving signal CKVi and i+1 driving signal CKVi+1 initial time delay be T1；Or
Person, high level lasting time of i-th of driving signal CKVi within a signal period can also be lasting for T1, low level
Time can also be that the initial time delay between T3, i-th of driving signal CKVi and i+1 driving signal CKVi+1 is
T2；Alternatively, high level lasting time of i-th of driving signal CKVi within a signal period can also be T3, low electricity
The flat duration can also the initial time between T2, i-th of driving signal CKVi and i+1 driving signal CKVi+1 prolong
It is late T1；Alternatively, high level lasting time of i-th of driving signal CKVi within a signal period can also for T3,
The low level duration can also starting between T1, i-th of driving signal CKVi and i+1 driving signal CKVi+1 when
Between delay be T2.Specifically, for example, high level of the 1st driving signal CKV1 within a signal period continues as i=1
Time can also be T2, and the low level duration can also be T1, the 1st driving signal CKV1 and the 2nd driving signal CKV2
Between initial time delay be T3.
Referring to Figure 4 together, in embodiments of the present invention, level translator 220 includes:
Logical transition circuit 221, for receiving timing control by the second pin 226 on level translator 220
The control signal CK1 that device 210 is sent decodes described T1, T2 and T3 in the CK1, and is generated according to described T1, T2 and T3
First indication signal of the information comprising described T1, T2 and T3 simultaneously sends first indication signal；
Logic control circuit 222 is electrically connected with the logical transition circuit 211, for receiving the logical transition electricity
First indication signal that road 221 is sent generates one according to the information of described T1, T2 and T3 in first indication signal
Group the second indication signal, such as 4 second indication signal 0-CKV1~0-CKV4, and send the second indication signal 0-CKV1~
0-CKV4.Wherein, the signal parameter of the second indication signal 0-CKV1~0-CKV4 is set according to described T1, T2 and T3
It sets.In the present embodiment, logic control circuit 222 generates 4 the second indication signals, but present invention is naturally not limited to this.
In the present invention, the number for second indication signal that logic control circuit 222 generates is equal to the number of the driving signal,
It is all n, n is the positive integer more than or equal to 1.
Specifically, when second indication signal is n, for example, 4, wherein i-th of second indication signal 0-
Second indication signal high level lasting time of the CKVi within a signal period is equal to the T1, i-th second instructions
Second indication signal the low level duration of the signal 0-CKVi within a signal period is equal to the T2；Alternatively, described i-th
Second indication signal high level lasting time of a second indication signal 0-CKVi within a signal period is equal to the T2, institute
Second indication signal the low level duration of i-th of second indication signal 0-CKVi within a signal period is stated equal to described
T1.The high level absolute value of i-th of second indication signal 0-CKVi is less than the exhausted of the conducting voltage of the thin film transistor (TFT)
To value, the low level absolute value of i-th of second indication signal 0-CKVi is less than the blanking voltage of the thin film transistor (TFT)
The rising edge of absolute value, the rising edge initial time of i-th of second indication signal 0-CKVi and the control signal CK1 rise
Beginning time interval is (i-1) * T3, i=1,2 ... n.Specifically, for example, the 1st the second indication signal 0-CKV1 is in a signal
The second indication signal high level lasting time in period is equal to the T1, and the 1st second indication signal 0-CKV1 is one
The second indication signal the low level duration in a signal period is equal to the T2.The 1st second indication signal 0-
The high level absolute value of CKV1 is less than the absolute value of the conducting voltage of the thin film transistor (TFT), the 1st second indication signal
The low level absolute value of 0-CKV1 is less than the absolute value of the blanking voltage of the thin film transistor (TFT).The 1st second instruction letter
0 is divided between the rising edge initial time of number 0-CKV1 and the rising edge initial time of the control signal CK1.At this point, 0-CKV1
This second indication signal of group of~0-CKV4 can not be directly used in the TFT in driving liquid crystal display panel.
Signal amplification circuit 223 is electrically connected with the logic control circuit 222, for receiving the logic control electricity
Road 222 send 4 second indication signal 0-CKV1~0-CKV4, and to 4 second indication signal 0-CKV1~
Each indication signal in 0-CKV4 carries out signal amplification and generates driving signal CKV1~CKV4 with corresponding.Wherein, the driving
The high level of each driving signal in signal CKV1~CKV4 is the conducting voltage VGH of thin film transistor (TFT), low level is film
The blanking voltage VGL of transistor.At the control signal that level translator 220 can send sequence controller 210 as a result,
Reason generates the driving signal that can drive the TFT in liquid crystal display panel.
Above in conjunction with Fig. 1 to Fig. 4, the electricity of the liquid crystal display panel of thin film transistor of the embodiment of the present invention is described in detail
Flat conversion circuit.Below in conjunction with Fig. 1 to Fig. 4 to the level conversion of the liquid crystal display panel of thin film transistor of the embodiment of the present invention
Method is described.
The level conversion method of liquid crystal display panel of thin film transistor provided in an embodiment of the present invention the following steps are included:
Sequence controller sends control signal to level translator by the first pin on the sequence controller, described
First control signal high level lasting time or first control signal low level of the signal within a signal period is controlled to continue
Time is T1, and the second control signal high level lasting time or second control signal low level within a signal period continue
Time is T2, and the third control signal high level lasting time or third control signal low level within a signal period continue
Time is T3.
The level translator receives what the sequence controller was sent by the second pin on the level translator
The control signal, and n driving signal is generated according to the control signal, i-th of driving letter in the n driving signals
Number the driving signal high level lasting time in a signal period be equal to the T1, within a signal period driving letter
Number the low level duration is equal to the T2, or the driving signal high level lasting time within a signal period is equal to institute
State T2, the driving signal the low level duration within a signal period is equal to the T1, the height of i-th of driving signal
Level is the conducting voltage of the thin film transistor (TFT), and the low level of i-th of driving signal is cutting for the thin film transistor (TFT)
Only voltage is divided between the rising edge initial time of i-th of driving signal and the rising edge initial time of the control signal
(i-1) * T3, wherein n is the positive integer more than or equal to 1, i=1,2 ... n.
Therefore, the level conversion method of the liquid crystal display panel of thin film transistor of the embodiment of the present invention, sequence controller are logical
First pin crossed thereon sends a control signal to level translator, and level translator passes through one second thereon
Pin receives the control signal, so that sequence controller, which can control the level translator, generates multiple driving signals, by
This reduces the number of pins between sequence controller and level translator, simplifies circuit structure, reduces costs.
Optionally, the level translator generates n driving signal CKV1~CKVn, packet according to the control signal CK1
It includes:
The level translator decodes described T1, T2 and T3 in the control signal；
The level translator generates the first instruction of the information comprising described T1, T2 and T3 according to described T1, T2 and T3
Signal；
The level translator generates the n driving signals according to first indication signal.
Optionally, the level translator according to first indication signal generate n driving signal CKV1~
CKVn, comprising:
The level translator generates n second according to the information of described T1, T2 and T3 in first indication signal
Indication signal；
The level translator generates the n driving signals according to n second indication signals.
Specifically, i-th of second indication signal 0-CKVi in n the second indication signal 0-CKV1~0-CKVn exist
The second indication signal high level lasting time in one signal period is equal to the T1, i-th of second indication signal 0-
Second indication signal the low level duration of the CKVi within a signal period is equal to the T2.Alternatively, described i-th second
Second indication signal high level lasting time of the indication signal 0-CKVi within a signal period is equal to the T2, described i-th
Second indication signal the low level duration of a second indication signal 0-CKVi within a signal period is equal to the T1.Institute
State i-th of second indication signal 0-CKVi high level absolute value be less than the thin film transistor (TFT) conducting voltage absolute value,
The low level absolute value of i-th of second indication signal 0-CKVi is less than the absolute of the blanking voltage of the thin film transistor (TFT)
When the rising edge of value, the rising edge initial time of i-th of second indication signal 0-CKVi and the control signal CK1 originate
Between between be divided into (i-1) * T3.Specifically, for example, second finger of the 1st the second indication signal 0-CKV1 within a signal period
Show that signal high level lasting time is equal to the T1, the 1st second indication signal 0-CKV1 is within a signal period
Second indication signal the low level duration is equal to the T2.The high level of the 1st second indication signal 0-CKV1 is absolute
Value is less than the absolute value of the conducting voltage of the thin film transistor (TFT), and the low level of the 1st second indication signal 0-CKV1 is exhausted
It is less than the absolute value of the blanking voltage of the thin film transistor (TFT) to value.The rising edge of the 1st second indication signal 0-CKV1
0 is divided between initial time and the rising edge initial time of the control signal CK1.
Optionally, the level translator generates described in n according to n the second indication signal 0-CKV1~0-CKVn
Driving signal CKV1~CKVn, comprising:
The level translator receives n second indication signals；
The level translator amplifies n second indication signals, generates the n driving signals.
It is understood that each executing subject in the level conversion method of the embodiment of the present invention can correspond to the present invention
Modules in the level shifting circuit 200 of embodiment, and the corresponding process of the level conversion method is respectively by level
The above and other operation and/or function of modules in conversion circuit 200 is achieved.For sake of simplicity, no longer superfluous herein
It states.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily expect various equivalent modifications or
Replacement, these modifications or substitutions should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention Ying Yiquan
Subject to the protection scope that benefit requires.
Claims (4)
1. a kind of level shifting circuit of liquid crystal display panel of thin film transistor, including sequence controller and with the timing control
The level translator of device electrical connection, which is characterized in that the sequence controller includes the first pin, and the sequence controller passes through
First pin sends control signal, first control of the control signal within a signal period to the level translator
Signal high level lasting time processed or first control signal the low level duration are T1, the second control within a signal period
Signal high level lasting time processed or second control signal the low level duration are T2, the third control within a signal period
Signal high level lasting time processed or third control signal the low level duration are T3, wherein described T1, T2 and T3 are not
Zero；
The level translator include logical transition circuit, with the logical transition circuit be electrically connected logic control circuit,
The signal amplification circuit being electrically connected with the logic control circuit and the second pin being electrically connected with first pin, institute
Logic translator is stated to receive the control signal of the sequence controller transmission by the second pin and decode described
Described T1, T2 and T3 in signal are controlled, and generates the of the information comprising described T1, T2 and T3 according to described T1, T2 and T3
One indication signal, the logic control circuit receive first indication signal, and according to the institute in first indication signal
The information for stating T1, T2 and T3 generates n the second indication signals, and the signal amplification circuit receives n second indication signals,
And n second indication signals are amplified, n driving signal of generation, i-th in n second indication signals
The high level absolute value of second indication signal be less than the thin film transistor (TFT) conducting voltage absolute value, described i-th second
The low level absolute value of indication signal is less than the absolute value of the blanking voltage of the thin film transistor (TFT), i-th second instructions
(i-1) * T3 is divided between the rising edge initial time of signal and the rising edge initial time of the control signal；The n drivings
Driving signal high level lasting time of i-th of driving signal within a signal period in signal is equal to the T1, one
Driving signal the low level duration in a signal period is equal to the T2, or the driving signal within a signal period
High level lasting time is equal to the T2, the driving signal the low level duration within a signal period is equal to the T1,
The high level of i-th of driving signal is the conducting voltage of the thin film transistor (TFT), the low level of i-th of driving signal
For the blanking voltage of the thin film transistor (TFT), the rising edge initial time of i-th of driving signal and the control signal
(i-1) * T3 is divided between rising edge initial time, wherein n is the positive integer more than or equal to 1, i=1,2 ... n.
2. level shifting circuit according to claim 1, which is characterized in that i-th in n second indication signals
Second indication signal high level lasting time of a second indication signal within a signal period is equal to the T1, believes at one
The second indication signal the low level duration in number period is equal to the T2, or the second instruction within a signal period
Signal high level lasting time is equal to the T2, the second indication signal the low level duration within a signal period is equal to
The T1.
3. a kind of level conversion method of liquid crystal display panel of thin film transistor characterized by comprising
Sequence controller sends control signal, the control to level translator by the first pin on the sequence controller
First control signal high level lasting time or first control signal the low level duration of the signal within a signal period
For T1, second control signal high level lasting time or second control signal the low level duration within a signal period
For T2, third control signal high level lasting time or third within a signal period control signal the low level duration
For T3；Wherein, described T1, T2 and T3 are not zero；
The level translator receives the described of the sequence controller transmission by the second pin on the level translator
Signal is controlled, and n driving signal is generated according to the control signal, i-th of driving signal in the n driving signals exists
It is low that driving signal high level lasting time in one signal period is equal to the T1, the driving signal within a signal period
Level duration is equal to the T2, or the driving signal high level lasting time within a signal period is equal to described
T2, the driving signal the low level duration within a signal period are equal to the T1, the height electricity of i-th of driving signal
It puts down as the conducting voltage of the thin film transistor (TFT), the low level of i-th of driving signal is the cut-off of the thin film transistor (TFT)
Voltage is divided into (i- between the rising edge initial time of i-th of driving signal and the rising edge initial time of the control signal
1) * T3, wherein n is the positive integer more than or equal to 1, i=1,2 ... n；Wherein, the level translator is according to the control
Signal generates the n driving signals, comprising:
The level translator decodes described T1, T2 and T3 in the control signal；
The level translator generates the first indication signal of the information comprising described T1, T2 and T3 according to described T1, T2 and T3；
The level translator generates n second instruction according to the information of described T1, T2 and T3 in first indication signal
Signal；
The level translator receives n second indication signals；
The level translator amplifies n second indication signals, generates the n driving signals, wherein n
The high level absolute value of i-th of second indication signals in second indication signal is less than the electric conduction of the thin film transistor (TFT)
The absolute value of pressure, the low level absolute value of i-th of second indication signals are less than the blanking voltage of the thin film transistor (TFT)
Absolute value, between the rising edge initial time of i-th of second indication signals and the rising edge initial time of the control signal
It is divided into (i-1) * T3.
4. level conversion method according to claim 3, which is characterized in that i-th in n second indication signals
Second indication signal high level lasting time of a second indication signal within a signal period is equal to the T1, believes at one
The second indication signal the low level duration in number period is equal to the T2, or the second instruction within a signal period
Signal high level lasting time is equal to the T2, the second indication signal the low level duration within a signal period is equal to
The T1.
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| CN105761694B (en) * | 2016-05-12 | 2019-02-26 | 深圳市华星光电技术有限公司 | Level translator for array substrate gate driving circuit |
| CN106448580A (en) * | 2016-05-25 | 2017-02-22 | 深圳市华星光电技术有限公司 | Level shift circuit and display panel having level shift circuit |
| CN105810169A (en) | 2016-05-25 | 2016-07-27 | 深圳市华星光电技术有限公司 | Drive system and method of liquid crystal display |
| CN106169289B (en) * | 2016-09-27 | 2019-01-04 | 深圳市华星光电技术有限公司 | A kind of array substrate horizontal drive circuit and its over-current protection method, liquid crystal display |
| CN107144989B (en) * | 2017-06-06 | 2020-06-05 | 昆山龙腾光电股份有限公司 | Wide-narrow visual angle switching module and liquid crystal display device |
| CN107481682A (en) * | 2017-07-21 | 2017-12-15 | 惠科股份有限公司 | Driving method and driving device of display panel |
| CN107395006B (en) * | 2017-09-13 | 2020-07-03 | 深圳市华星光电技术有限公司 | Overcurrent protection circuit and liquid crystal display |
| CN109979405B (en) * | 2019-03-27 | 2021-08-06 | 昆山龙腾光电股份有限公司 | Time sequence control circuit and display device |
| CN110310590B (en) * | 2019-06-17 | 2025-01-07 | 深圳市帝麦德斯科技有限公司 | A control chip for LED display screen drive system |
| CN113421509A (en) * | 2021-06-04 | 2021-09-21 | Tcl华星光电技术有限公司 | Drive circuit and display device |
| CN113612472B (en) * | 2021-07-01 | 2024-05-10 | 上海爻火微电子有限公司 | Level conversion circuit and electronic equipment |
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