CN114284363A - Thin film transistor and display panel - Google Patents
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- CN114284363A CN114284363A CN202111625183.2A CN202111625183A CN114284363A CN 114284363 A CN114284363 A CN 114284363A CN 202111625183 A CN202111625183 A CN 202111625183A CN 114284363 A CN114284363 A CN 114284363A
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Abstract
本申请公开了一种薄膜晶体管和显示面板。所述薄膜晶体管包括：玻璃基板，栅极，设置在所述玻璃基板上；栅绝缘层，设置在所述玻璃基板上，且覆盖所述栅极；氧化物半导体复合膜层，设置在所述栅绝缘层上，且位于所述栅极的上方；源漏极，包括源极和漏极，设置在所述氧化物半导体复合膜层上，且所述源极与所述漏极同层布置；其中，所述氧化物半导体复合膜层包括第一金属氧化物层、第二金属氧化物层和第三金属氧化物层，所述第二金属氧化物层和所述第三金属氧化物层中掺杂钛。本申请的薄膜晶体管可以有效减少半导体膜层中氧空位的生成，以及减少光照对氧化铟镓锌中载流子的浓度的影响，提高器件的稳定性。
The present application discloses a thin film transistor and a display panel. The thin film transistor comprises: a glass substrate, a gate, arranged on the glass substrate; a gate insulating layer, arranged on the glass substrate and covering the gate; an oxide semiconductor composite film layer, arranged on the glass substrate on the gate insulating layer and above the gate; a source and a drain, including a source and a drain, are arranged on the oxide semiconductor composite film layer, and the source and the drain are arranged in the same layer ; wherein, the oxide semiconductor composite film layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer, the second metal oxide layer and the third metal oxide layer doped titanium. The thin film transistor of the present application can effectively reduce the generation of oxygen vacancies in the semiconductor film layer, reduce the influence of light on the concentration of carriers in the indium gallium zinc oxide, and improve the stability of the device.
Description
Technical Field
The application relates to the technical field of display, in particular to a thin film transistor and a display panel.
Background
In the field of active matrix flat panel displays, including Active Matrix Liquid Crystal Displays (AMLCDs), Active Matrix Organic Light Emitting Diodes (AMOLEDs), thin film transistors (tfts) are used as switches for pixels, and have no substitutable function. High resolution, large size, and flexible displays have becomeThe development of display technology is a new direction, and for this reason, higher requirements are also placed on the thin film transistor. Oxide Thin Film Transistors (TFTs) are particularly useful in large size and high resolution and flexible displays due to their amorphous structure, higher mobility and lower cost than a-Si. In order to improve the stability of an oxide TFT, a TFT having an Etch Stop Layer (ESL) structure is widely used, and the structure can effectively reduce the influence of external environmental factors and the etching damage of source and drain electrodes on a back channel. However, the array fabrication method of the Etch Stop Layer (ESL) structure requires more mask times and significantly increases the TFT size and parasitic capacitance. The Back Channel Etching (BCE) structure TFT does not need an etching barrier layer, and the channel can be obviously reduced compared with an ESL structure, so that the back channel TFT has lower production cost and technical advantages compared with the ESL structure, but the back channel TFT is easily influenced by a post-processing procedure, so that the performance of a device is poor, the process requirement is higher, and the back channel TFT is generally applied to an LCD. With the increasing display requirements, i.e., the popularization of high resolution and high refresh rate, higher requirements are put on the mobility of the TFT, and the mobility of the Indium Gallium Zinc Oxide (IGZO) TFT which is currently available for mass production is far from sufficient, and needs to be improved urgently. Meanwhile, an active layer widely adopted by the oxide TFT with the back channel etching type (BCE) structure is ZnO doped with In/Ga (indium gallium oxide), namely IGZO, which is very sensitive to water and oxygen and is easily influenced by H injection, so that the performance of the device is poor. Therefore, the selection of the insulating layers of the upper and lower layers is limited, and SiO with certain water and oxygen blocking function and less hydrogen and oxygen is mostly adoptedxThe process is relatively limited and the storage stability of the device is poor. In addition, the TFT with IGZO as an active layer is sensitive to illumination, and photo-generated carriers are easily generated under illumination, which is not favorable for illumination stability of the device. Oxide devices of Back Channel Etch (BCE) architecture are susceptible to top light.
Therefore, it is desirable to provide a thin film transistor to reduce the influence of light and improve the light stability.
Disclosure of Invention
In order to overcome the defects of the prior art, the thin film transistor provided by the application can effectively reduce the generation of oxygen vacancies in a semiconductor film layer, reduce the influence of illumination on the concentration of carriers in IGZO and improve the stability of a device.
The present application provides a thin film transistor, comprising:
a glass substrate having a plurality of glass layers,
a gate electrode disposed on the glass substrate;
the grid insulating layer is arranged on the glass substrate and covers the grid;
the oxide semiconductor composite film layer is arranged on the gate insulating layer and is positioned above the gate;
the source and drain electrodes are arranged on the oxide semiconductor composite film layer and comprise a source electrode and a drain electrode, and the source electrode and the drain electrode are arranged on the same layer;
the oxide semiconductor composite film layer comprises a first metal oxide layer, a second metal oxide layer and a third metal oxide layer, wherein the second metal oxide layer and the third metal oxide layer are doped with titanium.
Optionally, in some embodiments of the present application, the molar percentage of titanium in the second metal oxide layer is 0.1% to 1.5%.
Optionally, in some embodiments of the present application, the molar percentage of titanium in the third metal oxide layer is 1.5% to 3%.
Optionally, in some embodiments of the present application, the first metal oxide layer is located on a side of the gate insulating layer facing away from the gate electrode, the second metal oxide layer is located on a side of the first metal oxide layer facing away from the gate insulating layer, and the third metal oxide layer is located on a side of the second metal oxide layer facing away from the first metal oxide layer.
Optionally, in some embodiments of the present application, the thin film transistor further includes a protective layer located on the gate insulating layer and covering the source electrode and the drain electrode.
Optionally, in some embodiments of the present application, the material of the protective layer includes SiOx。
Optionally, in some embodiments of the present application, the material of the oxide semiconductor composite film layer includes Indium Gallium Zinc Oxide (IGZO).
Optionally, in some embodiments of the present application, a material of the first metal oxide layer includes Indium Gallium Zinc Oxide (IGZO).
Optionally, in some embodiments of the present application, the second metal oxide layer is formed by doping indium gallium zinc with metal titanium.
Optionally, in some embodiments of the present application, the third metal oxide layer is formed by doping indium gallium zinc with metal titanium.
Optionally, in some embodiments of the present application, the second metal oxide layer includes two portions separately disposed from each other, and the two portions are respectively connected to two ends of the first metal oxide layer. The third metal oxide layer comprises two parts which are separated from each other and are respectively connected with the two parts which are separated from each other of the second metal oxide layer.
Optionally, in some embodiments of the present application, the source electrode and the drain electrode are respectively connected to two portions of the third metal oxide layer, which are spaced apart from each other.
Optionally, in some embodiments of the present application, a material of the gate insulating layer includes SiOx。
Correspondingly, the application also provides a display panel comprising the thin film transistor.
The beneficial effect of this application lies in:
the present application provides an oxide semiconductor composite film layer using a multi-layered semiconductor film in a Back Channel Etch (BCE) structure Thin Film Transistor (TFT) in a thin film transistor, and particularly, an oxide semiconductor composite film layer having three semiconductor films, two of which are doped with different contents of a metal element titanium.
In the thin film transistor, metal oxide is a main semiconductor layer, and titanium (Ti) has low oxygen negativity and strong binding force with oxygen (O), so that the generation of oxygen vacancies in a semiconductor film layer can be reduced, the concentration of current carriers in the film is reduced, and the stability of a device is improved. When the content of Ti is lower, such as the second metal oxide layer, free oxygen in the semiconductor film layer can be reduced, the reduction of effective carrier concentration caused by self collision among conductive ions can be reduced, and the mobility of the device can be improved to a certain extent; when the Ti content continues to increase, such as in the third metal oxide layer, the carrier concentration decreases and the stability improves.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a thin film transistor provided in an embodiment of the present application;
fig. 2 is a first schematic structural diagram in a process of manufacturing an oxide semiconductor composite film layer in a thin film transistor according to an embodiment of the present disclosure;
fig. 3 is a second schematic structural diagram in the process of manufacturing an oxide semiconductor composite film layer in a thin film transistor according to an embodiment of the present disclosure;
fig. 4 is a schematic partial structural diagram of a thin film transistor provided in an embodiment of the present application.
Description of reference numerals: 100. a thin film transistor; 110. a glass substrate; 120. a gate electrode; 130. a gate insulating layer; 140. an oxide semiconductor composite film layer; 141. a first metal oxide layer; 142. a second metal oxide layer; 143. a third metal oxide layer; 150. a source and a drain; 151. a source electrode; 152. a drain electrode; 160. and a protective layer.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In this application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to upper and lower portions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings.
The embodiment of the application provides a thin film transistor and a display panel. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
The embodiment of the present application provides a thin film transistor 100, please refer to fig. 1, which includes a glass substrate 110, a gate electrode 120, a gate insulating layer 130, an oxide semiconductor composite film layer 140, and a source/drain 150.
Further, the gate electrode 120 is a metal layer, and the gate electrode 120 is disposed on the glass substrate 110. The Gate insulating layer 130 (GI) is disposed on the glass substrate 110, and the Gate insulating layer 130 covers the Gate electrode 120; it is conceivable that the gate insulating layer 130 is disposed on a side of the gate electrode 120 facing away from the glass substrate 110, and on a same side of the glass substrate 110 as the gate electrode 120. Further, the material of the gate insulating layer 130 may be silicon oxide (SiO)x)。
In the embodiment of the present invention, the oxide semiconductor composite film layer 140 is disposed on a side of the gate insulating layer 130 away from the gate electrode 120. The oxide semiconductor composite film layer 140 is located above the gate electrode 120. Further, the oxide semiconductor composite film layer 140 includes a first metal oxide layer 141, a second metal oxide layer 142, and a third metal oxide layer 143. The first metal oxide layer 141 is disposed on a side of the gate insulating layer 130 facing away from the gate electrode 120. The second metal oxide layer 142 is disposed on a side of the first metal oxide layer 141 facing away from the gate insulating layer 130. The third metal oxide layer 143 is disposed on a side of the second metal oxide layer 142 facing away from the first metal oxide layer 141.
Further, the second metal oxide layer 142 includes two portions spaced apart from each other and disposed at both ends of the first metal oxide layer 141, respectively. Further, the third metal oxide layer 143 includes two portions spaced apart from each other, and is disposed on the two portions of the second metal oxide layer 142 spaced apart from each other.
Further, the second metal oxide layer 142 and the third metal oxide layer 143 are doped with titanium. The material of the first metal oxide layer 141 includes Indium Gallium Zinc Oxide (IGZO). Further, the second metal oxide layer 142 and the third metal oxide layer 143 may each include indium gallium zinc oxide.
The source and drain 150 is a metal layer, and the source and drain 150 is disposed on a side of the oxide semiconductor composite film layer 140 deviating from the gate insulating layer 130 and the gate electrode 120. Further, the source and drain 150 is divided into a source 151 and a drain 152, the source 151 and the drain 152 are disposed in the same layer, and the source 151 and the drain 152 are spaced apart from each other.
Further, as shown in fig. 1, the second metal oxide layer 142 and the third metal oxide layer 143 under the source 151 and the drain 152 respectively correspond to the source 151 and the drain 152 one by one, that is, the second metal oxide layer 142 and the third metal oxide layer 143 include two parts that are separated and not connected to each other, and are respectively connected to the source 151 and the drain 152 above the two parts.
In some embodiments of the present application, the molar percentage of titanium in the second metal oxide layer 142 may be 0.1%, 0.2%, 0.4%, 0.5%, 0.8%, 1.0%, 1.2%, 1.4%, or 1.5%. Further, the second metal oxide layer 142 may be metal titanium doped in indium gallium zinc oxide.
In some embodiments of the present application, the molar percentage of titanium in the third metal oxide layer may be 1.5%, 1.6%, 1.8%, 2.0%, 2.2%, 2.5%, 2.7%, 2.9%, or 3%. Further, the third metal oxide layer may be formed by doping metal titanium in indium gallium zinc oxide.
In the embodiment of the present application, the oxide semiconductor composite film 140 is a main semiconductor layer, and titanium (Ti) has low oxygen negativity and strong binding force with oxygen (O), so that generation of oxygen vacancies in the semiconductor film can be reduced, the concentration of carriers in the film can be reduced, and the stability of the device can be improved. When the content of Ti is low, free oxygen in the semiconductor film layer can be reduced, the decrease in the effective carrier concentration due to self-collision between conductive ions can be reduced, and the mobility of the device can be improved to some extent. As the Ti content continues to increase, the carrier concentration decreases and stability improves.
It is known that IGZO is sensitive to light, and a photo-generated carrier is easily generated under light, which is not favorable for light stability of the device. Oxide devices with back channel etch type structures are susceptible to top light. In the embodiment of the present application, the semiconductor device has a multilayer semiconductor structure, for example, two titanium-doped IGZO layers are disposed on the IGZO layer, and in the two titanium-doped IGZO layers, not only can the influence of light on the device be effectively reduced, but also free oxygen in the semiconductor film layer can be effectively reduced.
In some embodiments of the present application, the first metal oxide layer 141 is located on a side of the gate insulating layer 130 facing away from the gate electrode 120, the second metal oxide layer 142 is located on a side of the first metal oxide layer 141 facing away from the gate insulating layer 130, and the third metal oxide layer is located on a side of the second metal oxide layer 142 facing away from the first metal oxide layer 141.
In some embodiments of the present application, with continued reference to fig. 1, the thin film transistor 100 further includes a protection layer 160. The protection layer 160 is an inorganic insulating cover layer, and is located on the gate insulating layer 130 and covers the source electrode and the drain electrode. Further, the material of the protection layer 160 includes SiOx. The protective layer 160 can protect the layer and has the function of blocking water and oxygen; has the function of supplementing oxygen with less hydrogen.
In an embodiment of the present application, with reference to fig. 1, the thin film transistor 100 includes:
the glass substrate 110, the grid 120 is set up on the said glass substrate 110;
the gate insulating layer 130 is arranged on one side, away from the glass substrate 110, of the gate electrode 120, and meanwhile, the gate insulating layer 130 is arranged on the glass substrate 110 and covers the gate electrode 120;
an oxide semiconductor composite film layer 140 disposed on the gate insulating layer 130, the oxide semiconductor composite film layer 140 including: a first metal oxide layer 141 disposed on a side of the gate insulating layer 130 away from the glass substrate 110, where the first metal oxide layer may be indium gallium zinc oxide; a second metal oxide layer 142, disposed on a side of the first metal oxide layer 141 away from the glass substrate 110 or the gate insulating layer 130, where the second metal oxide layer 142 may be a material doped with indium-gallium-zinc-oxide and having a low content of titanium, and the second metal oxide layer 142 includes two parts that are separated from each other and disposed on the same layer, and are respectively connected to two ends of the first metal oxide layer 141; a third metal oxide layer 143, disposed on a side of the second metal oxide layer 142 away from the first metal oxide layer 141, where the third metal oxide layer 143 may be made of a material doped with high-content titanium, indium gallium zinc oxide, and the third metal oxide layer 143 includes two parts that are separated from each other and disposed on the same layer, and are respectively connected to the two parts of the second metal oxide layer 142;
a source/drain 150 disposed on the third metal oxide layer 143, wherein the source/drain 150 includes a source 151 and a drain 152, and is respectively connected to two portions of the third metal oxide layer 143;
and the protective layer 160 is disposed on the gate insulating layer 130, the oxide semiconductor composite film layer 140, and the source/drain 150, and is used for isolating water and oxygen to protect. The material of the protective layer may be silicon oxide, such as SiOx。
Further, the oxide semiconductor composite film layer 140 is located above the gate electrode 120 in the thin film transistor 100. It is conceivable that the front projection of the oxide semiconductor composite film layer 140 on the glass substrate 110 has an overlapping portion with the gate electrode 120.
The embodiment of the present application further provides a manufacturing process of the thin film transistor, please refer to fig. 2, fig. 3, and fig. 4, and fig. 2, fig. 3, and fig. 4 show a process of the oxide semiconductor composite film.
In one embodiment, the process for preparing an oxide semiconductor composite film layer in a thin film transistor includes:
step one, referring to fig. 2, a gate electrode 120 is formed on a glass substrate 110, and a gate insulating layer 130 is formed on the glass substrate 110 and the gate electrode 120; forming a full-surface first metal oxide layer 141 ″ on the gate insulating layer 130, forming a full-surface second metal oxide layer 142 ″ on the first metal oxide layer 141 ″, and forming a full-surface third metal oxide layer 143 ″ on the second metal oxide layer 142 ″;
step two, referring to fig. 3, patterning the film layer obtained in the step one to form a first metal oxide layer 141, a pre-second metal oxide layer 142 'and a pre-third metal oxide layer 143';
step three, referring to fig. 4, the film layer obtained in step two is patterned, a trench is formed in a portion of the second metal oxide layer 142 'and a portion of the third metal oxide layer 143', so that two portions separated from each other are formed, the second metal oxide layer 142 and the third metal oxide layer 143 are formed, and finally, the oxide semiconductor composite film layer is formed.
Further, in the first step, it is understood that a layer of metal oxide (e.g., Indium Gallium Zinc Oxide (IGZO)) is deposited on the gate insulating layer 130, and a layer of titanium (Ti) -doped oxide (e.g., titanium-doped Indium Gallium Zinc Oxide (IGZO)) is deposited, wherein the molar percentage of Ti is 0.1% to 1.5%; a layer of metal oxide with high Ti content is deposited on the surface, wherein the mol percentage of Ti is between 1.5 percent and 3 percent.
Furthermore, the oxide semiconductor composite film layer is of a multilayer structure, the lowest layer is a metal oxide, a titanium-containing oxide with a lower doping proportion is arranged on the metal oxide, and then a layer of oxide with titanium higher than that of the first layer is deposited on the metal oxide. Further, the titanium-containing oxide may be prepared by a magnetron sputtering method, and the titanium-containing oxide film may be formed by: the content of titanium is regulated and controlled during the preparation of the target material, wherein the content of titanium in the powder is controlled, the powder is ground and sintered after grinding to prepare the target material containing specific titanium content, and finally a film containing a certain amount of titanium is formed by a magnetron sputtering method.
Further, with reference to fig. 1 and fig. 4, a source/drain 150 is continuously formed on the film layer shown in fig. 4; then, a protective layer 160 is formed on the entire surface of the glass substrate to isolate water and oxygen.
The embodiment of the application also provides a display panel, which comprises the thin film transistor.
To sum up, the thin film transistor of this application through the setting of the compound rete of multilayer oxide semiconductor, effectively reduces the formation of oxygen vacancy in the semiconductor rete, and then reduces the concentration of current carrier in the film to and reduce irradiant influence, improved the illumination stability of device.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The foregoing detailed description is directed to a thin film transistor and a display panel provided in the embodiments of the present application, and specific examples are used herein to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
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