CN114281582B - Electrical failure analysis method and related device - Google Patents
Electrical failure analysis method and related device Download PDFInfo
- Publication number
- CN114281582B CN114281582B CN202111470371.2A CN202111470371A CN114281582B CN 114281582 B CN114281582 B CN 114281582B CN 202111470371 A CN202111470371 A CN 202111470371A CN 114281582 B CN114281582 B CN 114281582B
- Authority
- CN
- China
- Prior art keywords
- failure
- frequency
- structural layer
- low
- size
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004458 analytical method Methods 0.000 title claims abstract description 97
- 238000012360 testing method Methods 0.000 claims abstract description 219
- 238000013461 design Methods 0.000 claims abstract description 32
- 230000001502 supplementing effect Effects 0.000 claims description 7
- 239000013589 supplement Substances 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 description 70
- 238000000034 method Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 10
- 238000003745 diagnosis Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 238000007405 data analysis Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 101100282115 Candida albicans (strain SC5314 / ATCC MYA-2876) HIP1 gene Proteins 0.000 description 1
- 101500023488 Lithobates catesbeianus GnRH-associated peptide 1 Proteins 0.000 description 1
- 101500022510 Lithobates catesbeianus GnRH-associated peptide 2 Proteins 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 101150112629 gap3 gene Proteins 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The application provides an electrical failure analysis method which comprises the steps of obtaining a failure log of each failure grain of a wafer, determining each high-frequency leading failure grain and each low-frequency leading failure grain according to a high-frequency test result and a low-frequency test result in the failure log of the failure grain, obtaining a current high-frequency leading failure weight value, obtaining a failure deviation value of each structural layer according to the high-frequency failure size of each structural layer of each high-frequency leading failure grain, the low-frequency failure size of each structural layer of each low-frequency leading failure grain, the current high-frequency leading failure weight value and the design size of each structural layer of the wafer, and adjusting the current high-frequency leading failure weight value according to the failure deviation value and a preset deviation threshold until the failure deviation value of at least one structural layer meets the preset deviation threshold value, so as to obtain a maximum failure influence layer corresponding to the maximum failure deviation value. The electrical failure analysis method provided by the embodiment of the application can improve the accuracy of electrical failure analysis.
Description
Technical Field
The embodiment of the invention relates to the field of integrated circuits, in particular to an electrical failure analysis method and a related device.
Background
The electrical failure analysis (eFA) is the most common method for capturing chip defects, wherein Scan chain diagnosis (Scan diagnosis) is the most common analysis method for complex and large chips at present, the Scan chain diagnosis (Scan diagnosis) is divided into two major categories of low-frequency test (DC-Scan) and high-frequency test (AC-Scan) according to the difference of test frequencies, the chip working frequency is gradually accelerated along with the progressive process of the manufacturing process to deep micro-meter, the high-speed function abnormality caused by the resistance problem of the high-resistance path is more common, and various problems can occur on the chip passing through the original low-frequency test (DC-Scan) under the high working frequency, so that the high-frequency test (AC-Scan) is widely applied under the background that all defects can not be captured by the original low-frequency test (DC-Scan), and the test items of the low-frequency test (DC-Scan) are gradually reduced.
However, even so, in the test result, the number of die (die) dominated by low frequency failure (DC-SCAN) is still large, so that the low frequency test (DC-SCAN) failure data is dominant, the high frequency test (AC-SCAN) failure data is submerged, the function of the high frequency test (AC-SCAN) failure data in electrical failure analysis cannot be accurately reflected, and the accuracy of the high frequency test (AC-SCAN) electrical failure analysis is affected.
Therefore, how to improve the accuracy of the electrical failure analysis in the high-frequency test is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
Therefore, the electrical failure analysis method provided by the embodiment of the application can ensure that the high-frequency test failure data is not submerged by the low-frequency test failure data during electrical failure analysis, and improves the accuracy of the high-frequency test electrical failure analysis.
In order to achieve the above purpose, the embodiment of the present application provides the following technical solutions.
In a first aspect, an embodiment of the present application provides an electrical failure analysis method, including:
obtaining a failure log of each failure grain of the wafer;
determining each high-frequency dominant failure grain and each low-frequency dominant failure grain according to a high-frequency test result and a low-frequency test result in the failure log of each failure grain;
acquiring a current high-frequency dominant failure weight value;
obtaining a failure deviation value of each structural layer according to a high-frequency failure size of each structural layer in the failure log of each high-frequency dominant failure grain, a low-frequency failure size of each structural layer in the failure log of each low-frequency dominant failure grain, the current high-frequency dominant failure weight value and a design size of each structural layer of the wafer, and adjusting the current high-frequency dominant failure weight value according to the failure deviation value and a preset deviation threshold until the failure deviation value of at least one structural layer meets the preset deviation threshold, thereby obtaining a maximum failure influence layer corresponding to the maximum failure deviation value.
In a second aspect, an embodiment of the present application provides an electrical failure analysis apparatus, including:
the failure log acquisition module is suitable for acquiring the failure log of each failure grain of the wafer;
The failure grain determining module is suitable for determining each high-frequency dominant failure grain and each low-frequency dominant failure grain according to a high-frequency test result and a low-frequency test result in the failure log of each failure grain;
the high-frequency leading failure weight value acquisition module is suitable for acquiring the current high-frequency leading failure weight value;
The maximum failure influence layer acquisition module is suitable for acquiring failure deviation values of all the structural layers according to high-frequency failure sizes of all the structural layers in the failure logs of all the high-frequency dominant failure grains, low-frequency failure sizes of all the structural layers in the failure logs of all the low-frequency dominant failure grains, the current high-frequency dominant failure weight value and design sizes of all the structural layers of the wafer, and adjusting the current high-frequency dominant failure weight value according to the failure deviation values and a preset deviation threshold until the failure deviation value of at least one structural layer meets the preset deviation threshold, so as to acquire the maximum failure influence layer corresponding to the maximum failure deviation value.
In a third aspect, an embodiment of the present application provides a storage medium storing a program adapted for electrical failure analysis to implement the electrical failure analysis method according to the first aspect.
In a fourth aspect, an embodiment of the present application provides an electronic device, including at least one memory and at least one processor, where the memory stores a program, and the processor invokes the program to perform the electrical failure analysis method according to the first aspect.
The electrical failure analysis method comprises the steps of firstly obtaining failure logs of all failure grains of a wafer when electrical failure analysis is carried out, then determining all high-frequency dominant failure grains and all low-frequency dominant failure grains according to high-frequency test results and low-frequency test results in the failure logs of all the failure grains, then obtaining current high-frequency dominant failure weight values, and finally obtaining the maximum failure effect layer corresponding to the maximum failure deviation value according to the high-frequency failure size of all the structural layers in the failure logs of all the high-frequency dominant failure grains, the low-frequency failure size of all the structural layers in the failure logs of all the low-frequency dominant failure grains, the current high-frequency dominant failure weight values and the design size of all the structural layers of the wafer, and further adjusting the current high-frequency dominant failure weight values according to the failure deviation value and a preset deviation threshold value until the failure deviation value of at least one structural layer meets the preset deviation threshold value.
In this way, according to the electrical failure analysis method provided by the embodiment of the application, each high-frequency dominant failure grain and each low-frequency dominant failure grain are determined according to the failure log of each failure grain of the wafer, so that the high-frequency dominant failure data and each low-frequency dominant failure data are distinguished, then the design size of each structural layer of the wafer and the failure size of each high-frequency dominant failure grain are combined with the failure size of each low-frequency dominant failure grain which is not weighted after weight adjustment according to the current high-frequency dominant failure weight value, and the failure size of each low-frequency dominant failure grain is obtained, thus, the addition of the failure size of each low-frequency dominant failure grain can ensure the required data amount in the process of electrical failure analysis, and meanwhile, when the failure deviation value is obtained, the weight of the high-frequency dominant failure size is increased through the current high-frequency dominant failure weight value, and then a preset deviation threshold is combined, so that the high-frequency dominant failure data is displayed until the failure deviation value of at least one structural layer meets the preset deviation threshold, and then the failure deviation value of the structural layer corresponding to the maximum failure deviation value is obtained, and the failure layer is affected accurately. It can be seen that the electrical failure analysis method provided by the embodiment of the application can ensure enough data quantity by using the low-frequency test dominant failure data, and can also ensure that the high-frequency test dominant failure data is highlighted, but not submerged by the low-frequency test failure data, so that the influence of the high-frequency test failure data is fully displayed, and the accuracy of the electrical failure analysis of the high-frequency test is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram illustrating flooding of high frequency test failure data in the prior art;
FIG. 2 is a schematic flow chart of an alternative electrical failure analysis method according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an obtaining flow of a failure log of an electrical failure analysis method according to an embodiment of the present application;
FIG. 4 is a schematic diagram of an alternative failure grain classification of the electrical failure analysis method according to an embodiment of the present application;
FIG. 5 is a schematic diagram of an alternative failure deviation value obtaining flow chart of an electrical failure analysis method according to an embodiment of the present application;
Fig. 6 is a block diagram of an electrical failure analysis apparatus according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In combination with the foregoing discussion, during electrical failure analysis, high-frequency test (AC-SCAN) failure data may be submerged, so that the effect of the high-frequency test (AC-SCAN) failure data during electrical failure analysis may not be accurately reflected, and the accuracy of the high-frequency test (AC-SCAN) electrical failure analysis may be affected.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating that high frequency test failure data is submerged in the prior art.
As shown in the figure, M1, M3, K2, and G1 are only examples of the structural layer, when the high-frequency test failure data is not submerged (only the high-frequency failure data, i.e., the middle table in fig. 1), the failure size of the structural layer G1 is the largest (100), the failure proportion of G1 is the largest, and correspondingly, the failure deviation value of G1 is the largest, and it can be seen through data analysis that the probability of failure of the structural layer G1 is the largest, i.e., the structural layer G1 is the main cause of the grain failure.
When the low frequency failure data is added (when the high frequency failure data and the low frequency failure data are both included, i.e. the lowest table in the figure), as can be seen from the figure, the total failure size becomes the largest failure size (142) of the structural layer M3, the total failure proportion of M3 is also the largest, and correspondingly, the total failure deviation value of M3 is also the largest, and the probability of failure of the structural layer M3 is the largest through data analysis, i.e. the structural layer M3 is the main cause of the grain failure.
Therefore, due to the addition of the low-frequency failure data, the high-frequency failure data is submerged, so that the effect of the high-frequency test failure data in electrical failure analysis is reduced, the high-frequency test failure data cannot be accurately reflected, and the accuracy of the high-frequency test electrical failure analysis is affected.
For this reason, an embodiment of the present application provides an electrical failure analysis method, please refer to fig. 2, and fig. 2 is an optional flow chart of the electrical failure analysis method provided by the embodiment of the present application.
As shown in the figure, the electrical failure analysis method provided by the embodiment of the application comprises the following steps:
step S20, obtaining the failure log of each failure grain of the wafer.
It is easy to understand that before failure analysis is performed, the wafer is tested by using test items of the wafer test, each failure grain of the wafer is obtained according to the test result, and then a failure log of each failure grain of the wafer is obtained for failure analysis.
In a specific embodiment, the wafer may be tested using an ATE test bench and failure logs collected, and the failure logs may be analyzed using various EDA failure analysis tools, the application is not limited to use with tools for wafer testing, failure log collection, and failure log analysis, and in various embodiments, suitable tools may be used to accomplish this.
With the requirements for upgrading the test mode of the mass production wafer and optimizing the test time, in the existing wafer test items, the test items of the low-frequency test (DC-SCAN) are gradually simplified, and some test items are deleted from the original test items of the low-frequency test (DC-SCAN), so that in a specific embodiment, the application can acquire the failure logs of each failed crystal grain of the wafer according to the existing wafer test items.
However, since the test items of the low frequency test (DC-SCAN) are deleted, the test data of the low frequency test is insufficient, which may cause some dies that fail the low frequency test to be wrongly classified as dies that fail the high frequency test, and further affect the accuracy of the electrical failure analysis of the high frequency test, so in order to ensure the accuracy of classifying the failed dies, the embodiment of the present application further provides another electrical failure analysis method, please refer to fig. 3, fig. 3 is a schematic diagram of an obtaining flow of a failure log of the electrical failure analysis method provided by the embodiment of the present application, where the step of obtaining the failure log of each failed die of the wafer in the electrical failure analysis method provided by the embodiment of the present application may include:
And S30, testing the wafer by using test items tested by the wafer, and obtaining each failure grain and a first failure log of each failure grain, wherein the low-frequency test items in the test items are less than the high-frequency test items.
Firstly, testing the wafer by using the test items of the existing wafer test to obtain each failed grain and the first failure log of each failed grain, wherein the test items of the existing wafer test have some low-frequency test (DC-SCAN) items deleted, so that the low-frequency test items in the test items are less than the high-frequency test items.
And S31, supplementing the low-frequency test item.
Since test items of the low frequency test (DC-SCAN) are deleted, resulting in insufficient test data of the low frequency test, it is possible that some dies that fail the low frequency test are misclassified as dies that fail the high frequency test, so that the test items of the low frequency test (DC-SCAN) may be supplemented so as not to affect the accuracy of the analysis of the electrical failure of the high frequency test.
In a specific embodiment, the step of supplementing the low frequency test item comprises supplementing the low frequency test item with the high frequency test item.
Therefore, the low-frequency test items can be more complete, and the low-frequency test items can be more simply supplemented, so that the test result can be more accurate simply, and the accuracy of electrical failure analysis is ensured.
And S32, performing a second test on each failed grain according to the low-frequency test item to obtain a second failure log of each failed grain.
After the low-frequency test item is supplemented, performing a second test on each failure grain obtained according to the supplemented low-frequency test item, so as to obtain a second failure log of each failure grain.
And step S33, obtaining the failure logs of the failure grains according to the first failure log and the second failure log.
After the first failure log and the second failure log of each failure grain are obtained, the first failure log and the second failure log are combined, and the required failure log of each failure grain is obtained.
Therefore, the first failure log of each failure grain is obtained according to the existing low-frequency test item, then the low-frequency test item is supplemented, the second failure log of each failure grain is obtained according to the supplemented low-frequency test item, and finally the obtained failure log of each failure grain can enable the low-frequency test item to be more complete, avoid errors caused by the loss of the low-frequency test item and further ensure the accuracy of electrical failure analysis of the high-frequency test, and on the other hand, only the obtained low-frequency test item is tested, so that the workload required by the test can be reduced on the basis of meeting the test accuracy.
Of course, in another specific embodiment, in order to ensure the accuracy of classifying the failed grains, the low-frequency test items can be supplemented before the test, and then the wafer test is performed, so that the completeness of the low-frequency test items can be ensured, errors caused by the absence of the low-frequency test items can be avoided, and the accuracy of electrical failure analysis of the high-frequency test can be improved.
Therefore, based on the method, the failure log of each failure grain of the wafer can be obtained, and the electrical failure analysis can be continued.
For this reason, please continue with reference to fig. 2, step S21 is to determine each high frequency dominant failure grain and each low frequency dominant failure grain according to the high frequency test result and the low frequency test result in the failure log of each failure grain.
After the failure logs of each failure grain are obtained, each high-frequency dominant failure grain and each low-frequency dominant failure grain are determined according to the high-frequency test result and the low-frequency test result in each failure log, and in a specific embodiment, the written software script can be utilized to realize the distinction of marks of each high-frequency dominant failure grain and each low-frequency dominant failure grain, so that the distinction accuracy is ensured, and the obtaining efficiency of the high-frequency dominant failure grain and the low-frequency dominant failure grain is improved.
In a specific embodiment, to facilitate determination of high frequency dominant failure grains and low frequency dominant failure grains, the step of determining each high frequency dominant failure grain and each low frequency dominant failure grain from high frequency test results and low frequency test results in the failure log of each of the failure grains may include:
And when the low-frequency test result of the failed grain is passing, but the high-frequency test result of the failed grain is failed, determining that the failed grain is a high-frequency dominant failed grain.
In a specific test process, if the low frequency test of a certain grain fails, the high frequency test of the grain also fails, but the main reason of the failure of the grain test is that the low frequency test fails, so that the failed grain can be classified and marked according to the high frequency test result and the low frequency test result in each failure log of the failed grain, when the test result is that the low frequency test fails, the failed grain can be determined and marked as the low frequency dominant failure grain, and when the test result is that the low frequency test passes but the high frequency test fails, the failed grain can be determined and marked as the high frequency dominant failure grain.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating an alternative failure grain classification of the electrical failure analysis method according to an embodiment of the present application.
In a specific embodiment, as shown in the figure, the wafer is tested first, where the high-frequency test item and the low-frequency test item are the same, then the failed die is classified according to the test result, if the low-frequency test of a certain die fails, then the high-frequency test of this die fails, so when the test result is that the low-frequency test fails, the failed die may be identified as the low-frequency dominant failed die C, and when the test result is that the low-frequency test passes but the high-frequency test fails, the failed die may be identified as the high-frequency dominant failed die B, and it should be noted that fig. 4 is only an example of a failed die classification method, and the present application is not limited to a failed die classification method, and in various embodiments, other suitable classification methods may be adopted.
By classifying the failed grains, the failure reasons of the failed grains can be easily distinguished, and a basis can be provided for the completion of the subsequent implementation steps of the application.
And S22, acquiring a current high-frequency dominant failure weight value.
After each high-frequency dominant failure grain and each low-frequency dominant failure grain are determined, a current high-frequency dominant failure weight value is obtained, and when failure deviation values are calculated later, weights can be added for the high-frequency failure sizes of each structural layer in each failure log of each high-frequency dominant failure grain, so that high-frequency test failure data are highlighted and are not submerged by low-frequency test failure data, and the accuracy of high-frequency test (AC-SCAN) electrical failure analysis is improved.
The application does not limit the acquisition mode of the current high-frequency dominant failure weight value, and in different embodiments, different acquisition methods of the current high-frequency dominant failure weight value can be adopted.
Step S23, obtaining failure deviation values of all the structural layers according to the high-frequency failure sizes of all the structural layers in the failure logs of all the high-frequency dominant failure grains, the low-frequency failure sizes of all the structural layers in the failure logs of all the low-frequency dominant failure grains, the current high-frequency dominant failure weight value and the design sizes of all the structural layers of the wafer.
After the failure logs of each failure grain of the wafer are obtained, and each high-frequency dominant failure grain and each low-frequency dominant failure grain are determined according to the high-frequency test result and the low-frequency test result in each failure log of the failure grain, and the current high-frequency dominant failure weight value is obtained, the failure deviation value of each structural layer can be obtained according to the high-frequency failure size of each structural layer in the failure logs of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer in the failure logs of each low-frequency dominant failure grain, the current high-frequency dominant failure weight value and the design size of each structural layer of the wafer, wherein the structural layer of the wafer is identical to the structural layer of the grain.
Referring to fig. 5, fig. 5 is a schematic diagram of an alternative failure deviation value obtaining flow chart of the electrical failure analysis method according to an embodiment of the present application.
As shown in the figure, the step of obtaining the failure deviation value of each structural layer includes:
And S50, acquiring the failure dimension proportion of each structural layer of the wafer according to the high-frequency failure dimension of each structural layer of each high-frequency dominant failure grain, the low-frequency failure dimension of each structural layer of each low-frequency dominant failure grain and the current high-frequency dominant failure weight value.
In order to obtain the failure size proportion of each structural layer of the wafer, firstly, the failure size proportion of each structural layer of the wafer is obtained according to the high-frequency failure size of each structural layer of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer of each low-frequency dominant failure grain and the current high-frequency dominant failure weight value.
The step of obtaining the failure size of the structural layer of each structural layer of the wafer may specifically include:
Obtaining the sum of high-frequency failure sizes of the same structural layer of each high-frequency dominant failure grain to obtain the high-frequency failure size of each structural layer, and obtaining the sum of low-frequency failure sizes of the same structural layer of each low-frequency dominant failure grain to obtain the low-frequency failure size of each structural layer;
Obtaining the high-frequency failure weight size of each structural layer according to the high-frequency failure size of each structural layer and the current high-frequency dominant failure weight value;
And obtaining the failure size of the structural layer according to the high-frequency failure weight size and the low-frequency failure size of the structural layer of the same structural layer to obtain the failure size of the structural layer of each structural layer.
For clarity of illustration of the steps for obtaining the failure dimension ratios of the respective structural layers of the wafer, the structural layers M1-M3 are illustrated by way of example, wherein the structural layers M1-M3 are merely exemplary, and in various embodiments, other suitable structural layers may be used.
1) And obtaining the sum of the high-frequency failure sizes of the same structural layer of each high-frequency leading failure grain, namely calculating the high-frequency failure size of each structural layer according to the following formula according to the high-frequency failure size of each failure grain in the failure log.
The result obtained by the formula is the high-frequency failure size of the M1 structural layer, wherein SCAN_AC_Main is the failure size of a certain high-frequency dominant failure grain, the high-frequency failure size of the M1 structural layer can be obtained by summing the failure sizes of all the high-frequency dominant failure grains of the M1 structural layer, and it is easy to understand that the high-frequency failure sizes of the M2 and M3 structural layers can be calculated based on the same method.
2) And obtaining the sum of the low-frequency failure sizes of the same structural layer of each low-frequency dominant failure grain, namely calculating the low-frequency failure size of each structural layer according to the low-frequency failure size of each failure grain in the failure log and the following formula.
The result obtained by the formula is the low-frequency failure size of the M1 structural layer, wherein SCAN_DC_Main is the failure size of a certain low-frequency dominant failure grain, the low-frequency failure size of the M1 structural layer can be obtained by summing the failure sizes of all low-frequency dominant failure grains of the M1 structural layer, and it is easy to understand that the low-frequency failure sizes of the M2 and M3 structural layers can be calculated based on the same method.
3) And assuming that the current high-frequency dominant failure weight value is alpha, acquiring the high-frequency failure weight size of each structural layer according to the high-frequency failure size of each structural layer and the current high-frequency dominant failure weight value, namely calculating the high-frequency failure weight size of each structural layer according to the following formula:
the result obtained by the formula is the high-frequency failure weight size of the M1 structural layer, and the high-frequency failure weight sizes of the M2 and M3 structural layers can be calculated based on the same method.
4) According to the high-frequency failure weight size and the low-frequency failure size of the structural layer of the same structural layer, the failure size of the structural layer is obtained, and the failure size of the structural layer of each structural layer is obtained, namely the failure size of the structural layer of each structural layer is calculated according to the following formula:
In the formula, F1 is the failure size of the structural layer of the wafer M1, and the failure sizes F2 and F3 of the structural layers of the wafers M2 and M3 can be calculated.
Therefore, the obtained structure layer failure sizes of the structure layers of the wafer contain the current high-frequency dominant failure weight value, so that the high-frequency failure weight sizes of the structure layers with increased weights can be obtained, and further, the high-frequency test failure data can be highlighted and not submerged by the low-frequency test failure data.
5) Obtaining the failure size of each structural layer of the wafer, and then obtaining the failure size proportion of each structural layer of the wafer according to the failure size of each structural layer, namely calculating the failure size proportion of each structural layer of the wafer according to the following formula:
F1_P=(F1/(F1+F2+F3))*100%
F2_P=(F2/(F1+F2+F3))*100%
F3_P=(F3/(F1+F2+F3))*100%
Therefore, the failure dimension proportion of each structural layer of the wafer is obtained through the failure dimension of each structural layer of the wafer, and a basis is provided for further calculating the failure deviation value of each structural layer.
And S51, obtaining the design size proportion of each structural layer of the wafer according to the design size of each structural layer of the wafer.
Assuming that the design dimensions of the structural layers of the wafers M1-M3 are D1-D3, the ratio of the design dimensions of the respective structural layers is:
D1_P=(D1/(D1+D2+D3))*100%
D2_P=(D2/(D1+D2+D3))*100%
D3_P=(D3/(D1+D2+D3))*100%
Step S52, according to the failure dimension proportion and the design dimension proportion of the same structural layer, obtaining the failure deviation values of the structural layer to obtain the failure deviation values, namely failure deviation values GAP1-GAP3 of the structural layers M1-M3, wherein the failure deviation values are as follows:
GAP1=F1_P-D1_P
GAP2=F2_P-D2_P
GAP3=F3_P-D3_P
Therefore, according to the high-frequency failure size of each structural layer in the failure log of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer in the failure log of each low-frequency dominant failure grain, the current high-frequency dominant failure weight value and the design size of each structural layer of the wafer, the failure deviation value of each structural layer can be finally obtained, and further, the failure condition of each structural layer of the wafer can be further analyzed according to the failure deviation value of each structural layer, so that the required high-quality high-frequency test electrical failure analysis result is obtained.
After obtaining the failure deviation values, step S24 is further executed to determine whether the failure deviation value of at least one of the structural layers satisfies the predetermined deviation threshold, if not, step S25 is executed, and if yes, step S26 is executed.
After obtaining the failure deviation values of the structural layers, judging whether the failure deviation values meet a preset deviation threshold value.
The predetermined deviation threshold may be a predetermined threshold requirement in an actual failure analysis tool, for example, the predetermined deviation threshold is preferably more than 10% when the YE tool in the EDA failure analysis tool is combined with the actual verification.
When the predetermined deviation threshold is met, the maximum failure influence layer can be determined according to the failure deviation value, otherwise, the current high-frequency dominant failure weight value needs to be continuously adjusted, namely, step S25 is executed.
And S25, adjusting the current high-frequency dominant failure weight value according to the failure deviation value and a preset deviation threshold value, and continuously executing the step S23.
And (3) continuously executing the step S23 by adjusting the current high-frequency dominant failure weight value to obtain the high-frequency failure weight sizes of different structural layers, further obtaining the failure sizes of the structural layers of different wafers, and further calculating the failure size proportion of each structural layer.
Specifically, the adjustment of the current high-frequency dominant failure weight value can be adjusted according to the relationship between the failure deviation value and the preset deviation threshold, when the difference between each failure deviation value and the preset deviation threshold is larger, the difference between the adjusted current high-frequency dominant failure weight value and the preliminarily determined current high-frequency dominant failure weight value can be larger, and when the difference between at least one failure deviation value and the preset deviation threshold is smaller, the adjustment amplitude can be smaller.
And S26, acquiring a maximum failure influence layer corresponding to the maximum failure deviation value.
And when the failure deviation value of at least one structural layer meets the preset deviation threshold, acquiring the maximum failure deviation value and the maximum failure influence layer corresponding to the maximum failure deviation value.
It is easy to understand that the most failure affecting layer is the structural layer corresponding to the most failure deviation value, i.e. the structural layer that affects the failure most, so that the structural layer can be further analyzed more precisely.
Thus, after obtaining the failure deviation value of each structural layer, the current high-frequency dominant failure weight value can be adjusted according to the failure deviation value and a preset deviation threshold value until the failure deviation value of at least one structural layer meets the preset deviation threshold value, and the maximum failure influence layer corresponding to the maximum failure deviation value is obtained.
In a specific embodiment, for convenience, the step of obtaining the current high-frequency dominant failure weight value includes:
randomly selecting a high-frequency dominant failure weight value as the current high-frequency dominant failure weight value within a preset high-frequency dominant failure weight value range;
the step of adjusting the current high frequency dominant failure weight value according to the failure deviation value and a predetermined deviation threshold may include:
And when the failure deviation value is smaller than the preset deviation threshold value, increasing the current high-frequency dominant failure weight value.
In a specific embodiment, the predetermined high frequency dominant failure weight value range may be 1-10, and the present application is not limited to the high frequency dominant failure weight value range, and in various embodiments, other suitable high frequency dominant failure weight value ranges may be employed.
For clarity of explanation of the step of adjusting the current high frequency dominant failure weight value, the above example will be described with reference to a range of predetermined high frequency dominant failure weight values from 1 to 10 and a predetermined deviation threshold of 10%.
Firstly, randomly selecting a high-frequency dominant failure weight value as the current high-frequency dominant failure weight value in a preset high-frequency dominant failure weight value range 1-10, then adjusting the current high-frequency dominant failure weight value alpha in F1-F3 according to a calculation formula of a failure deviation value, and increasing the current high-frequency dominant failure weight value when the failure deviation value is smaller than the preset deviation threshold value until the failure deviation value of at least one structural layer meets the preset deviation threshold value, wherein the maximum failure influence layer corresponding to the maximum failure deviation value can be obtained at the moment, and the maximum failure influence layer is the maximum failure influence layer corresponding to the high-frequency test failure.
Therefore, through the adjustment mode of the current high-frequency dominant failure weight value, the weight can be increased for the high-frequency failure size of each structural layer more quickly, so that the high-frequency test failure data can be highlighted more quickly, the maximum failure influence layer corresponding to the high-frequency test failure can be accurately acquired, and further, the high-quality high-frequency test electrical failure analysis result can be acquired according to the acquired maximum failure influence layer.
In another specific embodiment, for convenience, the step of obtaining the current high-frequency dominant failure weight value includes:
Determining a minimum value in a preset high-frequency dominant failure weight value range as the current high-frequency dominant failure weight value;
the step of adjusting the current high frequency dominant failure weight value according to the failure deviation value and a predetermined deviation threshold value comprises:
and when the failure deviation value is smaller than the preset deviation threshold value, increasing the current high-frequency dominant failure weight value according to a preset increment.
Continuing with the example above, the description is given by taking a range of predetermined high frequency dominant failure weights of 1-10 and a predetermined deviation threshold of 10%.
Firstly, selecting a minimum value 1 in a preset high-frequency dominant failure weight value range as the current high-frequency dominant failure weight value in the preset high-frequency dominant failure weight value range 1-10, then adjusting a current high-frequency dominant failure weight value alpha in F1-F3 according to a calculation formula of a failure deviation value, and increasing the current high-frequency dominant failure weight value according to preset increment when the failure deviation value is smaller than the preset deviation threshold value.
In different embodiments, the current high-frequency dominant failure weight value may be increased according to different predetermined increments, for example, in a specific embodiment, the current high-frequency dominant failure weight value may be gradually increased by adopting a predetermined increment of 0.1 until the failure deviation value of one structural layer meets a predetermined deviation threshold, at this time, a maximum failure affecting layer corresponding to the failure deviation value may be obtained, and the maximum failure affecting layer is the maximum failure affecting layer corresponding to the high-frequency test failure.
In another specific embodiment, a larger predetermined increment, for example, greater than 5, may be used to increase the current high frequency dominant failure weight value, where it is possible to obtain failure deviation values for at least one structural layer that already satisfy the predetermined deviation threshold value, due to the larger predetermined increment, and where the largest failure influencing layer corresponding to the largest of the failure deviation values may be obtained.
Therefore, different adjustment methods are adopted, so that the current high-frequency leading failure weight value adjustment method is more flexible and diversified, and if a larger preset increment is adopted to increase the current high-frequency leading failure weight value, the failure deviation value of at least one structural layer can be acquired at one time to meet the preset deviation threshold value, so that the acquisition of the failure deviation value is simpler, more convenient and faster, and the largest failure influence layer corresponding to the largest failure deviation value can be acquired more quickly, thereby acquiring the high-quality high-frequency test electrical failure analysis result according to the acquired largest failure influence layer more quickly.
In summary, in the electrical failure analysis method provided by the embodiment of the present application, each high-frequency dominant failure grain and each low-frequency dominant failure grain are determined according to the failure log of each failure grain of the wafer, so as to distinguish each high-frequency dominant failure data from each low-frequency dominant failure data, then, according to the design size of each structural layer of the wafer and the failure size of each high-frequency dominant failure grain, after the weight adjustment is performed in combination with the failure size of the current high-frequency dominant failure weight value, and the failure size of each low-frequency dominant failure grain that is not performed in combination with the current high-frequency dominant failure weight value, a failure deviation value is obtained, so that the addition of the failure size of each low-frequency dominant failure grain can ensure the data amount required in the electrical failure analysis, and meanwhile, when the failure deviation value is obtained, the weight of the high-frequency failure size is improved through the current high-frequency dominant failure weight value, and then, a predetermined deviation threshold is combined, so that the high-frequency dominant failure data is displayed until the failure deviation value of at least one structural layer meets the predetermined deviation threshold, and then, the failure deviation value of the corresponding to the maximum failure deviation value is obtained, and the maximum failure layer is affected by the maximum dominant failure layer. It can be seen that the electrical failure analysis method provided by the embodiment of the application can ensure enough data quantity by using the low-frequency test dominant failure data, and can also ensure that the high-frequency test dominant failure data is highlighted, but not submerged by the low-frequency test failure data, so that the influence of the high-frequency test failure data is fully displayed, and the accuracy of the electrical failure analysis of the high-frequency test is improved.
The embodiment of the application also provides an electrical failure analysis device, which is described below, and the electrical failure analysis device described below can be regarded as a functional module architecture required by electronic equipment (such as a PC) to respectively implement the electrical failure analysis method provided by the embodiment of the application. The contents of the electrical failure analysis apparatus described below may be referred to in correspondence with the contents of the electrical failure analysis method described above.
In a specific embodiment, referring to fig. 6, fig. 6 is a block diagram of an electrical failure analysis apparatus according to an embodiment of the present application, where the apparatus may include:
A failure log obtaining module 60 adapted to obtain a failure log of each failed die of the wafer;
a failure grain determination module 61 adapted to determine each high frequency dominant failure grain and each low frequency dominant failure grain based on high frequency test results and low frequency test results in the failure log for each of the failure grains;
The high-frequency dominant failure weight value acquisition module 62 is adapted to acquire a current high-frequency dominant failure weight value;
The maximum failure affecting layer obtaining module 63 is adapted to obtain a failure deviation value of each structural layer according to a high-frequency failure size of each structural layer in the failure log of each high-frequency dominant failure grain, a low-frequency failure size of each structural layer in the failure log of each low-frequency dominant failure grain, the current high-frequency dominant failure weight value and a design size of each structural layer of the wafer, and adjust the current high-frequency dominant failure weight value according to the failure deviation value and a predetermined deviation threshold until the failure deviation value of at least one structural layer meets the predetermined deviation threshold, thereby obtaining a maximum failure affecting layer corresponding to the maximum failure deviation value.
In some embodiments, the failure log acquisition module 60 includes:
the first failure log obtaining unit is suitable for testing the wafer by using test items of the wafer test, and obtaining each failure grain and a first failure log of each failure grain, wherein the low-frequency test items in the test items are less than the high-frequency test items;
a replenishing unit adapted to replenish the low frequency test item;
the second failure log obtaining unit is suitable for carrying out a second test on each failure grain according to the low-frequency test items which are supplemented, and obtaining a second failure log of each failure grain;
And the failure log acquisition unit is suitable for acquiring the failure log of each failure grain according to the first failure log and the second failure log.
In further embodiments, the supplementing unit adapted to supplement the low frequency test item comprises:
And supplementing the low-frequency test item according to the high-frequency test item.
In some embodiments, the failure grain determination module 61 is adapted to determine each high frequency dominant failure grain and each low frequency dominant failure grain based on high frequency test results and low frequency test results in the failure log of each of the failure grains, and comprises:
When the low-frequency test result of the failed grain is failure, determining that the failed grain is a low-frequency dominant failed grain;
And when the low-frequency test result of the failed grain is passing but the high-frequency test result of the failed grain is failed, determining that the failed grain is a high-frequency dominant failed grain.
In some embodiments, the maximum failure affecting layer obtaining module 63 is adapted to obtain a failure deviation value of each structural layer according to a high-frequency failure size of each structural layer in the failure log of each high-frequency dominant failure grain, a low-frequency failure size of each structural layer in the failure log of each low-frequency dominant failure grain, the current high-frequency dominant failure weight value, and a design size of each structural layer of the wafer, including:
Acquiring the failure size proportion of each structural layer of the wafer according to the high-frequency failure size of each structural layer of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer of each low-frequency dominant failure grain and the current high-frequency dominant failure weight value;
Obtaining the design size proportion of each structural layer of the wafer according to the design size of each structural layer of the wafer;
and obtaining the failure deviation values of the structural layers according to the failure dimension proportion and the design dimension proportion of the same structural layer, and obtaining the failure deviation values.
In further embodiments, the maximum failure affecting layer obtaining module 63 is adapted to obtain a failure size ratio of each structural layer of the wafer according to a high frequency failure size of each structural layer of each high frequency dominant failure grain, a low frequency failure size of each structural layer of each low frequency dominant failure grain, and a current high frequency dominant failure weight value, and includes:
Obtaining a structural layer failure size of each structural layer of the wafer according to the high-frequency failure size of each structural layer of each high-frequency dominant failure grain, the low-frequency failure size of each structural layer of each low-frequency dominant failure grain and the current high-frequency dominant failure weight value;
and obtaining the failure dimension proportion of each structural layer of the wafer according to the failure dimension of each structural layer.
In further embodiments, the maximum failure affecting layer obtaining module 63 is adapted to obtain a structural layer failure size of each structural layer of the wafer according to a high frequency failure size of each structural layer of each high frequency dominant failure grain, a low frequency failure size of each structural layer of each low frequency dominant failure grain, and a current high frequency dominant failure weight value, and includes:
Obtaining the sum of high-frequency failure sizes of the same structural layer of each high-frequency dominant failure grain to obtain the high-frequency failure size of each structural layer, and obtaining the sum of low-frequency failure sizes of the same structural layer of each low-frequency dominant failure grain to obtain the low-frequency failure size of each structural layer;
Obtaining the high-frequency failure weight size of each structural layer according to the high-frequency failure size of each structural layer and the current high-frequency dominant failure weight value;
And obtaining the failure size of the structural layer according to the high-frequency failure weight size and the low-frequency failure size of the structural layer of the same structural layer to obtain the failure size of the structural layer of each structural layer.
In some embodiments, the high frequency dominant failure weight value acquisition module 62 is adapted to acquire a current high frequency dominant failure weight value, comprising:
randomly selecting a high-frequency dominant failure weight value as the current high-frequency dominant failure weight value within a preset high-frequency dominant failure weight value range;
the maximum failure influence layer obtaining module 63 is adapted to adjust the current high frequency dominant failure weight value according to the failure deviation value and a predetermined deviation threshold, and includes:
And when the failure deviation value is smaller than the preset deviation threshold value, increasing the current high-frequency dominant failure weight value.
In some embodiments, the high frequency dominant failure weight value acquisition module 62 is adapted to acquire a current high frequency dominant failure weight value, comprising:
Determining a minimum value in a preset high-frequency dominant failure weight value range as the current high-frequency dominant failure weight value;
the maximum failure influence layer obtaining module 63 is adapted to adjust the current high frequency dominant failure weight value according to the failure deviation value and a predetermined deviation threshold, and includes:
and when the failure deviation value is smaller than the preset deviation threshold value, increasing the current high-frequency dominant failure weight value according to a preset increment.
It can be seen that, according to the electrical failure analysis device provided by the embodiment of the application, each high-frequency dominant failure grain and each low-frequency dominant failure grain are determined according to the failure log of each failure grain of a wafer, so that the high-frequency dominant failure data and each low-frequency dominant failure data are differentiated, then the design size of each structural layer of the wafer and the failure size of each high-frequency dominant failure grain are combined with the failure size of each low-frequency dominant failure grain which is not weighted after being weighted according to the current high-frequency dominant failure weight value, and the failure deviation value is obtained, so that the addition of the failure size of each low-frequency dominant failure grain can ensure the required data amount in the electrical failure analysis, and meanwhile, when the failure deviation value is obtained, the weight of the high-frequency failure size is improved through the current high-frequency dominant failure weight value, and then the preset deviation threshold is combined, so that the high-frequency dominant failure data are displayed until the failure deviation value of at least one structural layer meets the preset deviation threshold, and then the failure deviation value of the structural layer corresponding to the maximum failure deviation value is obtained, and the structural layer corresponding to the maximum failure deviation value is affected accurately. The electrical failure analysis device provided by the embodiment of the application can ensure enough data quantity by utilizing the low-frequency test dominant failure data, can also ensure that the high-frequency dominant failure data is highlighted, can not be submerged by the low-frequency test failure data, fully displays the influence of the high-frequency test failure data, and improves the accuracy of the electrical failure analysis of the high-frequency test.
The embodiment of the application provides a storage medium which stores a program suitable for electrical failure analysis to realize the electrical failure analysis method.
The embodiment of the application provides electronic equipment, which comprises at least one memory and at least one processor, wherein the memory stores a program, and the processor calls the program to execute the electrical failure analysis method.
According to the storage medium and the electronic equipment provided by the embodiment of the application, each high-frequency dominant failure grain and each low-frequency dominant failure grain are determined according to the failure log of each failure grain of the wafer, so that the high-frequency dominant failure data and each low-frequency dominant failure data are distinguished, then the design size of each structural layer of the wafer and the failure size of each high-frequency dominant failure grain are combined with the failure size of each low-frequency dominant failure grain which is not subjected to weight adjustment, after weight adjustment is carried out according to the design size of each structural layer of the wafer and the failure size of each high-frequency dominant failure grain, the failure deviation value is obtained, therefore, the addition of the failure size of each low-frequency dominant failure grain can ensure the required data amount in the process of electrical failure analysis, and meanwhile, when the failure deviation value is obtained, the weight of the high-frequency dominant failure size is increased through the current high-frequency dominant failure weight value, and then a preset deviation threshold is combined, so that the high-frequency dominant failure data is obtained until the failure deviation value of at least one structural layer meets the preset deviation threshold, and further, the failure deviation value corresponding to the maximum failure deviation value is obtained, and the structural layer corresponding to the maximum failure deviation value is accurately influenced. The storage medium and the electronic equipment provided by the embodiment of the application can ensure enough data quantity by utilizing the low-frequency test dominant failure data, can also ensure that the high-frequency dominant failure data is highlighted, can not be submerged by the low-frequency test failure data, fully displays the influence of the high-frequency test failure data, and improves the accuracy of the high-frequency test electrical failure analysis.
Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the application, and the scope of the application should be assessed accordingly to that of the appended claims.
Claims (18)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111470371.2A CN114281582B (en) | 2021-12-03 | 2021-12-03 | Electrical failure analysis method and related device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111470371.2A CN114281582B (en) | 2021-12-03 | 2021-12-03 | Electrical failure analysis method and related device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114281582A CN114281582A (en) | 2022-04-05 |
| CN114281582B true CN114281582B (en) | 2025-03-04 |
Family
ID=80870849
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111470371.2A Active CN114281582B (en) | 2021-12-03 | 2021-12-03 | Electrical failure analysis method and related device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114281582B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108540244A (en) * | 2018-02-24 | 2018-09-14 | 新华三技术有限公司 | Pre emphasis factor test method, device and communication equipment |
| CN110146798A (en) * | 2019-03-29 | 2019-08-20 | 福建省福联集成电路有限公司 | The automatic analysis method and system of a kind of pair of failure core particles |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200849048A (en) * | 2007-06-13 | 2008-12-16 | Promos Technologies Inc | Method of predicting yield rate of wafer |
| CN110968984B (en) * | 2018-09-28 | 2022-12-09 | 长鑫存储技术有限公司 | Integrated circuit process analysis system and method |
| CN112331251A (en) * | 2020-12-03 | 2021-02-05 | 深圳市博业诚电子有限公司 | Test method of semiconductor memory |
| CN112397410B (en) * | 2020-12-08 | 2021-05-14 | 晶芯成(北京)科技有限公司 | Wafer failure analysis method and system |
-
2021
- 2021-12-03 CN CN202111470371.2A patent/CN114281582B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108540244A (en) * | 2018-02-24 | 2018-09-14 | 新华三技术有限公司 | Pre emphasis factor test method, device and communication equipment |
| CN110146798A (en) * | 2019-03-29 | 2019-08-20 | 福建省福联集成电路有限公司 | The automatic analysis method and system of a kind of pair of failure core particles |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114281582A (en) | 2022-04-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110911298B (en) | Method for determining wafer inspection parameters | |
| US6507800B1 (en) | Method for testing semiconductor wafers | |
| US8606536B2 (en) | Methods and apparatus for hybrid outlier detection | |
| US7904279B2 (en) | Methods and apparatus for data analysis | |
| CN1199931A (en) | Control system and method for semiconductor integrated circuit test process | |
| JP5080526B2 (en) | Method and apparatus for data analysis | |
| CN110596566B (en) | DPAT (dual port automatic test) method for ATE (automatic test equipment) system | |
| CN106294174B (en) | The various dimensions measure and device of testing adequacy | |
| TWI474208B (en) | Method of generating a recipe for a manufacturing tool and system thereof | |
| CN105702595A (en) | Wafer yield judging method and wafer qualification test multivariable detection method | |
| CN107462821A (en) | Remote monitoring method and system for wafer test machine | |
| CN114839518A (en) | A method and system for reordering effective critical area parameter vector sets | |
| WO2024000731A1 (en) | Wafer defect evaluation method and apparatus, memory chip, and readable storage medium | |
| CN114281582B (en) | Electrical failure analysis method and related device | |
| TWI700584B (en) | Testing system and adaptive method of generating testing program | |
| CN117272122B (en) | Wafer anomaly commonality analysis method and device, readable storage medium and terminal | |
| US6442499B1 (en) | Methods and apparatus for statistical process control of test | |
| JP4925200B2 (en) | Semiconductor wafer inspection equipment | |
| JP5207695B2 (en) | Process management method and system using the method | |
| CN116646281A (en) | Abnormal test structure acquisition method, verification method and related device | |
| CN104183511B (en) | A kind of method and crystal grain labeling method of the boundary for determining wafer sort data standard | |
| CN110008120A (en) | A Spectrum-Based Software Fault Location Method | |
| TW202343610A (en) | Wafer inspection method | |
| US6931297B1 (en) | Feature targeted inspection | |
| TWI860159B (en) | Establishing method for prediction model on probe mark defect, prediction system and prevention method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |