CN114264926B - Single-through hole cross-layer electromigration test structure of single-side lead-out voltage test pad - Google Patents
Single-through hole cross-layer electromigration test structure of single-side lead-out voltage test pad Download PDFInfo
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- CN114264926B CN114264926B CN202111426037.7A CN202111426037A CN114264926B CN 114264926 B CN114264926 B CN 114264926B CN 202111426037 A CN202111426037 A CN 202111426037A CN 114264926 B CN114264926 B CN 114264926B
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- 238000012360 testing method Methods 0.000 title claims abstract description 155
- 239000002184 metal Substances 0.000 claims abstract description 58
- 238000001514 detection method Methods 0.000 claims abstract description 35
- 238000001465 metallisation Methods 0.000 claims abstract description 23
- 230000000694 effects Effects 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 25
- 230000008569 process Effects 0.000 claims description 24
- 238000013461 design Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 3
- 238000000605 extraction Methods 0.000 claims description 3
- 238000007689 inspection Methods 0.000 abstract description 3
- 238000005259 measurement Methods 0.000 description 8
- 230000035882 stress Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000005389 semiconductor device fabrication Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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Abstract
The invention relates to the technical field of semiconductors, in particular to a single-via cross-layer type electromigration test structure of a single-side lead-out voltage test pad, which comprises a silicon substrate layer and an insulating medium layer, wherein the insulating medium layer is arranged at the top of the silicon substrate layer, and the structure further comprises: the metallization test line, the interconnection detection line and the through hole are positioned in the insulating medium layer; the metallization test line: for performing a test of the electromigration effect; the interconnection detection line: metal lines for interconnection and inspection; the through hole: for multilevel structured interconnects; large area metallized current test pads and voltage test pads: for current input and voltage reading, respectively. The interconnect detection line includes: test line interconnect segments, metal interconnect lines, and voltage detection lines. The test structure comprises two metal layers and is used for evaluating electromigration reliability problems caused in the manufacturing process of the semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a single-via cross-layer type electromigration test structure of a single-side lead-out voltage test pad.
Background
Electromigration (Electromigration) refers to the phenomenon in which metal ions in a metal conductor material migrate under the action of a large amount of electron motion, and macroscopically shows movement of a metal substance. This effect is particularly pronounced when large currents are passed in the metallic conductor material. After integrated circuits have been successfully commercialized, electromigration is one of the key mechanisms of concern in the field of semiconductor reliability. The test structure (Test Characterization vehicle) is a wafer level or package level structure for evaluating the reliability of semiconductor devices, and aims to find out the reliability defects thereof, take measures to solve, ensure good reliability of the devices during the whole product life, and can measure physical parameters, process parameters, device parameters or circuit parameters.
The design of the test structure for electromigration is generally a metal wire test structure, and the test structure consists of metal wires of each layer and VIA holes connected with each other in different layers in a CMOS (complementary metal oxide semiconductor) process. The electromigration test is simulated by applying electric stress and thermal stress to the test structure, and the reliability of the tested process is evaluated by test data.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a single-via cross-layer type electromigration test structure of a single-side lead-out voltage test pad, which is used for evaluating electromigration reliability problems caused in the manufacturing process of a semiconductor device.
The invention is realized by the following technical scheme:
the utility model provides a single via hole cross-layer type electromigration test structure of unilateral extraction voltage test pad, includes silicon substrate layer and insulating medium layer, the top of silicon substrate layer is equipped with insulating medium layer still includes: the metallization test line, the interconnection detection line, the through hole, the current test pad and the voltage test pad are positioned in the insulating medium layer;
the metallization test line: for performing a test of the electromigration effect;
the interconnection detection line: metal lines for interconnection and inspection;
the through hole: for multilevel structured interconnects;
large area metallized current test pads and voltage test pads: for current input and voltage reading, respectively.
Preferably, the interconnection detection line includes: test line interconnect segments, metal interconnect lines, and voltage detection lines.
Preferably, the test structure comprises two metal layers;
wherein the metallization test line, the metal interconnect line, and the current test pad are located in a first layer; the metallized test line is communicated with the metal interconnection line through the test line interconnection section, the leading-out end of the metal interconnection line is connected with the current test pad, and the current test pad positioned in the insulating medium layer is exposed through an etching process;
the voltage detection line and the voltage test pad are positioned on a second layer; the voltage detection line is communicated with the metal interconnection line through the through hole to form a cross-layer structure, meanwhile, the leading-out end of the voltage detection line is connected with the voltage test pad, and the voltage test pad positioned inside the insulating medium layer is exposed through an etching process.
Preferably, the metallized test line adopts two process line widths, namely a fixed line width and a minimum line width;
the fixed line width is 2 mu m, and the minimum line width complies with the design rule of the product process line; the length of the material is more than or equal to 800 mu m.
Preferably, the test line interconnect segment: providing the length of the test line interconnection section as the distance between the end of the metallized test line and the through hole;
the line width is 2 times of the length of the metallized test line;
The length of the test wire is required to meet the requirement that the ratio of the length of the metallized test wire to the length of the test wire interconnection section at the two ends of the metallized test wire is more than or equal to 95 percent and less than or equal to 8 mu m.
Preferably, the line width of the metal interconnection line is 2 times of the length of the metallization test line, and the length of the metal interconnection line is more than or equal to 80 μm.
Preferably, the line width of the voltage detection line is smaller than or equal to the line width of the metallization test line, and the length of the voltage detection line is larger than or equal to 80 μm.
Preferably, the number of the through holes for connecting the metal interconnection line and the voltage detection line is 1, which is a single-through hole structure.
Preferably, the size of each through hole takes the minimum value allowed by the design rule; and the minimum allowable values of the design rules are taken as the edge wrapping distances between the through holes and the Metal layers Metal 1 and Metal 2 respectively.
Preferably, the length and width of the voltage test pad and the current test pad should be designed to be at least 5 times or more as large as the width of the metal interconnection line.
The beneficial effects of the invention are as follows:
The invention is used for representing the electromigration effect reliability of the metallization test line and the through hole of the tested process. When testing, current needs to be added to two ends of a current source, and the voltage of two ends of a metal wire is measured through an independent voltage loop, so that the resistance change of the metal wire is observed. For evaluating electromigration reliability problems caused during semiconductor device fabrication.
If the voltages between PADs are measured directly, unnecessary parasitic parameters are introduced. The voltage measurement needs to form a current loop, but the current is very small, and the current in the electromigration test is relatively large, and the voltage measurement loop and the current stress loop are combined together, namely, the voltage measurement precision can be influenced by using a large current to measure the voltage. If the current is disconnected and the voltage measurement is performed in the test process, the continuity of the stress is damaged, and the test result is inaccurate. Therefore, the current loop and the voltage loop during the electromigration test should be independent of each other.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic plan view of the present invention;
FIG. 2 is a schematic plan view of a voltage terminal cross-layer structure of the present invention;
FIG. 3 is an enlarged view of a portion of a single via interconnect structure of the present invention;
FIG. 4 is a longitudinal cross-sectional view of the present invention;
FIG. 5 is a second longitudinal cross-sectional view of the present invention;
fig. 6 is a block diagram of an interconnect detection line of the present invention.
In the figure: 1-metallization test lines, 2-interconnect detect lines, 21-test line interconnect segments, 22-metal interconnect lines, 23-voltage detect lines, 3-vias, 4-current test pads, 5-voltage test pads.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Examples
Referring to fig. 1 to 6, the embodiment specifically discloses a technical scheme of a single-via cross-layer electromigration test structure of a single-side lead-out voltage test pad, which includes a silicon substrate layer and an insulating dielectric layer, wherein the top of the silicon substrate layer is provided with the insulating dielectric layer, and the method further includes: the metallization test line 1, the interconnection detection line 2, the through hole 3, the current test pad 4 and the voltage test pad 5 are positioned in the insulating medium layer;
Metallized test line 1: for performing a test of the electromigration effect;
interconnection detection line 2: metal lines for interconnection and inspection;
through hole 3: for multilevel structured interconnects;
large area metallized current test pad 4 and voltage test pad 5: for current input and voltage reading, respectively.
Specifically, the interconnect detection line 2 includes: test line interconnect segments 21, metal interconnect lines 22, and voltage detection lines 23.
Specifically, the test structure comprises two metal layers;
Wherein the metallization test line 1, the metal interconnect line 22 and the current test pad 4 are located in a first layer; the metallized test line 1 is conducted with the metal interconnection line 22 through the test line interconnection section 21, the leading-out end of the metal interconnection line 22 is connected with the current test pad 4, and the current test pad 4 positioned in the insulating medium layer is exposed through an etching process;
the voltage detection line 23 and the voltage test pad 5 are located at the second layer; the voltage detection line 23 is conducted with the metal interconnection line 22 through the through hole 3 to form a cross-layer structure, meanwhile, the leading-out end of the voltage detection line 23 is connected with the voltage test pad 5, and the voltage test pad 5 positioned in the insulating medium layer is exposed through an etching process.
Specifically, the metallized test line 1 adopts two process line widths, namely a fixed line width and a minimum line width;
the fixed line width is 2 mu m, and the minimum line width complies with the design rule of the product process line; the length of the material is more than or equal to 800 mu m.
Specifically, test line interconnect segment 21: the length of the test line interconnect segment 21 is defined as the distance between the end of the metallized test line 1 and the via 3;
The line width is 2 times of the length of the metallized test line 1;
The length of the test wire is required to satisfy the ratio of the length of the metallized test wire 1 to the length of the test wire interconnection section 21 at the two ends of the metallized test wire 1 being more than or equal to 95% and less than or equal to 8 μm.
Specifically, the line width of the metal interconnection line 22 is 2 times the length of the metallization test line 1, and the length thereof is 80 μm or more.
Specifically, the line width of the voltage detection line 23 is equal to or less than the line width of the metallization test line 1, and the length thereof is equal to or more than 80 μm.
Specifically, the number of through holes 3 for connecting the metal interconnection line 22 and the voltage detection line 23 is 1, which is a single through hole 3 structure.
Specifically, the size of the single through hole 3 takes the minimum value allowed by the design rule; the minimum allowable values of design rules are taken as the edge wrapping distances between the through holes 3 and the Metal layers Metal 1 and Metal 2 respectively.
Specifically, the lengths and widths of the voltage test pad 5 and the current test pad 4 should be designed to be at least 5 times as large as the width of the metal interconnect line 22.
The metallized test wire 1 is a long metallized resistor strip designed on an oxide layer, the cross-sectional area of which needs to be kept uniform in order to ensure that the test wire has an approximately uniform temperature before forming a significant void.
The metallized test line 1 generally requires two process linewidths to be designed: a fixed line width of 2 μm and a minimum line width conforming to the design rule of the product process line, the minimum line width being determined by the design rule of the product process line evaluated and verified. It should be noted that the process linewidth should be greater than the average size of the metal grains in the metallization test line 1.
The length of the metallized test wire 1 is more than or equal to 800 mu m, so that the metallized electromigration effect is better represented, the short wire effect and the thermal interference of two current pads are avoided, and the metallized test wire 1 is ensured to have approximately uniform temperature distribution before obvious cavities are formed.
The metallized through hole 3 interconnection structure is a single-ended through hole 3 interconnection structure, and a voltage detection line 23 is led out from the middle position of the through hole 3.
To reduce the effect of the metallization layers of the current test pad 4 and the voltage test pad 5 on the electromigration of the metallization interconnect, the length and width of the voltage test pad 5, the current test pad 4 should be designed to be at least not less than 5 times the width of the metal interconnect 22.
To facilitate the probe contact or bond extraction, it is recommended that the design dimensions of the current test pad 4 and the voltage test pad 5 be 90 μm or more by 90 μm.
The invention is used for representing the electromigration effect reliability of the metallization test line 1 and the through hole 3 of the tested process. When testing, current needs to be added to two ends of a current source, and the voltage of two ends of a metal wire is measured through an independent voltage loop, so that the resistance change of the metal wire is observed. For evaluating electromigration reliability problems caused during semiconductor device fabrication.
If the voltages between PADs are measured directly, unnecessary parasitic parameters are introduced. The voltage measurement needs to form a current loop, but the current is very small, and the current in the electromigration test is relatively large, and the voltage measurement loop and the current stress loop are combined together, namely, the voltage measurement precision can be influenced by using a large current to measure the voltage. If the current is disconnected and the voltage measurement is performed in the test process, the continuity of the stress is damaged, and the test result is inaccurate. Therefore, the current loop and the voltage loop during the electromigration test should be independent of each other.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (3)
1. The utility model provides a single via hole cross-layer type electromigration test structure of unilateral extraction voltage test pad, includes silicon substrate layer and insulating medium layer, the top of silicon substrate layer is equipped with insulating medium layer, its characterized in that still includes: the metallization test line (1), the interconnection detection line (2), the through hole (3), the current test pad (4) and the voltage test pad (5) are positioned in the insulating medium layer;
The metallized test line (1) is used for testing electromigration effect;
the interconnection detection line (2) is used for interconnecting and detecting metal wires;
-said vias (3) for multilevel interconnection;
A large-area metallized current test pad (4) and a voltage test pad (5) for current input and voltage reading, respectively;
The interconnect detection line (2) comprises: a test line interconnect segment (21), a metal interconnect line (22) and a voltage detection line (23);
The test structure comprises two metal layers; wherein the metallization test line (1), the metal interconnect line (22) and the current test pad (4) are located in a first layer; the metallized test line (1) is communicated with the metal interconnection line (22) through the test line interconnection section (21), the leading-out end of the metal interconnection line (22) is connected with the current test pad (4), and the current test pad (4) positioned in the insulating medium layer is exposed through an etching process; the voltage detection line (23) and the voltage test pad (5) are positioned on a second layer; the voltage detection line (23) is communicated with the metal interconnection line (22) through the through hole (3) to form a cross-layer structure, meanwhile, the leading-out end of the voltage detection line (23) is connected with the voltage test pad (5), and the voltage test pad (5) positioned in the insulating medium layer is exposed through an etching process;
The metallization test line (1) adopts two process line widths, namely a fixed line width and a minimum line width; the fixed line width is 2 mu m, the minimum line width complies with the design rule of the product process line, and the process line width is larger than the average size of metal grains in the metallization test line (1); the lengths of the two components are all more than 800 mu m; the metallized test line (1) is a long metallized resistor strip designed on the oxide layer, and the cross section area of the resistor strip needs to be kept uniform;
-said test line interconnect segment (21) having a linewidth of 2 times the length of said metallized test line (1); the length of the test wire is required to meet the requirement that the ratio of the length of the metallized test wire (1) to the length of the test wire interconnection section (21) at the two ends of the metallized test wire (1) is more than or equal to 95 percent and is equal to 8 mu m;
The line width of the metal interconnection line (22) is 2 times of the length of the metallization test line (1), and the length of the metal interconnection line is equal to 80 mu m;
the length and width of the voltage test pad (5) and the current test pad (4) are at least designed to be not less than 5 times of the width of the metal interconnection line (22);
the line width of the voltage detection line (23) is smaller than or equal to the line width of the metallization test line (1), and the length of the voltage detection line is equal to 80 mu m;
When testing, current needs to be added at two ends of a current source, the voltage at two ends of a metal wire is measured through an independent voltage loop, and the resistance change quantity of the metal wire is observed and is used for evaluating electromigration reliability problems caused in the manufacturing process of a semiconductor device.
2. The electromigration test structure of claim 1, wherein: the number of the through holes (3) for connecting the metal interconnection line (22) and the voltage detection line (23) is 1, which is a single through hole (3) structure.
3. The electromigration test structure of claim 2, wherein: the size of each through hole (3) takes the minimum value allowed by design rules; the minimum allowable values of the design rules are taken as the edge wrapping distances between the through holes (3) and the Metal layers Metal 1 and Metal 2 respectively.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2000174085A (en) * | 1998-12-08 | 2000-06-23 | Nec Corp | Semiconductor reliability evaluation device and method |
| US6680484B1 (en) * | 2002-10-22 | 2004-01-20 | Texas Instruments Incorporated | Space efficient interconnect test multi-structure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG30537G (en) * | 1990-03-21 | 1995-09-01 | At & T Corp | Integrated circuit electromigration monitor |
| CN102446900B (en) * | 2010-10-12 | 2014-02-26 | 上海华虹宏力半导体制造有限公司 | Electromigration reliability test structure for multilayer of metal interconnected metal wires |
| CN212540578U (en) * | 2020-06-12 | 2021-02-12 | 长江存储科技有限责任公司 | Test structure |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000174085A (en) * | 1998-12-08 | 2000-06-23 | Nec Corp | Semiconductor reliability evaluation device and method |
| US6680484B1 (en) * | 2002-10-22 | 2004-01-20 | Texas Instruments Incorporated | Space efficient interconnect test multi-structure |
Non-Patent Citations (1)
| Title |
|---|
| Reproducibility of Electromigration Measurements;HARRY A. SCHAFFT, et al.;《IEEE TRANSACTIONS ON ELECTRON DEVICES》;第34卷(第3期);第673-681页 * |
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