CN114256150A - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
- Publication number
- CN114256150A CN114256150A CN202010999928.0A CN202010999928A CN114256150A CN 114256150 A CN114256150 A CN 114256150A CN 202010999928 A CN202010999928 A CN 202010999928A CN 114256150 A CN114256150 A CN 114256150A
- Authority
- CN
- China
- Prior art keywords
- layer
- forming
- dielectric layer
- gate dielectric
- semiconductor structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0144—Manufacturing their gate insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate is provided with a fin part; forming a pseudo gate dielectric layer and an initial pseudo gate layer on the substrate; removing part of the initial pseudo gate layer to form a pseudo gate layer; removing the pseudo gate layer by one or more covering etching treatments until the pseudo gate dielectric layer is completely exposed, wherein the covering etching treatment method comprises the following steps: forming a protective layer on the surface of the exposed pseudo gate dielectric layer; and removing part of the pseudo gate layer by adopting dry etching. Before a part of the pseudo gate layer is removed by a dry etching process, a protective layer is formed on the surface of the pseudo gate dielectric layer exposed by the pseudo gate layer, and the protective layer is superposed on the pseudo gate dielectric layer, so that etching gas of the dry etching process is not easy to simultaneously permeate the protective layer and the pseudo gate dielectric layer to contact with the surface of the fin part, further the damage of the fin part is caused, and the performance of the finally formed semiconductor structure is effectively improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. Transistors are widely used as the most basic semiconductor devices, and the conventional planar transistors have weak control capability on channel current, short channel effect is generated, leakage current is caused, and finally the electrical performance of the semiconductor devices is affected.
In order to overcome the short channel effect of the transistor and suppress the leakage current, the prior art proposes a Fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the Fin FET includes: the semiconductor device comprises a fin part and a dielectric layer, wherein the fin part and the dielectric layer are positioned on the surface of a semiconductor substrate, the dielectric layer covers a part of the side wall of the fin part, and the surface of the dielectric layer is lower than the top of the fin part; the grid electrode structures are positioned on the surface of the dielectric layer, the top of the fin part and the surface of the side wall; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
In order to further reduce the size of a device and improve the density of the device, a high-K metal gate transistor is introduced on the basis of a fin field effect transistor, namely, a high-K dielectric material is used as a gate dielectric layer, and a metal material is used as a gate electrode. The high-K metal gate transistor is formed by adopting a gate last (gate last) process, wherein one gate last process is to form a gate groove after removing a pseudo gate oxide layer and a pseudo gate layer, and then form a gate dielectric layer made of a high-K dielectric material on the surface of the inner wall of the gate groove.
However, the prior art still has a plurality of problems in the process of removing the pseudo gate structure.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which can effectively improve the performance of the finally formed semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate is provided with a plurality of mutually discrete fin parts; forming a pseudo gate dielectric layer and an initial pseudo gate layer on the substrate, wherein the pseudo gate dielectric layer covers partial side wall and top surface of the fin portion, and the initial pseudo gate layer is positioned on the pseudo gate dielectric layer; removing part of the initial pseudo gate layer by adopting a first etching process to form a pseudo gate layer, wherein the top surface of the pseudo gate layer is lower than that of the fin part, and part of the pseudo gate dielectric layer is exposed out of the pseudo gate layer; removing the pseudo gate layer by one or more covering etching treatments until the pseudo gate dielectric layer is completely exposed, wherein the covering etching treatment method comprises the following steps: forming a protective layer on the surface of the exposed pseudo gate dielectric layer; and removing part of the pseudo gate layer by adopting a dry etching process, so that the top surface of the pseudo gate layer is lower than the bottom surface of the protective layer.
Optionally, the material of the protective layer includes: silicon oxide.
Optionally, the density of the protection layer is greater than that of the dummy gate dielectric layer.
Optionally, the method for forming the protective layer on the exposed surface of the dummy gate dielectric layer includes: forming a precursor layer on the surface of the exposed pseudo gate dielectric layer; and carrying out oxidation treatment on the precursor layer to form the protective layer.
Optionally, the method for forming the precursor layer includes: and treating the surface of the exposed pseudo gate dielectric layer by using gas containing a silicon material, so that the gas containing the silicon material is attached to the surface of the exposed pseudo gate dielectric layer to form the precursor layer.
Optionally, the gas containing silicon material comprises: a silane.
Optionally, the oxidation treatment method includes: and carrying out oxygen plasma implantation treatment on the precursor layer.
Optionally, the thickness of the protective layer formed each time is 0.5 nm to 1 nm.
Optionally, before forming the protective layer each time, the method further includes: and forming a suppression layer on the surface of the pseudo gate layer.
Optionally, after forming the protective layer each time and before removing a portion of the dummy gate layer, the method further includes: and removing the inhibiting layer.
Optionally, the material of the inhibition layer includes: acetone, ethanol or propylene glycol.
Optionally, the thickness of the inhibition layer formed each time is 0.5 nm to 1 nm.
Optionally, the first etching process includes: a wet etching process or a dry etching process.
Optionally, the removing of part of the dummy gate layer by using a dry etching process includes: the etching gas comprises CF4HBr and H2(ii) a The gas flow is 150 sccm-300 sccm; the etching time is 50 s-150 s.
Optionally, the height of the dummy gate layer removed each time is 20 to 100 angstroms.
Optionally, the number of times of the covering etching treatment is 5 to 10.
Optionally, after forming the initial dummy gate layer, the method further includes: and forming a side wall on the side wall of the initial pseudo gate layer.
Optionally, after forming the sidewall spacers and before performing the cover etching treatment, the method further includes: forming source-drain doped layers in the substrate on two sides of the initial pseudo gate layer; and forming a dielectric layer on the substrate, wherein the dielectric layer covers the side wall of the side wall.
Optionally, before forming the dummy gate dielectric layer and the initial dummy gate layer, the method further includes: and forming an isolation layer on the substrate, wherein the isolation layer covers part of the side wall of the fin part, and the top surface of the isolation layer is lower than that of the fin part.
Optionally, after the dummy gate dielectric layer is completely exposed, the method further includes: and forming an interface layer on the surfaces of the protective layer and the pseudo gate dielectric layer.
Optionally, the material of the interface layer includes: silicon oxide.
Optionally, after forming the interface layer, the method further includes: and removing the interface layer, the protective layer and the pseudo gate dielectric layer.
Optionally, after removing the interfacial layer, the protective layer, and the dummy gate dielectric layer, the method further includes: forming a gate dielectric layer on the substrate, wherein the gate dielectric layer covers part of the side wall and the top surface of the fin part; and forming a gate electrode layer on the gate dielectric layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the forming method of the technical scheme, the pseudo gate layer is removed by adopting a dry etching process, and the corner position of the pseudo gate layer can be completely removed due to the anisotropic characteristic of the dry etching process, so that the problem of incomplete removal of the pseudo gate layer is avoided.
In addition, before a part of the pseudo gate layer is removed by a dry etching process, a protective layer is formed on the surface of the pseudo gate dielectric layer exposed by the pseudo gate layer, and the protective layer is superposed on the pseudo gate dielectric layer, so that etching gas in the dry etching process is not easy to permeate the protective layer and the pseudo gate dielectric layer to contact with the surface of the fin part at the same time, the fin part is damaged, and the performance of the finally formed semiconductor structure is effectively improved.
Further, the density of the protective layer is greater than that of the pseudo gate dielectric layer. Through forming the protective layer with better density, the protective layer has better compactness, and then can prevent etching gas from permeating to the surface of the fin portion better and causing damage, and the performance of the finally formed semiconductor structure is effectively improved.
Further, before forming the protective layer each time, the method further includes: and forming a suppression layer on the surface of the pseudo gate layer. The inhibiting layer has the effects that on one hand, the inhibiting layer covers the surface of the pseudo gate layer, the protecting layer is prevented from being formed on the surface of the pseudo gate layer while the protecting layer is formed on the surface of the pseudo gate dielectric layer, and further, the process that the protecting layer on the pseudo gate layer needs to be removed before the pseudo gate layer is etched in the follow-up process is avoided; on the other hand, the protective layer is only required to be formed on the surface of the exposed pseudo gate dielectric layer, the formation of the precursor layer on the surface of the precursor layer can be inhibited by the inhibiting layer, and the protective layer cannot be formed on the surface of the inhibiting layer after the oxidation treatment.
Further, the material of the inhibition layer comprises: acetone, ethanol or propylene glycol. The material can effectively avoid the formation of the precursor layer on the surface of the inhibition layer; in addition, the material is in a liquid state, so that the material can be conveniently removed before the pseudo gate layer is etched subsequently.
Further, after the dummy gate dielectric layer is completely exposed, the method further comprises the following steps: and forming an interface layer on the surfaces of the protective layer and the pseudo gate dielectric layer. After multiple times of covering and etching treatment, the thickness of the protective layer formed on the surface of the pseudo gate dielectric layer is uneven, and the thickness of the protective layer is gradually reduced from the top surface of the fin portion to the bottom surface of the fin portion, so that the unevenness of the surface of the protective layer can be reduced through the interface layer, and the removal effect of the protective layer can be improved in the subsequent removal process of the protective layer.
Drawings
FIGS. 1-3 are schematic structural diagrams of a semiconductor structure;
fig. 4 to 27 are schematic structural diagrams of steps of a semiconductor structure forming method according to an embodiment of the invention.
Detailed Description
As described in the background, the prior art still has many problems in removing the dummy gate structure.
Currently, when removing a dummy gate layer (poly) in a dummy gate structure, dry etching or wet etching is generally used. However, in the dry etching process, the etching gas H is not mixed with the etching gas2The concentration is not easy to control when H2At higher concentrations, H2The dummy gate dielectric layer penetrating through the dummy gate structure contacts the top surface of the Fin portion, and the Fin portion (Fin) is easily damaged. In addition, during wet etching, polysilicon material is usually left due to the diffusion characteristics of the etching solution and the generation of hydrogen bubbles, both of which affect the performance of the finally formed semiconductor device.
In order to solve the above problems, a method for forming a semiconductor structure is also provided in the prior art, and will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 having a plurality of fins 101 separated from each other; forming a dummy gate structure on the substrate 100, wherein the dummy gate structure covers part of the side wall and the top surface of the fin portion 101, the dummy gate structure includes a dummy gate dielectric layer 102, a dummy gate layer 103 located on the dummy gate dielectric layer 102, and a side wall 104 located on the side wall of the dummy gate layer 103, and the dummy gate layer 103 includes a first region I and a second region II located on the first region I.
Referring to fig. 2, the second region II of the dummy gate layer 103 is removed by dry etching.
Referring to fig. 3, a wet etching process is used to remove the first region I of the dummy gate layer 103.
In this embodiment, since only the second region II of the gate layer 103 is removed by dry etching, the dry etching time can be shortened, and thus the dry etching H can be reduced2And the etching liquid permeates to the top surface of the fin part 101, so that the etching damage of the dry etching to the fin part 101 is effectively reduced. However, when the wet etching process is used to remove the first region I of the dummy gate layer 103, since the wet etching is an isotropic etching process, at the corner position a of the dummy gate layer 103, an etching solution of the wet etching process hardly completely reacts with the gate layer, so that material residues of the dummy gate layer 103 may also be left.
On the basis, the invention provides a method for forming a semiconductor structure, wherein the dummy gate layer is removed by adopting a dry etching process, and the corner position of the dummy gate layer can be completely removed due to the anisotropic characteristic of the dry etching process, so that the problem of incomplete removal of the dummy gate layer is avoided. In addition, before a part of the pseudo gate layer is removed by a dry etching process, a protective layer is formed on the surface of the pseudo gate dielectric layer exposed by the pseudo gate layer, and the protective layer is superposed on the pseudo gate dielectric layer, so that etching gas in the dry etching process is not easy to permeate the protective layer and the pseudo gate dielectric layer to contact with the surface of the fin part at the same time, the fin part is damaged, and the performance of the finally formed semiconductor structure is effectively improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 27 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, a substrate 200 is provided, and the substrate 200 has a plurality of fins 201 separated from each other.
In this embodiment, the method for forming the substrate 200 and the fin 201 includes: providing an initial substrate (not shown) having a mask layer (not shown) thereon, the mask layer exposing a portion of a top surface of the initial substrate; and etching the initial substrate by taking the mask layer as a mask to form the substrate 200 and the fin part 201 on the substrate 200.
In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium.
In this embodiment, the fin 201 is made of silicon; in other embodiments, the material of the fin portion may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
Referring to fig. 5, an isolation layer 202 is formed on the substrate 200, wherein the isolation layer 202 covers a portion of the sidewall of the fin 201, and a top surface of the isolation layer 202 is lower than a top surface of the fin 201.
In this embodiment, the method for forming the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate 200; and etching to remove part of the initial isolation layer to form the isolation layer 202, wherein the top surface of the isolation layer 202 is lower than that of the fin 201.
The isolation layer 202 is made of an insulating material, and the insulating material comprises silicon oxide or silicon oxynitride; in this embodiment, the material of the isolation layer 202 is silicon oxide.
Referring to fig. 6, after forming the isolation layer 202, a dummy gate dielectric layer 203 and an initial dummy gate layer 204 are formed on the substrate 200, where the dummy gate dielectric layer 203 covers a portion of the sidewall and the top surface of the fin 201, and the initial dummy gate layer 204 is located on the dummy gate dielectric layer 203.
In this embodiment, the dummy gate dielectric layer 203 is made of silicon oxide; in other embodiments, the dummy gate dielectric layer material may also be silicon oxynitride.
In this embodiment, the material of the initial dummy gate layer 204 is polysilicon.
Referring to fig. 7, after the dummy gate dielectric layer 203 and the initial dummy gate layer 204 are formed, a sidewall spacer 205 is formed on a sidewall of the initial dummy gate layer 204.
In this embodiment, the method for forming the sidewall spacers 205 includes: forming a sidewall material layer (not shown) on the sidewalls and the top surface of the initial dummy gate layer 204 and the top surface of the isolation layer 202; and removing the side wall material layers on the top surfaces of the initial pseudo gate layer 203 and the isolation layer 202 to form the side wall 205.
In this embodiment, the sidewall spacers 205 are made of silicon nitride.
Referring to fig. 8 to 10, fig. 8 is a top view of a semiconductor structure, fig. 9 is a schematic cross-sectional view taken along line a-a in fig. 8, fig. 10 is a schematic cross-sectional view taken along line B-B in fig. 8, and after forming the sidewall spacers 205, source-drain doped layers 206 are formed in the substrate 200 at both sides of the initial dummy gate layer 204; forming a dielectric layer 207 on the substrate 200, wherein the dielectric layer 207 covers the side wall of the sidewall spacer 205.
In this embodiment, the method for forming the source-drain doping layer 206 includes: etching the fin portion 201 by using the initial pseudo gate layer 204 and the side walls 205 as masks, and forming a plurality of epitaxial openings (not labeled) in the fin portion 201; and forming the source-drain doping layer 206 in the epitaxial opening.
In this embodiment, the method for forming the dielectric layer 207 includes: forming an initial dielectric layer (not shown) on the substrate 200, wherein the initial dielectric layer covers the initial dummy gate layer 204 and the sidewall spacers 205; and performing planarization treatment on the initial dielectric layer until the top surfaces of the initial pseudo gate layer 204 and the side walls 205 are exposed, so as to form the dielectric layer 207.
In this embodiment, the dielectric layer 207 is made of silicon oxide; in other embodiments, the material of the dielectric layer may also be a low-k dielectric material (referring to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-k dielectric material (referring to a dielectric material with a relative dielectric constant lower than 2.5).
Referring to fig. 11, where the view directions of fig. 11 and fig. 10 are the same, a first etching process is used to remove a portion of the initial dummy gate layer 204, so as to form a dummy gate layer 208, where a top surface of the dummy gate layer 208 is lower than a top surface of the fin 201, and a portion of the dummy gate dielectric layer 203 is exposed by the dummy gate layer 208.
The first etching process comprises the following steps: a wet etching process or a dry etching process. In this embodiment, the first etching process is a dry etching process.
In this embodiment, a part of the initial dummy gate layer 204 is removed first to expose a part of the dummy gate dielectric layer 203, so that a protective layer is formed on the exposed dummy gate dielectric layer 203 in the subsequent process, and thus, in the subsequent process of removing the dummy gate layer 208, etching gas can be prevented from penetrating into the fin portion 201 through the protective layer, and further, damage is caused to the fin portion 201.
After forming the dummy gate layer 208, the method further includes: removing the pseudo gate layer 208 by one or more covering etching processes until the pseudo gate dielectric layer 203 is completely exposed, wherein the covering etching process method comprises the following steps: forming a protective layer on the surface of the exposed pseudo gate dielectric layer 203; and removing part of the dummy gate layer 208 by adopting a dry etching process, so that the top surface of the dummy gate layer 208 is lower than the bottom surface of the protective layer. Please refer to fig. 12 to fig. 16.
Referring to fig. 12, a suppression layer 209 is formed on the surface of the dummy gate layer 208.
In this embodiment, the inhibiting layer 209 functions to cover the surface of the dummy gate layer 208, so as to prevent the protective layer from being formed on the surface of the dummy gate layer 208 while the protective layer is formed on the surface of the subsequent dummy gate dielectric layer 203, thereby avoiding a process of removing the protective layer on the dummy gate layer 208 before the subsequent etching of the dummy gate layer 208; on the other hand, since the protective layer only needs to be formed on the surface of the exposed dummy gate dielectric layer 203, the formation of a subsequent precursor layer on the surface thereof is inhibited by using the inhibiting layer 209, and the protective layer is not formed on the surface of the inhibiting layer 209 after the oxidation treatment.
The material of the inhibition layer 209 includes acetone, ethanol, or propylene glycol; in this embodiment, acetone is used as the material of the suppression layer 209. The material can effectively avoid the precursor layer from being formed on the surface of the inhibition layer 209; in addition, such a material is in a liquid form, which facilitates removal prior to subsequent etching of the dummy gate layer 208.
In this embodiment, the thickness of the inhibiting layer 209 is 0.5 nm to 1 nm. The suppression layer 209 having this thickness range can effectively prevent the formation of the subsequent precursor layer on the dummy gate layer 208.
Referring to fig. 13, a precursor layer 210 is formed on the exposed surface of the dummy gate dielectric layer 203.
The method for forming the precursor layer 210 comprises the following steps: and treating the exposed surface of the dummy gate dielectric layer 203 with a gas containing a silicon material, so that the gas containing the silicon material adheres to the exposed surface of the dummy gate dielectric layer 203 to form the precursor layer 210.
Because the gas containing the silicon material has growth selectivity, the gas can form the precursor layer 210 on the surface of the pseudo gate dielectric layer 203 in an attached manner, but does not form the precursor layer 210 on the surface of the inhibiting layer 209 in an attached manner, so that the protective layer formed by subsequent oxidation is only positioned on the pseudo gate dielectric layer 203.
In this embodiment, the gas comprising the silicon material comprises silane.
Referring to fig. 14, the precursor layer 210 is oxidized to form the protection layer 211.
In this embodiment, the method of oxidation treatment includes: the precursor layer 210 is subjected to a plasma implantation process of oxygen.
In this embodiment, the material of the protection layer 211 includes silicon oxide.
In the present embodiment, the density of the protection layer 211 formed by oxidizing the precursor layer 210 is greater than the density of the dummy gate dielectric layer 203.
By forming the protective layer 211 with better density, the protective layer 211 has better compactness, so that etching gas can be better prevented from permeating into the surface of the fin portion 201 to cause damage, and the performance of the finally formed semiconductor structure is effectively improved.
In the present embodiment, the thickness of the protection layer 211 is 0.5 nm to 1 nm. The protective layer 211 with the thickness within the range can have a good blocking effect on subsequent etching gas.
Referring to fig. 15, after the protective layer 211 is formed, the inhibiting layer 209 is removed.
In this embodiment, the method for removing the inhibiting layer 209 includes: E-Chuck baking and vacuum evaporation processes.
Referring to fig. 16, after removing the inhibiting layer 209, a dry etching process is used to remove a portion of the dummy gate layer 208, so that the top surface of the dummy gate layer 208 is lower than the bottom surface of the protection layer 211.
In this embodiment, a dry etching process is used to remove the dummy gate layer 208, and since the dry etching process has an anisotropic characteristic, it can be ensured that the corner position of the dummy gate layer 208 is also completely removed, so that the problem of incomplete removal of the dummy gate layer 208 does not exist.
In addition, before a part of the dummy gate layer 208 is removed by performing a dry etching process each time, a protective layer 211 is formed on the surface of the dummy gate dielectric layer 203 exposed by the dummy gate layer 208, and the protective layer 211 is superposed on the dummy gate dielectric layer 203, so that etching gas in the dry etching process is not easy to simultaneously permeate the protective layer 211 and the dummy gate dielectric layer 203 to contact with the surface of the fin portion 201, thereby causing damage to the fin portion 201 and effectively improving the performance of a finally formed semiconductor structure.
In this embodiment, the removing of the portion of the dummy gate layer 208 by using the dry etching process includes: the etching gas comprises CF4HBr and H2(ii) a The gas flow is 150 sccm-300 sccm; the etching time is 50 s-150 s.
In the present embodiment, the height of the dummy gate layer 208 is 20 to 100 angstroms each time it is removed. The height direction is a direction perpendicular to the top surface of the substrate 200. When the height of the dummy gate layer 208 is less than 20 angstroms after one-time removal, the required number of times of covering etching treatment is more, and the production efficiency is further reduced; when the height of the dummy gate layer 208 removed at one time is greater than 100 angstroms, the area of the dummy gate dielectric layer 203 exposed on the sidewall of the fin portion 201 is large, and the etching gas easily permeates through the dummy gate dielectric layer 203 on the sidewall of the fin portion 201, so that the sidewall of the fin portion 201 is damaged.
At this time, one covering etching process is completed, and if the dummy gate layer 208 is not completely removed at this time, the next covering etching process needs to be performed until the dummy gate dielectric layer 203 is completely exposed.
For convenience of description, in the present embodiment, the number of times of the blanket etching process is only described in 3 times, and for a specific process, reference is made to fig. 17 to 24, and a description of a related process is described with reference to fig. 12 to 16, which is not repeated herein. In the actual processing process, the number of times of the covering etching processing is 5 to 10.
Referring to fig. 25, after the dummy gate dielectric layer 203 is completely exposed, an interfacial layer 212 is formed on the surface of the protection layer 211 and the dummy gate dielectric layer 203.
After multiple times of covering and etching treatment, the thickness of the protection layer 211 formed on the surface of the pseudo gate dielectric layer 203 is uneven, and the thickness of the protection layer 211 is gradually reduced from the top surface of the fin portion 201 to the bottom surface of the fin portion 201, so that the unevenness of the surface of the protection layer 211 can be reduced through the interface layer 212, and the removal effect of the protection layer 211 can be improved in the subsequent removal process of the protection layer 211.
In this embodiment, the material of the interfacial layer 212 is silicon oxide.
Referring to fig. 26, after the interfacial layer 212 is formed, the interfacial layer 212, the protective layer 211 and the dummy gate dielectric layer 203 are removed.
In this embodiment, the process of removing the interfacial layer 212, the protective layer 211 and the dummy gate dielectric layer 203 adopts a dry etching process; in other embodiments, the process for removing the interfacial layer, the protective layer and the dummy gate dielectric layer may also adopt a wet etching process.
Referring to fig. 27, after removing the interfacial layer 212, the protective layer 211 and the dummy gate dielectric layer 203, a gate dielectric layer 213 is formed on the substrate 200, wherein the gate dielectric layer 213 covers a portion of the sidewall and the top surface of the fin 201; a gate layer 214 is formed on the gate dielectric layer 213.
In this embodiment, a high-k dielectric material (i.e., a dielectric material having a relative dielectric constant lower than 3.9) is used as the material of the gate dielectric layer 213.
The material of the gate layer 214 comprises a metal comprising: tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the material of the gate layer 214 is tungsten.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (23)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a plurality of mutually discrete fin parts;
forming a pseudo gate dielectric layer and an initial pseudo gate layer on the substrate, wherein the pseudo gate dielectric layer covers partial side wall and top surface of the fin portion, and the initial pseudo gate layer is positioned on the pseudo gate dielectric layer;
removing part of the initial pseudo gate layer by adopting a first etching process to form a pseudo gate layer, wherein the top surface of the pseudo gate layer is lower than that of the fin part, and part of the pseudo gate dielectric layer is exposed out of the pseudo gate layer;
removing the pseudo gate layer by one or more covering etching treatments until the pseudo gate dielectric layer is completely exposed, wherein the covering etching treatment method comprises the following steps: forming a protective layer on the surface of the exposed pseudo gate dielectric layer; and removing part of the pseudo gate layer by adopting a dry etching process, so that the top surface of the pseudo gate layer is lower than the bottom surface of the protective layer.
2. The method of forming a semiconductor structure of claim 1, wherein a material of the protective layer comprises: silicon oxide.
3. The method of claim 1, wherein a density of the protective layer is greater than a density of the dummy gate dielectric layer.
4. The method for forming a semiconductor structure of claim 3, wherein the step of forming a protective layer on the exposed surface of the dummy gate dielectric layer comprises: forming a precursor layer on the surface of the exposed pseudo gate dielectric layer; and carrying out oxidation treatment on the precursor layer to form the protective layer.
5. The method of forming a semiconductor structure of claim 4, wherein the method of forming the precursor layer comprises: and treating the surface of the exposed pseudo gate dielectric layer by using gas containing a silicon material, so that the gas containing the silicon material is attached to the surface of the exposed pseudo gate dielectric layer to form the precursor layer.
6. The method of forming a semiconductor structure of claim 5, wherein the gas comprising a silicon material comprises: a silane.
7. The method of forming a semiconductor structure of claim 4, wherein the oxidizing comprises: and carrying out oxygen plasma implantation treatment on the precursor layer.
8. The method of claim 1, wherein the protective layer is formed to a thickness of 0.5 nm to 1 nm each time.
9. The method of forming a semiconductor structure of claim 1, further comprising, prior to each forming of the protective layer: and forming a suppression layer on the surface of the pseudo gate layer.
10. The method of forming a semiconductor structure of claim 9, further comprising, after each forming of the protective layer and before removing a portion of the dummy gate layer: and removing the inhibiting layer.
11. The method of forming a semiconductor structure of claim 9, wherein the inhibiting layer comprises a material comprising: acetone, ethanol or propylene glycol.
12. The method of forming a semiconductor structure according to claim 9, wherein the thickness of the inhibiting layer formed each time is 0.5 nm to 1 nm.
13. The method of forming a semiconductor structure of claim 1, wherein the first etching process comprises: a wet etching process or a dry etching process.
14. The method for forming a semiconductor structure of claim 1, wherein the removing the portion of the dummy gate layer using a dry etching process comprises: the etching gas comprises CF4HBr and H2(ii) a The gas flow is 150 sccm-300 sccm; the etching time is 50 s-150 s.
15. The method of forming a semiconductor structure of claim 1, wherein the dummy gate layer is removed each time to a height of 20 to 100 angstroms.
16. The method of forming a semiconductor structure of claim 1, wherein the blanket etch process is performed between 5 and 10 times.
17. The method of forming a semiconductor structure of claim 1, further comprising, after forming the initial dummy gate layer: and forming a side wall on the side wall of the initial pseudo gate layer.
18. The method for forming a semiconductor structure according to claim 17, further comprising, after forming the sidewalls and before performing the blanket etching process: forming source-drain doped layers in the substrate on two sides of the initial pseudo gate layer; and forming a dielectric layer on the substrate, wherein the dielectric layer covers the side wall of the side wall.
19. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming said dummy gate dielectric layer and said initial dummy gate layer: and forming an isolation layer on the substrate, wherein the isolation layer covers part of the side wall of the fin part, and the top surface of the isolation layer is lower than that of the fin part.
20. The method of forming a semiconductor structure of claim 1, further comprising, after completely exposing the dummy gate dielectric layer: and forming an interface layer on the surfaces of the protective layer and the pseudo gate dielectric layer.
21. The method of forming a semiconductor structure of claim 20, wherein the material of the interfacial layer comprises: silicon oxide.
22. The method of forming a semiconductor structure of claim 20, further comprising, after forming the interfacial layer: and removing the interface layer, the protective layer and the pseudo gate dielectric layer.
23. The method of forming a semiconductor structure of claim 22, further comprising, after removing the interfacial layer, the protective layer, and the dummy gate dielectric layer: forming a gate dielectric layer on the substrate, wherein the gate dielectric layer covers part of the side wall and the top surface of the fin part; and forming a gate electrode layer on the gate dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010999928.0A CN114256150B (en) | 2020-09-21 | 2020-09-21 | Method for forming semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010999928.0A CN114256150B (en) | 2020-09-21 | 2020-09-21 | Method for forming semiconductor structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114256150A true CN114256150A (en) | 2022-03-29 |
| CN114256150B CN114256150B (en) | 2025-04-25 |
Family
ID=80788382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010999928.0A Active CN114256150B (en) | 2020-09-21 | 2020-09-21 | Method for forming semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114256150B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160233164A1 (en) * | 2015-02-10 | 2016-08-11 | Jung-Hun Choi | Integrated circuit device and method of manufacturing the same |
| CN105990140A (en) * | 2015-01-30 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
| CN107039272A (en) * | 2016-02-03 | 2017-08-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming fin transistors |
| CN109300844A (en) * | 2017-07-25 | 2019-02-01 | 中芯国际集成电路制造(上海)有限公司 | Fin transistor and method of forming the same |
-
2020
- 2020-09-21 CN CN202010999928.0A patent/CN114256150B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105990140A (en) * | 2015-01-30 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
| US20160233164A1 (en) * | 2015-02-10 | 2016-08-11 | Jung-Hun Choi | Integrated circuit device and method of manufacturing the same |
| CN107039272A (en) * | 2016-02-03 | 2017-08-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming fin transistors |
| CN109300844A (en) * | 2017-07-25 | 2019-02-01 | 中芯国际集成电路制造(上海)有限公司 | Fin transistor and method of forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114256150B (en) | 2025-04-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10177146B2 (en) | Semiconductor structure with improved punch-through and fabrication method thereof | |
| US11004752B2 (en) | Fin field-effect transistor | |
| US6838326B2 (en) | Semiconductor device, and method for manufacturing the same | |
| EP3282485A1 (en) | Semiconductor device and fabrication method thereof | |
| CN110164767B (en) | Semiconductor device and method of forming the same | |
| CN110364483B (en) | Semiconductor structure and method of forming the same | |
| CN107045981B (en) | Formation method of semiconductor structure | |
| CN112151382B (en) | Semiconductor structure and forming method thereof | |
| CN109003976B (en) | Semiconductor structure and method of forming the same | |
| CN108022881B (en) | Transistor and forming method thereof | |
| CN114256150B (en) | Method for forming semiconductor structure | |
| US10748817B2 (en) | Semiconductor device and fabrication method thereof | |
| CN109285876B (en) | Semiconductor structure and method of forming the same | |
| CN110034187B (en) | Semiconductor structure and forming method thereof | |
| CN113871352A (en) | Method of making a semiconductor structure | |
| CN114203634A (en) | Method of forming a semiconductor structure | |
| CN114497215A (en) | Semiconductor structure and forming method thereof | |
| CN107785264B (en) | Method of forming a semiconductor device | |
| CN107706153B (en) | Method of forming a semiconductor device | |
| CN113764273B (en) | Semiconductor structure and forming method thereof | |
| CN113937163B (en) | Semiconductor device and method of forming the same | |
| CN113745112B (en) | Method for forming semiconductor device | |
| CN111128731A (en) | Semiconductor device and method of forming the same | |
| CN114551596B (en) | Semiconductor structure and method for forming the same | |
| CN113745214B (en) | Semiconductor structures and methods of forming them |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |