CN114236686B - Light emitting/in structure of multilayer multidimensional photon integrated chip and preparation method - Google Patents

Abstract

The present invention discloses a multi-layer multi-dimensional photon integrated chip input/output light structure, including a silicon substrate placed at the bottom, with n layers of photon integrated chips stacked in sequence above the silicon substrate, and the first n-1 stacked photon integrated chips are used to realize n-1 dimensional horizontal interconnection, and the number of dimensions of horizontal interconnection is equal to the number of sides of the photon integrated chip; the structure of each layer of photon integrated chip is the same, from bottom to top, it is a lower cladding, a core layer and an upper cladding, the core layer is integrated with an input and output light optical waveguide structure composed of an input waveguide and an output waveguide, and the input and output light optical waveguide structures of the remaining layers of photon integrated chips except the top layer are respectively oriented in different directions, and the top layer of the photon integrated chip is connected to its input and output light optical waveguide structure through a surface grating set at the top, and the input and output of light is realized after the surface grating is connected to the optical fiber. The present invention can realize the connection between the optical fiber and the photon integrated chip in multiple dimensions, and has excellent performance.

Description

A multi-layer multi-dimensional photon integrated chip light-in/light-out structure and preparation method thereof

Technical Field

The invention relates to a multi-layer multi-dimensional photon integrated chip light input/output structure and a preparation method thereof, belonging to the technical field of integrated photon devices.

Background Art

With the rapid increase in demand for communication capacity, various technologies are being applied to optical communications. Optical communication technology has significant advantages such as ultra-high speed, ultra-large capacity, ultra-long transmission distance and ultra-low crosstalk, and is therefore widely used in telecommunication networks, satellite communications, submarine communications, data centers, wireless base stations and other communication equipment.

The functions of light source, modulation (conversion of electrical signals into optical signals), transmission, control, detection (conversion of optical signals into electrical signals) and other functions required by optical communication systems need to be realized through optical devices and integrated into photonic integrated chips. The emergence of silicon photonic technology can reduce the cost of photonic integrated chips, reduce chip size and increase transmission rate. With the rapid maturity of technology, photonic integrated chips are becoming more and more complex, and thousands of photonic devices can be integrated on a chip. The multi-layer stacking of photonic integrated chips further improves the integration level. Various on-chip optical interconnection devices have begun to be mass-produced and put into various industries. The problem faced at this time is that the existing single-mode optical fiber core diameter is 8-10μm, and the input/output optical path width of the photonic integrated chip is in the nanometer range. The huge size difference has caused great trouble for the connection between optical fiber and on-chip devices. In addition, the multi-layer stacking of photonic integrated chips makes traditional interconnection methods stretched.

This patent proposes a multi-layer and multi-dimensional photon integrated chip light-in/light-out structure and provides a preparation method. This structure can achieve multi-layer and multi-dimensional efficient coupling, has strong scalability and mature technology.

Summary of the invention

In view of some problems existing in the prior art with the above-mentioned technology and material selection, the present invention provides a multi-layer and multi-dimensional photonic integrated chip light input/output structure and a preparation method, which can realize the connection between optical fiber and photonic integrated chip in multiple dimensions, and has simple operation, excellent performance and low processing cost.

The present invention proposes a multi-layer multi-dimensional photon integrated chip input/output light structure, comprising a silicon substrate placed at the bottom, and five layers of photon integrated chips stacked in sequence on the silicon substrate. The structures of the photon integrated chips in each layer are the same, and from bottom to top, they are the lower cladding layer, the core layer and the upper cladding layer. The core layer is integrated with input and output optical waveguides, and the number of the optical waveguide structures can be arbitrarily selected under the condition that the size is satisfied. The optical waveguide structures of the first to fourth layers are oriented in different directions respectively. The fifth layer of photon integrated chip connects the input and output waveguides through the surface grating set on the top thereof, and completes the input and output of light through the grating. The topmost layer of photon integrated chip is vertically coupled by the grating, that is, the grating for coupling light can be placed at any position of the chip. However, the optical fiber can only be aligned with the grating in the vertical direction and has an inclination angle of 8°. The input and output waveguides in the lower four layers of photon integrated chips are interconnected with the optical fiber through a curved waveguide, and the center position of the optical fiber port is consistent with the center of the end face of the connected input and output waveguide in the horizontal direction, and the vertical direction is arbitrary. In the above five-layer photonic integrated chip, the upper cladding layer of the next layer is also the lower cladding layer of the previous layer.

Furthermore, the photonic integrated chip uses silicon and silicon-based oxide, the connecting waveguide uses polymer material, and the optical fiber uses single-mode quartz optical fiber.

Furthermore, the lower cladding layer and the upper cladding layer are both made of silicon dioxide, and the core layer is made of silicon material.

Furthermore, the photonic integrated chip is interconnected with the optical fiber in a four-dimensional coupling manner in the horizontal direction through the input and output optical waveguide structures, and is interconnected in a multi-point coupling manner in the vertical direction.

A method for preparing a multi-layer multi-dimensional photon integrated chip input/output structure comprises the following specific steps:

Step 1, set up the silicon substrate, which is a 5 mm thick silicon wafer on which 3 µm of plasma enhanced chemical vapor deposition (PECVD) SiO ₂ is deposited to provide bottom optical insulation. PECVD Si is deposited on this layer and waveguides are placed into this layer using photolithography. This layer is the bottom (first) layer of the photonic integrated chip and is clad with the core layer using PECVD SiO _2. The cladding process forms ridges above all the silicon. These ridges limit the ability to stack vertical layers, so a chemical mechanical polishing (CMP) tool and KOH and silicon dioxide solution are used to planarize the wafer to the waveguide level. The second deposition of PECVD SiO ₂ creates a vertical gap between the optical layers, which can be used to increase or decrease the coupling between them. Adjusting the gap, and thus coupling by deposition, allows us to have more control than typical lateral coupling, which is determined by the limitations of resist, photolithography, and etching. The second layer of Si is then deposited and patterned in the same way as the first layer and the core layer is clad with PECVD SiO _2. We refer to this layer as the second layer of the photonic integrated chip. In this way, a five-layer photonic integrated chip can be constructed.

Furthermore, due to the limitation that the glue dispensing machine can only dispense glue on the horizontal plane, the photonic integrated chip is fixed by a clamp to prevent the photonic integrated chip from moving when the glue dispensing machine is working. The photonic integrated chip is fixed from a horizontal position to a vertical position, and the optical fiber and the input and output waveguide are connected by the glue dispensing machine.

Furthermore, the optical fiber is tilted 8° in the vertical direction and aligned with the chip grating coupling region.

Furthermore, the curved waveguide is a truncated cone-shaped curved waveguide, which is drawn by a glue dispenser and is symmetrical about a line connecting the centers of the two end faces. One end of the curved waveguide is connected to an optical fiber and the other end is connected to a light input/output waveguide and is symmetrical about a line connecting the centers of the two end faces.

Furthermore, the glue is a UV curing glue, the main component of which is a silicate-based organic-inorganic composite resin, the viscosity is 1,000-10,000 [mPa·s], the curing conditions are 10mW/cm2x2min + 150℃x60min, and the refractive index is 1.52-1.60. The optical fiber is a quartz optical fiber.

The beneficial effects of the present invention are as follows: the multi-layer multi-dimensional photonic integrated chip structure of the present invention realizes the connection between the photonic chip and the optical fiber in multiple dimensions. In the horizontal direction, the optical fiber is connected to the integrated chip through a truncated cone-shaped curved waveguide, which greatly reduces the related loss and crosstalk and increases the flexibility of the integrated photonic device; in the vertical direction, multi-point light output/input is realized; it can be expanded to multi-polarization multi-mode coupling. The preparation process of the present invention is mature and compatible with complementary metal oxide semiconductors. The multi-layer multi-dimensional output/input light structure of the present invention can be expanded to an n-layer n-dimensional output/input light structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic cross-sectional view of the bottom-layer photonic integrated chip of the present invention.

FIG. 2 is a schematic structural diagram of a single-layer photonic integrated chip of the present invention.

FIG. 3 is a schematic diagram of the structure of the lower four-layer photonic integrated chip of the present invention.

FIG. 4 is a schematic structural diagram of a five-layer photonic integrated chip of the present invention.

FIG5 is a schematic diagram of a structure in which a single optical fiber on a single-layer photonic integrated chip of the present invention is connected to a waveguide on the chip through a curved waveguide.

FIG6 is a schematic diagram of a structure in which multiple optical fibers on a single-layer photonic integrated chip of the present invention are connected to a waveguide on the chip via a curved waveguide.

7 is a schematic diagram of the structure of the top-layer photonic integrated chip of the present invention and the connection structure of multiple optical fibers on the lower four-layer photonic integrated chips through curved waveguides and the waveguides on the chip.

FIG8 is a schematic diagram of a structure in which a single optical fiber on a top-layer photonic integrated chip of the present invention is connected to a waveguide on the chip through a grating.

FIG. 9 is a schematic diagram of a structure in which multiple optical fibers on a top-layer photonic integrated chip of the present invention are connected to a waveguide on the chip through a grating.

FIG. 10 is a schematic diagram of a structure in which a five-layer photonic integrated chip of the present invention is interconnected with optical fibers in horizontal and vertical directions.

FIG. 11 is a schematic diagram of the interconnection structure between the seven-layer photonic integrated chip of the present invention and the optical fiber in the horizontal and vertical directions.

DETAILED DESCRIPTION

In order to better understand the technical content of the present invention, specific embodiments are given and described as follows in conjunction with the accompanying drawings.

Example 1

The connection solution provided in this embodiment is implemented in a five-layer stacked photonic integrated chip, realizing four-dimensional coupling interconnection in the horizontal direction and multi-point coupling interconnection in the vertical direction.

The preparation method of this embodiment comprises the following specific steps:

A silicon substrate is set up, which is a 5 mm thick silicon wafer on which 3 µm of plasma enhanced chemical vapor deposition (PECVD) SiO ₂ is deposited to provide bottom optical insulation. PECVD Si is deposited on this layer and waveguides are placed into this layer using photolithography. This layer is the bottommost (first) layer of the photonic integrated chip and is clad with the core layer using PECVD SiO _2. The cladding process forms ridges above all the silicon. These ridges limit the ability to stack vertical layers, so a chemical mechanical polishing (CMP) tool and KOH and silicon dioxide solution are used to planarize the wafer to the waveguide level. A second deposition of PECVD SiO ₂ creates a vertical gap between the optical layers that can be used to increase or decrease the coupling between them. Adjusting the gap, and thus coupling by deposition, allows for more control than typical lateral coupling, which is determined by the limitations of resist, photolithography, and etching. A second layer of Si is then deposited and patterned in the same manner as the first layer and the core layer is clad with PECVD SiO ₂ , and this layer is referred to as the second layer of the photonic integrated chip. Thus, three layers of photonic integrated chips with the same structure as the bottom layer are designed on top of the bottom layer, and the three layers of photonic integrated chips respectively select different directions to expose the input waveguide and the output waveguide. At the same time, a top layer of photonic integrated chips is designed on top of the four layers of photonic integrated chips, and _SiO2 is coated by plasma enhanced chemical vapor deposition on the fourth layer of photonic integrated chips; the top layer of photonic integrated chips connects the input and output waveguides through the surface grating set on its upper surface.

Step 4, in the horizontal direction, by controlling the glue dispenser, a curved waveguide made of adhesive is drawn between the optical fiber and the waveguide, thereby realizing the connection between the optical fiber and the waveguide.

In the multi-layer photonic integrated chip of the above technical solution, the bottom layer of the photonic chip structure is the upper cladding layer 001, the core layer 002, the lower cladding layer 003 and the silicon substrate 004, and the remaining four layers are the upper cladding layer 001, the core layer 002 and the lower cladding layer 003.

In the above technical solution, the horizontally interconnected photonic integrated chip 101 is designed with light input and output waveguides 201, 202, 203, 204, and 205, as shown in FIG2. The remaining horizontally interconnected photonic integrated chips 102, 103, and 104 are also designed with light input and output waveguides. The four layers of waveguides are consistent in structure, but different in the light input and output directions, as shown in FIG3. The spacing of the above light input and output waveguides is consistent with the diameter of the optical fiber. The vertically interconnected photonic integrated chip 105 is designed with light input and output gratings 301 and 302. Since different polarized lights (TE, TM, etc.) are used in practical applications, different lights have different requirements for the grating period. Therefore, the type of input light can be determined in the design stage according to application needs, as shown in FIG4. The grating distribution can be arbitrarily designed as needed. The grating structure is provided by a third party during the tape-out.

The overall multi-layer photonic integrated chip is prepared by complementary metal oxide semiconductor process.

As shown in FIG5 , the optical fiber 501 is interconnected with the photon integrated chip 101 by the curved waveguide 401, and the end face of the optical fiber is parallel to the end face of the photon integrated chip. The center of the optical fiber 501 is consistent with the center of the light input and output waveguide 201 in the horizontal direction. After the center of the waveguide is determined in space, the center of the optical fiber is aligned with the center of the waveguide, and the optical fiber can only move in the vertical direction. In the vertical direction, it can be set arbitrarily as needed (that is, the optical fiber can only move in the y-axis and z-axis, and the center of the optical fiber in the x-axis is consistent with the center of the light input and output waveguide). The curved waveguide is symmetrical with the line connecting the centers of the two end faces, that is, the curved waveguide is only bent in the vertical direction. As shown in FIG6 , optical fibers 502, 503, 504, and 505 are connected to the light input and output waveguides 202, 203, 204, and 205 respectively through curved waveguides 402, 403, 404, and 405, and finally realize the interconnection of five optical fibers with the photon integrated chip. The interconnection of more (fewer) optical fibers with the photon integrated chip can be achieved by increasing (reducing) the number of light input and output waveguides. As shown in Fig. 7, the structure composed of the curved waveguides 401-420 and the optical fibers 501-520 is represented by 601-620 respectively. To prepare the curved waveguide, the chip needs to be placed vertically and fixed with a clamp, and the glue dispenser draws the curved waveguide on the plane where each curved waveguide is located.

As shown in FIG8 , in the vertical direction, the optical fiber 521 is aligned with the grating 301 region at an inclination angle of 8°. The gratings are different according to different light polarization directions and need to be designed as needed. Taking two-point entry and exit as an example, as shown in FIG9 , the optical fibers 521 and 522 are interconnected with the photonic integrated chip 105 by aligning the grating 301 and 302 regions.

As shown in FIG10 , the topmost photonic integrated chip 105 realizes two-point coupling interconnection with optical fibers 521 and 522 in the vertical direction; in the horizontal direction, the photonic integrated chips 101, 102, 103, and 104 realize interconnection with 601-605, 606-610, 611-615, and 616-620, respectively.

Example 2

A seven-layer, seven-dimensional photonic integrated chip access structure is prepared by the same method as in Example 1, and its structure is shown in FIG11 . The designed hexagonal photonic integrated chip realizes six-dimensional optical fiber interconnection in the horizontal direction; in the vertical direction, the coupling structure is consistent with the four-sided photonic integrated chip structure.

In this embodiment, the photonic integrated chip used for horizontal interconnection has six sides, and six stacked photonic integrated chips are required to realize six-dimensional horizontal interconnection. As an extension of this, if the photonic integrated chip needs to realize n-dimensional horizontal coupling, n stacked photonic integrated chips are required to realize n-dimensional horizontal interconnection, and the photonic integrated chip has n (greater than or equal to 3) sides. In the above, the number of dimensions of horizontal interconnection is equal to the number of sides of the photonic integrated chip. For the vertical aspect, no matter how the photonic integrated chip used for the horizontal interconnection direction changes, it will eventually be stacked on top of it for vertical interconnection.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. A person with ordinary knowledge in the technical field to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the claims.

Claims (5)

1. A preparation method of a multilayer multidimensional photon integrated chip input/output structure is characterized by comprising the following steps: the multi-layer multidimensional photon integrated chip light emitting/entering structure comprises a silicon substrate arranged at the bottom, wherein n layers of photon integrated chips are sequentially overlapped above the silicon substrate, and n-1-dimensional horizontal interconnection is realized through the front n-1 stacked photon integrated chips, and the number of the dimensions of the horizontal interconnection is equal to the number of the side surfaces of the photon integrated chips;

The structure of each layer of photon integrated chip is the same, the lower cladding, the core layer and the upper cladding are sequentially arranged from bottom to top, the core layer is integrated with an in-out light waveguide structure formed by an input waveguide and an output waveguide, the in-out light waveguide structures of the other layers of photon integrated chips except the topmost layer face different directions respectively, the topmost layer photon integrated chip is connected with the in-out light waveguide structure through a surface grating arranged at the top, and light input and output are realized after the surface grating is connected with an optical fiber;

The photon integrated chip adopts silicon and silicon-based oxide, the connecting waveguide adopts polymer material, and the optical fiber adopts single-mode quartz optical fiber;

the lower cladding and the upper cladding are both made of silicon dioxide, and the core layer is made of silicon material;

the photon integrated chip is in n-1 dimension coupling interconnection with the optical fiber in the horizontal direction and in multi-point coupling interconnection in the vertical direction through an input optical waveguide structure and an output optical waveguide structure;

The method comprises the following specific steps:

step 1, providing a silicon substrate which is a 5mm thick silicon wafer and on which 3 mu m of plasma enhanced chemical vapor deposition SiO ₂ is deposited to provide bottom optical insulation; designing a bottommost photon integrated chip on a silicon substrate, wherein the bottommost photon integrated chip comprises a lower cladding layer, a core layer and an upper cladding layer, the core layer is obtained by using photoetching, and input and output waveguides are exposed out of the side core layer; coating the core layer by PECVD SiO ₂ to obtain an upper cladding layer;

Planarizing the wafer to a waveguide level using a chemical mechanical polishing CMP tool and KOH and a silicon dioxide solution;

Step 2, depositing and patterning a layer of Si in the same way as the bottommost layer, coating the core layer by PECVD SiO ₂ to obtain an upper cladding layer, and polishing to the waveguide grade; the n-2 layer photonic integrated chip with the same structure as the bottommost layer is designed on the bottommost layer; the n-1 layer photon integrated chip respectively selects different directions to expose the input waveguide and the output waveguide;

Step 3, designing a top-layer photon integrated chip on the n-1 layer photon integrated chip in the previous step, depositing and patterning a layer of Si on the n-1 layer photon integrated chip, and then coating by plasma enhanced chemical vapor deposition SiO ₂; the topmost photonic integrated chip is connected with the input and output waveguides through a surface grating arranged on the upper surface of the topmost photonic integrated chip;

and 4, drawing a curved waveguide formed by an adhesive between the optical fiber and the waveguide by controlling the adhesive dispenser in the horizontal direction, so as to realize the connection of the optical fiber and the waveguide.

2. The method for manufacturing the multi-layer multi-dimensional photonic integrated chip input/output structure according to claim 1, wherein the method comprises the following steps: the photon integrated chip is fixed through the clamp to prevent the photon integrated chip from moving when the dispenser works, the photon integrated chip is horizontally placed and fixed and is converted into vertically placed, and the round table-shaped bent waveguide is manufactured through the dispenser to connect the optical fiber with the input waveguide and the output waveguide.

3. The method for manufacturing the multi-layer multi-dimensional photonic integrated chip input/output structure according to claim 2, wherein: the optical fiber is inclined by 8 degrees in the vertical direction and aligned with the chip grating coupling region.

4. The method for manufacturing the multi-layer multi-dimensional photonic integrated chip input/output structure according to claim 1, wherein the method comprises the following steps: the curved waveguide is a truncated cone-shaped curved waveguide, one end of the curved waveguide is connected with the optical fiber, and the other end of the curved waveguide is connected with the light outgoing/incoming waveguide and is symmetrical by a connecting line in the center of the two end faces.

5. The method for manufacturing the multi-layer multi-dimensional photonic integrated chip input/output structure according to claim 2, wherein: the adhesive is silicate-based organic-inorganic composite resin, the viscosity is 1,000-10,000 [ mPa.s ], the curing condition is 10mW/cm2x2min + 150 ℃ x60min, and the refractive index is 1.52-1.60.