CN114236366B - Chip and test method supporting out-of-order finished product testing - Google Patents
Chip and test method supporting out-of-order finished product testing Download PDFInfo
- Publication number
- CN114236366B CN114236366B CN202111549917.3A CN202111549917A CN114236366B CN 114236366 B CN114236366 B CN 114236366B CN 202111549917 A CN202111549917 A CN 202111549917A CN 114236366 B CN114236366 B CN 114236366B
- Authority
- CN
- China
- Prior art keywords
- data
- circuit module
- finished product
- chip
- main circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012360 testing method Methods 0.000 title claims description 227
- 238000010998 test method Methods 0.000 title description 2
- 238000001514 detection method Methods 0.000 claims description 34
- 101150070189 CIN3 gene Proteins 0.000 claims description 9
- 101150110971 CIN7 gene Proteins 0.000 claims description 9
- 101100286980 Daucus carota INV2 gene Proteins 0.000 claims description 9
- 101100508840 Daucus carota INV3 gene Proteins 0.000 claims description 9
- 101150110298 INV1 gene Proteins 0.000 claims description 9
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 claims description 9
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 claims description 9
- 101001116668 Homo sapiens Prefoldin subunit 3 Proteins 0.000 claims description 4
- 102100024884 Prefoldin subunit 3 Human genes 0.000 claims description 4
- 239000000047 product Substances 0.000 description 107
- 239000012467 final product Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 238000013500 data storage Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 4
- 238000003491 array Methods 0.000 description 3
- 238000013100 final test Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000007405 data analysis Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318522—Test of Sequential circuits
- G01R31/31853—Test of registers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
本发明涉及一种芯片及测试方法，尤其是一种支持乱序成品测试的芯片及测试方法。按照本发明提供的技术方案，所述支持乱序成品测试的芯片，包括芯片主电路模块，还包括至少一个可读写电路模块，所述可读写电路模块与芯片主电路模块适配连接；对芯片主电路模块进行所需的成品测试时，一次或多次成品测试用的成品测试数据写入并锁存在可读写电路模块内，且通过芯片主电路模块的输出端OUT能读取得到可读写电路模块内相应锁存的成品测试数据，以便利用所读取的成品测试数据与当前对芯片主电路模块成品测试时的当前成品测试数据进行所需的测试处理。本发明能有效支持乱序测试，提高测试的效率，降低测试成本，安全可靠。
The present invention relates to a chip and a testing method, in particular to a chip and a testing method that supports out-of-order finished product testing. According to the technical solution provided by the present invention, the chip that supports out-of-order finished product testing includes a chip main circuit module, and also includes at least one readable and writable circuit module, and the readable and writable circuit module is adaptively connected to the chip main circuit module; when the chip main circuit module is subjected to the required finished product test, the finished product test data for one or more finished product tests is written and locked in the readable and writable circuit module, and the finished product test data correspondingly latched in the readable and writable circuit module can be read through the output terminal OUT of the chip main circuit module, so as to use the read finished product test data and the current finished product test data when the chip main circuit module is subjected to the finished product test to perform the required test processing. The present invention can effectively support out-of-order testing, improve the efficiency of testing, reduce testing costs, and be safe and reliable.
Description
Technical Field
The invention relates to a chip and a testing method, in particular to a chip and a testing method supporting out-of-order finished product testing.
Background
Multiple tests are required in the production process of the chip, wherein the main two test nodes are wafer test after wafer production and final test after packaging (also called finished product test). In each test link, multiple tests may be performed under different test conditions provided by different test machines, for example, in order to reduce the waiting time required for changing the test temperature, the tests under different temperature conditions are typically performed by different test machines.
Because the testing conditions can be changed for all the chips on the whole wafer at the same time, and the testing data of different chips can be recorded according to the coordinate positions of the chips determined on the wafer, the connection of the testing results obtained by different testing machines is convenient to establish and the whole data analysis is convenient, and therefore, the difficulty and the cost of the wafer testing are relatively low.
The finished product test is different from the wafer test, the chips are packaged into a disordered independent body, if the data obtained by the respective test of different machines are to be connected, the chips can be tested and transferred among the different test machines in sequence according to the established sequence, so that additional automatic transfer equipment is required and the test time is greatly increased. For characteristic parameters such as the temperature of a chip, comprehensive calculation and comparison analysis are generally required to be carried out on test data of multiple machines, the efficiency of finished product test is extremely low, and the required equipment cost and time cost are extremely high.
In order to improve the efficiency of chip finished product testing and reduce the testing cost, improvements on chips and testing methods are urgently needed to meet the requirement that certain parameters must be tested out of order.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a chip and a testing method for supporting disordered finished product testing, which can effectively support disordered testing, improve testing efficiency, reduce testing cost, and are safe and reliable.
According to the technical scheme provided by the invention, the chip supporting the out-of-order finished product test comprises a chip main circuit module and at least one readable and writable circuit module, wherein the readable and writable circuit module is connected with the chip main circuit module in an adapting way;
When the chip main circuit module is subjected to the required finished product test, the finished product test data for one or more times of finished product test are written into and locked in the readable and writable circuit module, and the corresponding latched finished product test data in the readable and writable circuit module can be read through the output end OUT of the chip main circuit module, so that the read finished product test data and the current finished product test data when the finished product of the chip main circuit module is tested at present are utilized to carry OUT the required test treatment.
And the finished product test data is written into the readable and writable circuit module in series, and the finished product test data written and latched in the readable and writable circuit module is output through serial reading.
The circuit comprises a chip main circuit module, a data reading state switch S1, a chip main circuit module, a chip read state switch S1 and a chip read state switch, wherein one end of the data reading state switch S1 is connected with an output end OUT of the chip main circuit module, the other end of the data reading state switch S1 is grounded, and a control end of the data reading state switch S1 and an enabling end of the chip main circuit module are connected with a read-write circuit output end of the chip main circuit module;
when the data reading output signal output by the reading and writing circuit output end of the readable and writable circuit module enables the data reading state switch S1 to be in a conducting state, the chip main circuit module is simultaneously enabled to be in a closing enabling state by utilizing the data reading output signal.
The read-write circuit module comprises a logic input detection unit, a shift register, a data latch array and a logic operation unit;
The input end of the logic input detection unit is connected with any input port of the chip main circuit module, the shift control output end of the logic input detection unit is connected with the clock end of the shift register, the latch control output end of the logic input detection unit is connected with the data latch control end in the data latch array, the data shift output end of the shift register is adaptively connected with the data latch chip selection signal end of the data latch array and the logic operation chip selection signal end of the logic operation unit, the data latch output end of the data latch array is adaptively connected with the logic operation input end of the logic operation unit, and the output end of the logic operation unit is connected with the control end of the data reading state switch S1 and the enabling end of the chip main circuit module;
The logic input detection unit outputs an effective shift control signal Y1 through a shift control output end or outputs an effective latch control signal Y2 through a latch control output end according to a loaded input signal IN, the effective shift control signal Y1 drives a register chip selection signal output by a shift register data shift output end to shift, and the effective latch control signal Y2 and a corresponding register chip selection signal can be utilized to latch required finished product test sub-data IN a corresponding data latch unit of the data latch array;
When the finished product test data latched in the data latch array is read, the logic operation unit operates the corresponding finished product test sub-data in the data latch array according to the register chip selection signal output by the data shift output end of the shift register and serially reads the data.
The logic input detection unit includes a shift control signal generation section and a latch control signal generation section;
When the shift control signal Y1 is high-level and effective, the shift control signal generating unit includes a PMOS tube PM1, an NMOS tube NM2, and an inverter INV1, where the source of the PMOS tube PM1 is connected to the voltage VDD, the gate of the PMOS tube PM1 is connected to the bias voltage VBP1, the drain of the PMOS tube PM1 is connected to the input of the inverter INV1 and the drain of the NMOS tube NM2, the gate of the NMOS tube NM2 is connected to GND, and the output of the inverter INV1 forms a shift control output, and the source of the NMOS tube NM2 receives an input signal IN, and when the input signal IN is a pulse lower than the GND potential, the shift control output outputs the shift control signal Y1 of high level.
When the latch control signal Y2 is high, the latch control signal generating unit includes a PMOS tube PM2, an NMOS tube NM1, an inverter INV2, and an inverter INV3, where the source terminal of the PMOS tube PM2 receives the input signal IN, the gate terminal of the PMOS tube PM2 receives the voltage VDD, the drain terminal of the PMOS tube PM2 is connected to the drain terminal of the NMOS tube NM1 and the input terminal of the inverter INV2, the gate terminal of the NMOS tube NM1 receives the bias voltage VBN1, the source terminal of the NMOS tube NM1 is grounded, the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3, the output terminal of the inverter INV3 forms a latch control output terminal, and when the input signal IN is a pulse higher than the VDD potential, the latch control output terminal outputs the latch control signal Y2 of high level.
The data latch array comprises a plurality of data latch units which are mutually independent and distributed in an array, the data latch units comprise Fuse wires Fuse, one end of each Fuse wire Fuse is connected with a voltage VDD, and the other end of each Fuse wire Fuse is connected with an NMOS tube NM3, one end of a current source Iread and the input end of an inverter INV 4;
The source end of the NMOS tube NM3 and the grounding end of the current source Iread are connected with GND, the grid end of the NMOS tube NM3 is connected with the output end of the AND gate U1, the input end of the AND gate U1 is connected with the latch control signal Y2 and the register chip selection signal of the shift register, and the output end of the inverter INV4 is connected with the data latch state output end of the data latch unit.
The testing method of the chip supporting the disordered finished product test comprises a chip main circuit module and at least one readable and writable circuit module, wherein the readable and writable circuit module is connected with the chip main circuit module in an adapting way;
When the chip main circuit module is subjected to the required finished product test, the finished product test data for one or more times of finished product test are written into and locked in the readable and writable circuit module, and the corresponding latched finished product test data in the readable and writable circuit module can be read through the output end OUT of the chip main circuit module, so that the read finished product test data and the current finished product test data when the finished product of the chip main circuit module is tested at present are utilized to carry OUT the required test treatment.
The circuit comprises a chip main circuit module, a data reading state switch S1, a chip main circuit module and a data reading state switch S1, wherein one end of the data reading state switch S1 is connected with an output end OUT of the chip main circuit module, the other end of the data reading state switch S1 is grounded, and a control end of the data reading state switch S1 and an enabling end of the chip main circuit module are connected with an output end Y of the chip main circuit module;
when the data reading output signal output by the reading and writing circuit output end Y of the readable and writable circuit module enables the data reading state switch S1 to be in a conducting state, the chip main circuit module is simultaneously enabled to be in a closing enabling state by utilizing the data reading output signal.
The read-write circuit module comprises a logic input detection unit, a shift register, a data latch array and a logic operation unit;
The input end of the logic input detection unit is connected with any input port of the chip main circuit module, the shift control output end of the logic input detection unit is connected with the clock end of the shift register, the latch control output end of the logic input detection unit is connected with the data latch control end in the data latch array, the data shift output end of the shift register is adaptively connected with the data latch chip selection signal end of the data latch array and the logic operation chip selection signal end of the logic operation unit, the data latch output end of the data latch array is adaptively connected with the logic operation input end of the logic operation unit, and the output end of the logic operation unit is connected with the control end of the data reading state switch S1 and the enabling end of the chip main circuit module;
The logic input detection unit outputs an effective shift control signal Y1 through a shift control output end or outputs an effective latch control signal Y2 through a latch control output end according to a loaded input signal IN, the effective shift control signal Y1 drives a register chip selection signal output by a shift register data shift output end to shift, and the effective latch control signal Y2 and a corresponding register chip selection signal can be utilized to latch required finished product test sub-data IN a corresponding data latch unit of the data latch array;
When the finished product test data latched in the data latch array is read, the logic operation unit operates the corresponding finished product test sub-data in the data latch array according to the register chip selection signal output by the data shift output end of the shift register and serially reads the data.
The invention has the advantages that the readable and writable circuit module is connected with the chip main circuit module in an adapting way, the function and the effect of the finished chip are realized by utilizing the chip main circuit module, the readable and writable circuit module can latch the finished product test data once or a plurality of times, and the corresponding latched finished product test data in the readable and writable circuit module can be read through the output end OUT of the chip main circuit module, so that the read finished product test data and the current finished product test data when the finished product of the chip main circuit module is tested at present are utilized to perform the required test treatment, thereby effectively supporting the OUT-of-order test, improving the test efficiency and reducing the test cost.
Drawings
Fig. 1 is a block diagram of the structure of the present invention.
FIG. 2 is a flow chart of a prior art product test.
FIG. 3 is a flow chart of the final product test of the present invention.
Fig. 4 is a schematic circuit diagram of a logic input detection unit according to the present invention.
FIG. 5 is a schematic diagram of signals of the logic input detection unit of the present invention when in operation.
Fig. 6 is a schematic circuit diagram of a data latch unit according to the present invention.
The reference numerals indicate 1-finished chips, 2-chip main circuit modules, 3-readable and writable circuit modules, 4-logic input detection units, 5-shift registers, 6-data latch arrays and 7-logic operation units.
Detailed Description
The invention will be further described with reference to the following specific drawings and examples.
As shown in FIG. 1, in order to effectively support out-of-order testing, improve testing efficiency and reduce testing cost, the finished chip 1 of the invention comprises a chip main circuit module 2 and at least one readable and writable circuit module 3, wherein the readable and writable circuit module 3 is connected with the chip main circuit module 2 in an adapting way;
When the chip main circuit module 2 is subjected to the required finished product test, the finished product test data for one or more times of finished product test are written into and locked in the readable and writable circuit module 3, and the corresponding latched finished product test data in the readable and writable circuit module 3 can be read through the output end OUT of the chip main circuit module 2, so that the read finished product test data and the current finished product test data during the finished product test of the chip main circuit module 2 are used for carrying OUT the required test treatment.
Specifically, the finished chip 1 includes a chip main circuit module 2 and a readable/writable circuit module 3, where the chip main circuit module 2 is used to implement the functions of the finished chip 1, that is, the chip main circuit module 2 may take the form of the existing finished chip 1, and the specific form and function of the chip main circuit module 2 are consistent with those of the existing finished chip, which are well known to those skilled in the art and will not be repeated herein. In the embodiment of the present invention, the readable and writable circuit module 3 is added in the finished chip 1, and in general, the readable and writable circuit module 3 is set to be invisible by technical means commonly used in the technical field, so that the work of the chip main circuit module 2 is not affected, that is, the function and the work of the finished chip 1 are not affected.
In the embodiment of the present invention, when the finished product chip 1 is tested, that is, the main circuit module 2 is tested, the specific type and process of the finished product test are consistent with those of the prior art, and are well known to those skilled in the art, and will not be repeated here. After the readable and writable circuit module 3 is arranged, the readable and writable circuit module 3 is connected with the chip main circuit module 2 in an adapting way, and the readable and writable circuit module 3 has data storage capacity.
As can be seen from the above description, when the chip main circuit module 2 is tested, that is, when the finished chip 1 needs to be tested again by using a new testing machine or changing testing conditions, the type and process of performing multiple finished tests on the chip main circuit module 2 can be selected according to actual needs, which are well known to those skilled in the art and will not be repeated here.
When the main chip circuit module 2 is tested by using a test machine, the finished product test data can be stored in the readable and writable circuit module 3, and the finished product test data of one finished product test or a plurality of finished product test data in a plurality of finished product tests can be stored in the readable and writable circuit module 3 by using the readable and writable circuit module 3. The finished test data can be locked in the readable and writable circuit module 3, namely, the finished test data written in the readable and writable circuit module 3 cannot be lost under the conditions of after test and the like. Namely, when the chip main circuit module 2 is subjected to finished product test, the finished product test data of the finished product test is written into the readable and writable circuit module 3, the quantity of the finished product test data stored in the readable and writable circuit module 3 is related to the storage capacity of the readable and writable circuit module 3 and the actual number of finished product tests of the chip main circuit module 2, if the chip main circuit module 2 is required to be subjected to the finished product test twice, the finished product test data of the first finished product test is stored in the readable and writable circuit module 3 after the first finished product test and the corresponding finished product test data of the second finished product test are stored in the readable and writable circuit module 3 after the chip main circuit module 2 is required to be subjected to the finished product test for three times, and the condition that the finished product test data is locked in the readable and writable circuit module 3 can be configured according to actual selection without redundancy.
In specific implementation, the finished product test data specifically refers to test result data after testing the finished chip 1. For example, the temperature coefficient of the finished chip 1 is tested, first finished test data is obtained at low temperature, then the data is written into the readable and writable circuit module 3 in series, second finished test data is obtained at high temperature, and then the first finished test data in the readable and writable circuit module 3 is read in series, so that the difference value of the test data under two temperature conditions can be calculated. The specific determination of the specific temperature values of the high temperature and the low temperature, the type of the finished chip 1, the specific test requirements, and the like are well known to those skilled in the art, and are not repeated herein.
As shown in fig. 2, a flow chart of the finished product test of the existing finished chip 1 is shown, and in fig. 2, two finished product tests of the finished chip 1 are taken as an example. Specifically, after the first final test, the first final test data needs to be derived. After the second product test, the second product test data and the derived first product test data are subjected to required operations. Therefore, according to the flowchart of fig. 2, the test requirements of the finished chip 1 can be guaranteed only in strict test sequence, otherwise, the operation requirements of the first and second finished test data cannot be realized. In specific implementation, the operation process, such as a difference value of test results of a certain electrical parameter under two test conditions, can determine that the finished chip 1 is a good chip if the difference value is within a certain range, otherwise, the finished chip 1 is a defective product. The specific manner and process of the operation may be selected according to the need, and are well known to those skilled in the art, and will not be described herein.
In the embodiment of the present invention, the final product test data of the first final product test may be written into the readable and writable circuit module 3, so that after the second final product test data, the output terminal OUT of the chip main circuit module 2 can be read to obtain the first final product test data latched correspondingly in the readable and writable circuit module 3, after the required final product test data is obtained by reading, the read final product test data and the current final product test data when the final product test of the chip main circuit module 2 is performed at present are subjected to required test processing, and the specific test processing mode and process are consistent with those of the prior art, which are well known to those skilled in the art and are not repeated herein. As shown in fig. 3, in the flow chart of the invention for performing the finished product test, since the first finished product test data is already stored in the readable and writable circuit module 3, after the first finished product test, the second finished product data obtained by the test and the first finished product data in the readable and writable circuit module 3 are read without storing or transferring in time according to the sequence, after the test condition is replaced or the test machine is replaced, so that the required test operation process can be conveniently realized, thereby effectively supporting the out-of-order test, improving the test efficiency and reducing the test cost.
Further, the finished test data is serially written into the readable and writable circuit module 3, and the finished test data written and latched in the readable and writable circuit module 3 is outputted through serial reading. In the embodiment of the invention, the finished product test data is written into the readable and writable circuit module 3 in a serial mode, and the finished product test data is read out in a serial mode, so that the reliability of data access and reading is improved, and the subsequent operation processing of the finished product test data is satisfied.
Further, the circuit further comprises a data reading state switch S1, wherein one end of the data reading state switch S1 is connected with the output end OUT of the chip main circuit module 2, the other end of the data reading state switch S1 is grounded, and the control end of the data reading state switch S1 and the enabling end of the chip main circuit module 2 are connected with the read-write circuit output end of the readable-write circuit module 3;
When the data reading output signal output by the output end of the reading and writing circuit of the readable and writable circuit module 3 makes the data reading state switch S1 be in a conducting state, the chip main circuit module 2 is simultaneously made to be in a closing enabling state by utilizing the data reading output signal.
Specifically, the data reading status switch S1 may be in a conventional controllable form, such as a MOSFET device, and the specific type may be selected according to needs, which is not described herein. When the data reading state switch S1 is in an on state, a low level can be obtained through the output terminal OUT of the chip main circuit module 2, and when the data reading state switch S1 is in an off state, a certain voltage value between GND to VDD can be obtained through the output terminal OUT of the chip main circuit module 2, wherein the specific condition of the voltage value is related to specific finished product test data. When the data reading state switch S1 is in a conducting state, the chip main circuit module 2 is in a closing enabling state by using the data reading output signal, that is, the output of the chip main circuit module 2 through the output end OUT is closed, so that the influence on the correct reading of the product test data in the readable and writable circuit module 3 is avoided. When the data reading state switch S1 is in an off state, the chip main circuit module 2 is in a normal working state, that is, the corresponding level value obtained by reading through the output terminal OUT of the chip main circuit module 2 is not affected.
Further, the readable and writable circuit module 3 includes a logic input detection unit 4, a shift register 5, a data latch array 6, and a logic operation unit 7;
the input end of the logic input detection unit 4 is connected with any input port of the chip main circuit module 2, the shift control output end of the logic input detection unit 4 is connected with the clock end of the shift register 5, the latch control output end of the logic input detection unit 4 is connected with the data latch control end in the data latch array 6, the data shift output end of the shift register 5 is connected with the data latch chip selection signal end of the data latch array 6 and the logic operation chip selection signal end of the logic operation unit 7 in an adapting way, the data latch output end of the data latch array 6 is connected with the logic operation input end of the logic operation unit 7 in an adapting way, and the output end of the logic operation unit 7 is connected with the control end of the data reading state switch S1 and the enabling end of the chip main circuit module 2;
The logic input detection unit 4 outputs an effective shift control signal Y1 through a shift control output end or an effective latch control signal Y2 through a latch control output end according to a loaded input signal IN, the effective shift control signal Y1 drives a register chip selection signal output by a data shift output end of the shift register 5 to shift, and the effective latch control signal Y2 and a corresponding register chip selection signal can be utilized to latch required finished product test sub-data into a corresponding data latch unit of the data latch array 6;
when the finished test data latched in the data latch array 6 is read, the logic operation unit 7 operates the corresponding finished test sub-data in the data latch array 6 according to the register chip selection signal output by the data shift output end of the shift register 5 and then serially reads the finished test sub-data.
IN the embodiment of the present invention, the logic input detection unit 4 receives the loaded input signal IN, and can input the finished product test data into the readable and writable circuit module 3 through the input signal IN. Specifically, according to the specific condition of the input signal IN, the logic input detection unit 4 can output an effective shift control signal Y1 through the shift control output end or output an effective latch control signal Y2 through the latch control output end, wherein the effective shift control signal Y1 can drive the shift register chip selection signal output by the data shift output end of the shift register 5 to shift, and the required finished product test sub-data can be latched IN the corresponding data latch unit of the data latch array 6 by utilizing the effective latch control signal Y2 and the corresponding register chip selection signal.
The shift register 5 may be in a conventional common form, and the shift register 5 can realize shift of the chip select signal of the N-bit register, where the size of N may be specifically selected according to actual needs, so as to meet the requirement of storing the product test data, which is not described herein. In the initial state, the register chip select signals CS <1:N > outputted by the shift register 5 default to all 0, the register chip select signals CS <1> are 1 and the rest are 0 after the CLK input of the clock terminal is valid for the first time, the register chip select signals CS <2> are 1 and the rest are 0 after the CLK input of the clock terminal is valid again for the shift control signal Y1, and the rest are not described one by one. The specific form and operation of the shift register 5 are consistent with the prior art and are well known to those skilled in the art, and will not be described in detail herein.
The data latch array 6 generally includes at least N data latch units, where the N data latch units are distributed in an array, and the N data latch units are connected to N register chip selection signals of the shift register 5 in a one-to-one correspondence manner, and each data latch unit also receives a latch control signal Y2. For any data latch unit, when the latch control signal Y2 is in an active state and the received register chip select signal is also simultaneously "1", latching of data in the current data latch unit can be achieved.
For the logic operation unit 7, the logic operation unit 7 is connected with the N register chip selection signals of the shift register 5 in a one-to-one correspondence manner and is correspondingly connected with the output ends of the N data latch units, and the output ends of the logic operation unit 7 form the output ends of the read-write circuit. The data latch state of each data latch unit in the data latch array 6 can be read out according to the sequential shift of the N register chip select signals.
As shown in fig. 3 and 4, the logic input detection unit 4 includes a shift control signal generation section and a latch control signal generation section;
When the shift control signal Y1 is high-level and effective, the shift control signal generating unit includes a PMOS tube PM1, an NMOS tube NM2, and an inverter INV1, where the source of the PMOS tube PM1 is connected to the voltage VDD, the gate of the PMOS tube PM1 is connected to the bias voltage VBP1, the drain of the PMOS tube PM1 is connected to the input of the inverter INV1 and the drain of the NMOS tube NM2, the gate of the NMOS tube NM2 is connected to GND, and the output of the inverter INV1 forms a shift control output, and the source of the NMOS tube NM2 receives an input signal IN, and when the input signal IN is a pulse lower than the GND potential, the shift control output outputs the shift control signal Y1 of high level.
Further, when the latch control signal Y2 is valid at a high level, the latch control signal generating unit includes a PMOS tube PM2, an NMOS tube NM1, an inverter INV2, and an inverter INV3, wherein a source terminal of the PMOS tube PM2 receives an input signal IN, a gate terminal of the PMOS tube PM2 receives a voltage VDD, a drain terminal of the PMOS tube PM2 is connected to a drain terminal of the NMOS tube NM1 and an input terminal of the inverter INV2, a gate terminal of the NMOS tube NM1 receives a bias voltage VBN1, a source terminal of the NMOS tube NM1 is grounded, an output terminal of the inverter INV2 is connected to an input terminal of the inverter INV3, and an output terminal of the inverter INV3 forms a latch control output terminal, and when the input signal IN is a pulse higher than the VDD potential, the latch control output terminal outputs the latch control signal Y2 at a high level.
IN the embodiment of the invention, when the potential of the input signal IN is between VDD and GND, the PMOS tube PM1 and the NMOS tube NM1 are conducted, and the shift control signal Y1 and the latch control signal Y2 are both low level. If the input signal IN is a pulse lower than the GND level, the NMOS transistor NM2 is turned on and the turn-on level is higher than that of the PMOS transistor PM1, and the shift control signal Y1 is a high level pulse, i.e. the shift control signal Y1 is IN an active state. If the input signal IN is a pulse higher than the VDD level, the PMOS transistor PM2 is turned on and the conduction degree is higher than that of the NMOS transistor NM1, and the latch control signal Y2 is a high level pulse, and the latch control signal Y2 is IN an active state. The specific magnitudes of the bias voltage VBN1 and the bias voltage VBP1 can be selected according to needs, and are well known in the art, and will not be described herein.
As shown in fig. 6, the data latch array 6 includes a plurality of data latch units that are independent from each other and distributed in an array, where the data latch units include a Fuse, one end of the Fuse is connected to the voltage VDD, and the other end of the Fuse is connected to the NMOS transistor NM3, one end of the current source Iread, and an input end of the inverter INV 4;
The source end of the NMOS tube NM3 and the grounding end of the current source Iread are connected with GND, the grid end of the NMOS tube NM3 is connected with the output end of the AND gate U1, the input end of the AND gate U1 is connected with a latch control signal Y2 and a register chip selection signal of the shift register 5, and the output end of the inverter INV4 is connected with the data latch state output end of the data latch unit.
Specifically, the data latch array 6 includes at least N data latch units, one specific case of which is shown in fig. 6. For the data latch unit in fig. 6, in the initial state, the resistance of the Fuse is very small (in the order of tens of Ω), the voltage drop across the Fuse is very small, and the voltage drop across the Fuse is R fsue ×iread. At this time, the input end of the inverter INV4 is at high potential, and the fuse state of the output end of the inverter INV4 is at low level. The current output by the current source Iread can be selected according to the requirement, and the current source Iread can specifically take the form of the current source Iread commonly used in the prior art, which is well known in the art and will not be described herein. In fig. 6, the CS signal received by the and gate U1 is a register chip select signal corresponding to the shift register 5, and the WRT signal received by the and gate U1 is a latch control signal Y2.
When the register chip select signal CS output by the shift register 5 is "1" (i.e. the data latch unit is selected), and the latch control signal Y2 is in a high-level active state, the and gate U1 outputs a high level, under the effect of the high level output by the and gate U1, the NMOS transistor NM1 is turned on, the Fuse instantaneously flows a large current to change the resistance characteristics of the Fuse, the resistance of the Fuse rises to the mΩ level, the voltage drop R fsue x Iread across the Fuse becomes large, the input end of the inverter INV4 is at a low level, and the output Fuse state is at a high level. The data storage of 1bit is realized through the data latch units, so the data latch array 6 formed by N data latch units can realize the storage of N bit data. In specific implementation, one data latch array 6 is generally used to latch the finished product test data once, and when multiple times of finished product test data are needed to be latched, multiple data latch arrays 6 may be provided, and the manner of implementing multiple times of finished product test data latching by using multiple data latch arrays 6 is well known in the art and is not repeated herein.
IN the implementation, according to the specific condition of the finished product test data, the specific level change of the corresponding input signal IN can be determined, that is, for a determined finished product test data, the input signal IN corresponding to the finished product test data can be determined, and according to the determined input signal, the finished product test data of N bits is obtained IN the data latch array 6, and the specific corresponding condition of the finished product test data and the input signal IN is well known IN the art, so that the finished product test data can be completely written into the data latch array 6, which is not repeated herein.
IN the implementation, along with the continuous loading of the input signal IN, the required effective shift control signal Y1 and latch control signal Y2 can be obtained, so that different data latch units are respectively selected under the action of the shift register 5, and the finished product test sub-data can be latched IN the corresponding data latch units of the data latch array 6. The required finished product test data can be formed by the N bit finished product test sub-data. Of course, the data latch unit may also have other latch forms, and may specifically be selected according to actual needs, which will not be described herein.
When the test device specifically works, after primary finished product test data is written into the data latch array 6 in the mode, the whole finished chip 1 is transferred to a new test machine or new test conditions are changed, the whole finished chip 1 is powered on again, all register chip selection signals of the shift register 5 are reset to zero again, data stored in the data latch array 6 cannot be lost, namely, the data storage signal Q of the output end of the written data latch unit through the inverter INV4 in the data latch unit is 1, and the data storage signal Q of the output end of the unwritten data latch unit through the inverter INV4 in the data latch unit is 0.
The logic input detection unit 4 is used for triggering and outputting an effective shift control signal Y1 again so as to drive the register chip selection signals of the shift register 5 to shift in sequence, and the logic operation unit 7 carries out operation according to bits according to N register chip selection signals CS <1:N > and data storage signals Q <1:N > respectively output by the N data latch units to obtain a logic operation output value Y, wherein the logic operation output value Y is specifically:
Y=CS<1>·Q<1>+CS<2>·Q<2>+...+CS<N>·Q<N>
In the above logical operation output value Y, CS <1> is a chip select signal value of the first bit of the shift register 5, Q <1> is a data storage signal Q value corresponding to the data latch unit of the first bit in the data latch array 6, and the rest of the cases are not described in detail herein.
As can be seen from the expression of the logical operation output value Y described above, the logical operation output value Y is a high potential 1 if and only if the data latch unit selected by the chip has been programmed. When the logic operation output value Y is a high potential "1", the enabling terminal of the chip main circuit module 2 is driven by the logic operation output value Y to enter a closed state, the data reading state switch S1 is turned on, and the output terminal OUT of the chip main circuit module 2 obtains a 0 potential. If the data latch unit selected by the register chip select signal is not programmed, the logic operation output value Y is low level 0, and the output end OUT of the chip main circuit module 2 is controlled by the chip main circuit module 2, namely, a certain determined voltage value between GND and VDD.
With the continuous shift of N register chip selection signals of the shift register 5, the output of the finished test sub-data latched in all the data latch units in the data latch array 6 can be realized, namely the serial reading of the finished test data stored in the data latch array 6 is realized.
In summary, the method for testing the chip supporting the out-of-order finished product test comprises a chip main circuit module 2 and at least one readable and writable circuit module 3, wherein the readable and writable circuit module 3 is adaptively connected with the chip main circuit module 2;
When the chip main circuit module 2 is subjected to the required finished product test, the finished product test data for one or more times of finished product test are written into and locked in the readable and writable circuit module 3, and the corresponding latched finished product test data in the readable and writable circuit module 3 can be read through the output end OUT of the chip main circuit module 2, so that the read finished product test data and the current finished product test data during the finished product test of the chip main circuit module 2 are used for carrying OUT the required test treatment.
In the specific implementation, the above description is referred to for the matching situation of the chip main circuit module 2 and the readable and writable circuit module 3, and the testing method for implementing the out-of-order finished product test of the chip main circuit module 2 by using the readable and writable circuit module 3, which is not repeated herein.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111549917.3A CN114236366B (en) | 2021-12-17 | 2021-12-17 | Chip and test method supporting out-of-order finished product testing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111549917.3A CN114236366B (en) | 2021-12-17 | 2021-12-17 | Chip and test method supporting out-of-order finished product testing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114236366A CN114236366A (en) | 2022-03-25 |
| CN114236366B true CN114236366B (en) | 2025-03-14 |
Family
ID=80758020
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111549917.3A Active CN114236366B (en) | 2021-12-17 | 2021-12-17 | Chip and test method supporting out-of-order finished product testing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114236366B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115902595B (en) * | 2023-02-20 | 2023-07-14 | 之江实验室 | A chip testing system and chip testing method |
| CN116155244B (en) * | 2023-04-18 | 2023-07-07 | 至讯创新科技(无锡)有限公司 | Chip multi-state identification circuit and method based on external bonding pad |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN216485391U (en) * | 2021-12-17 | 2022-05-10 | 江苏润石科技有限公司 | Chip supporting out-of-order finished product test |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5495486A (en) * | 1992-08-11 | 1996-02-27 | Crosscheck Technology, Inc. | Method and apparatus for testing integrated circuits |
| JP2004110935A (en) * | 2002-09-18 | 2004-04-08 | Renesas Technology Corp | Semiconductor integrated circuit device and test method therefor |
| US9310426B2 (en) * | 2012-09-25 | 2016-04-12 | Globalfoundries Inc. | On-going reliability monitoring of integrated circuit chips in the field |
| CN110967612A (en) * | 2018-09-28 | 2020-04-07 | 长鑫存储技术有限公司 | Chip testing method, apparatus, equipment and system |
| CN110365530A (en) * | 2019-07-11 | 2019-10-22 | 电子科技大学 | A network-independent test token-passing network |
| CN211180829U (en) * | 2019-10-15 | 2020-08-04 | 上海华虹集成电路有限责任公司 | Test card reader |
-
2021
- 2021-12-17 CN CN202111549917.3A patent/CN114236366B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN216485391U (en) * | 2021-12-17 | 2022-05-10 | 江苏润石科技有限公司 | Chip supporting out-of-order finished product test |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114236366A (en) | 2022-03-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101861027B1 (en) | Integrated circuit defect detection and repair | |
| JP4624516B2 (en) | Fuse detection circuit and integrated circuit memory thereof | |
| KR101445889B1 (en) | Circuits and methods for testing multi-device systems | |
| US7251756B2 (en) | Method and apparatus for increasing fuse programming yield through preferred use of duplicate data | |
| US9666307B1 (en) | Apparatuses and methods for flexible fuse transmission | |
| US7895028B2 (en) | Structure for increasing fuse programming yield | |
| JP2525945B2 (en) | Memory checkerboard self-test apparatus and method | |
| US20050138513A1 (en) | Multiple on-chip test runs and repairs for memories | |
| CN114236366B (en) | Chip and test method supporting out-of-order finished product testing | |
| US20130326295A1 (en) | Semiconductor memory device including self-contained test unit and test method thereof | |
| JPH04212796A (en) | Serial memory capable of permitting defect | |
| JP2008310955A (en) | Method for preventing consumption of time to program address in defective column | |
| JP2007179733A (en) | Coded cell of non-volatile ferroelectric memory device and driving method thereof | |
| CN216485391U (en) | Chip supporting out-of-order finished product test | |
| US10325669B2 (en) | Error information storage circuit and semiconductor apparatus including the same | |
| CN1637953B (en) | Semiconductor memory device having advanced test mode and test method | |
| JPH0745096A (en) | Semiconductor memory with bit error correcting function | |
| CN101563675B (en) | A new implementation of column redundancy for a flash memory with a high write parallelism | |
| US7461306B2 (en) | Output data compression scheme using tri-state | |
| CN102543171A (en) | Phase change memory with redundant circuit and redundancy method for phase change memory | |
| US7064571B2 (en) | Multiple-select multiplexer circuit, semiconductor memory device including a multiplexer circuit and method of testing the semiconductor memory device | |
| JP2008299993A (en) | Semiconductor storage device | |
| KR102604620B1 (en) | Serializer and memory device including the same | |
| JP2011048879A (en) | Semiconductor device | |
| CN114388048A (en) | Repair circuits and memories |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |