CN102543171A - Phase change memory with redundant circuit and redundancy method for phase change memory - Google Patents

Abstract

The invention discloses a phase change memory with redundant circuits, including P redundant rows or Q redundant columns, information storage circuits, row or column switch selection circuits; each row or column control line is connected with P+1 row switch or Q+1 column switch; the 0th row or column switch is connected in series with the row or column control line; one end of the 1st to Pth row switch or the 1st to Qth column switch is connected to the Row or column control line, the other end is connected to the next 1 to P row or Q column control line in turn; each row or column switch corresponds to an information storage circuit; the row or column switch selection circuit is connected to all information storage circuits; all information The storage circuit is connected to the writing circuit; when a certain row or column of the storage array is tested to be defective, the switch on or off information is stored in the information storage circuit, and the corresponding row switch or column switch is controlled to realize the use of non-defective row or column switches. Columns quickly replace defective rows or columns. The invention also discloses a method for realizing redundancy of the phase change memory.

Description

A phase-change memory with redundant circuits and a method for realizing redundancy thereof

technical field

The invention relates to a phase-change memory, in particular to a phase-change memory with redundant circuits and a method for realizing redundancy.

Background technique

Phase-change memory is a memory based on phase-change materials. By applying a long-term and medium-intensity electric pulse to the phase-change material, the phase-change material can be converted from an amorphous state to a crystalline state. This process is called Set process. Since the crystalline state has a low resistance value, it is generally defined as data "1". By applying a high-intensity but short-acting electric pulse to the phase-change material, the phase-change material can be converted from a crystalline state to an amorphous state, and this process is called a reset process. The amorphous state has a high resistance value, which is generally defined as data "0".

Considering the data retention characteristics of phase change memory, that is, since the amorphous state can be converted into a crystalline state through the spontaneous crystallization process of long-term thermal activation crystallization, the normal state of the phase change material is the crystalline state (that is, data "1"), That is, the stored data "0" may spontaneously convert to data "1" after a long period of time. Therefore, it is necessary to pay attention to the authenticity of the data "1".

Existing phase-change memories include write circuits and storage arrays. When redundancy is achieved, some rows or columns in the storage array are used as redundant rows or columns, and redundant rows or columns are used to replace storage A defective row or column in an array; the redundant row used to store replacement information for a specific row or column is called an information row. Generally, the method is to store the address in the information line by the writing circuit. When the phase change memory is to be read and written, the address of the storage unit to be read and written is first compared with the address stored in the information line to determine Whether the storage unit needs to be replaced. This results in a longer reading and writing time, which affects the storage speed of the memory.

Contents of the invention

In view of this, the main purpose of the present invention is to provide a phase-change memory with redundant circuits and a method for realizing redundancy thereof, so as to increase the read-write speed of the phase-change memory.

According to the first aspect of the above object, the present invention provides a phase change memory with redundant circuits, including a write circuit and a storage array, and also includes P redundant rows or Q redundant columns, multiple information storage circuit, row or column switch selection circuit.

The P redundant rows or Q redundant columns are arranged continuously with the rows or columns of the storage array.

Each row control line of the memory array is connected with P+1 row switches or each column control line is connected with Q+1 column switches; the 0th row switch or column switch is connected in series with the row or column control line ; One end of the 1st to Pth row switch or the 1st to Qth column switch is connected to the row or column control line, and the other end is connected to the next 1 to P row or 1 to Q column control line of the row or column in turn on-line.

Each row switch or each column switch is correspondingly connected to an information storage circuit; the row or column switch selection circuit is connected to all the information storage circuits; and the all information storage circuits are connected to the writing circuit.

When it is tested that a certain row or column of the memory array is defective, the row or column switch selection circuit is first used to select the currently closed row switch or column switch for the defective row or column and all rows or columns after the defective row or column For the corresponding information storage circuit, the write circuit stores the row or column switch off information in the selected information storage circuit, and the information storage circuit outputs a switch control signal to turn off the corresponding row switch or column switch; or column switch selection circuit, for a defective row or column and all rows or columns after the defective row or column, select an information storage circuit corresponding to a row switch or column switch with the same serial number connected to a non-defective row or column, The write circuit stores the turn-on information of the row or column switch in the selected information storage circuit, and the information storage circuit outputs a switch control signal to turn on the corresponding row switch or column switch.

According to the second aspect of the above-mentioned purpose, the present invention provides a method for realizing redundancy of a phase-change memory, which adopts the above-mentioned phase-change memory of the claim; when a certain row or column of the memory array is tested to be defective, perform the following steps:

A. Through the row or column switch selection circuit, for the defective row or column and all rows or columns after the defective row or column, select the information storage circuit corresponding to the currently closed row switch or column switch, and the write circuit selects Store row or column switch off information in the information storage circuit, and the information storage circuit outputs a switch control signal to turn off the corresponding row switch or column switch;

B. Through the row or column switch selection circuit, for the defective row or column and all rows or columns after the defective row or column, select a row switch or column switch corresponding to the row switch or column switch of the same serial number connected to the non-defective row or column In the information storage circuit, the write circuit stores the turn-on information of the row or column switch in the selected information storage circuit, and the information storage circuit outputs a switch control signal to turn on the corresponding row switch or column switch.

It can be seen from the above-mentioned technical scheme that the phase-change memory with redundant circuits and the method for realizing redundancy thereof of the present invention directly store the information of these rows or columns when defective rows or columns are found during testing. into a phase change material so that the information can be preserved when the power is turned off. During normal operation, the on-off of the corresponding switch is controlled by reading the information in the phase-change material, and the defective row or column is directly replaced by the corresponding redundant row or column in the circuit. In this way, it is not necessary to compare addresses every time when reading and writing, which improves the reading and writing speed and saves the comparison circuit.

Description of drawings

Fig. 1 is the default state (row replacement) of phase-change memory in a preferred embodiment of the present invention;

Fig. 2 is the state when a certain row of the phase change memory shown in Fig. 1 needs to be replaced;

Fig. 3 is the structure of an information storage circuit in the phase change memory shown in Fig. 1 and its connection diagram with logic circuit and writing circuit;

Fig. 4a is a working state of the circuit shown in Fig. 3 (writing "0" to the phase-change material 35);

Fig. 4b is another working state of the circuit shown in Fig. 3 (writing "1" to the phase change material 36);

Fig. 5 is the default state (column replacement) of the phase change memory of another preferred embodiment of the present invention;

FIG. 6 is a state when a column of the phase change memory shown in FIG. 5 needs to be replaced.

Detailed ways

The phase change memory with redundant circuits and the method for realizing redundancy of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

The phase-change memory with redundant circuits and the method for realizing redundancy of the present invention can be realized by adding redundant rows or adding redundant columns. Examples are given below to describe in detail.

first preferred embodiment

This embodiment is realized by adding redundant rows. The phase change memory of this embodiment is the same as the phase change memory of the prior art in that they all have a write circuit, a storage array and P redundant rows. It includes multiple information storage circuits and a row switch selection circuit.

The P redundant rows in this embodiment are arranged continuously with the storage rows of the storage array. Each row control line of the storage array is connected with P+1 row switches. Wherein, the 0th row switch is connected in series with the row control line, one end of the 1st to P row switches is connected to the row control line, and the other end is sequentially connected to the next 1 to P row control lines of the row. Wherein, each row switch is correspondingly connected to an information storage circuit. The row switch selection circuit is connected with all the information storage circuits, and all the information storage circuits are connected with the writing circuit.

When it is tested that a certain row of the memory array is defective, the row switch selection circuit is first used to select the information storage circuit corresponding to the currently closed row switch for the defective row and all rows after the defective row, and the write circuit is selected. The row switch shutdown information is stored in the information storage circuit, and the information storage circuit outputs a switch control signal to turn off the corresponding row switch; then through the row switch selection circuit, for the defective row and all rows or columns after the defective row , selecting an information storage circuit corresponding to a row switch with the same serial number connected to a non-defective row, storing the conduction information of the row switch in the selected information storage circuit by the write circuit, and the information storage circuit outputs a switch control signal, Turn on the corresponding row switch.

FIG. 1 shows the connection relationship between row switches, storage arrays and redundant rows in the phase change memory of this embodiment, and the row switches in FIG. 1 are in a default state.

As shown in FIG. 1 , the storage array of the phase change memory in this embodiment has m storage rows 11 and n storage columns, and m*n phase change storage cells 10 in total. The phase change memory has three redundant rows 12 arranged consecutively after m storage rows 11 .

In FIG. 1 , four row switches SW _i <j> are connected to the row control line WL<i> of each storage row, where i is from 0 to m-1, and j is from 0 to 3. For example: the row control line WL<0> of the 0th storage row is connected with SW ₀ <0>-SW ₀ <3>, a total of 4 row switches; ......, the control line WL< of the m-1th row m-1> is connected with SW _m-1 <0>-SW _m-1 <3>. Among them, the 4 row switches of each storage row are respectively connected to the row and the 3 rows below the row, that is, the 0th row switch is connected in series with the row control line, and one end of the 1st to 3rd row switches is connected to the The row control line, the other end is connected to the next 1 to 3 row control lines of the row in turn. The redundant row is used as the spare row of the storage row, and is connected to the corresponding row switch in the same way, for example, the switches SW _m-2 <0>-SW _m-2 <3> will be respectively connected to the m-2th row and the The m-1th row below the row and two redundant rows (redundant rows marked as 0 and 1 in the figure); the switches SW _m-1 <0>-SW _m-1 <3> will be respectively connected to the m-th 1 row and 3 redundant rows below that row.

Figure 1 shows the default state of the row switches, specifically SW<0>...SW _m-1 <0> of each storage row is turned on, SW ₀ <1>-SW ₀ <3>, ......, SW _m-1 <1>-SW _m-1 <3> off. At this time, each row control signal WL<0>...WL<m-1> controls its corresponding row. The above is an example of 3 redundant rows. If it is assumed that there are h redundant rows (h≤m), and each row control signal is connected to g switches, then g needs to satisfy g=h+1.

When a certain row is found to be wrong during the test, it is assumed that the first row in the storage row 11 (the storage row where the number 1 is located in Figure 1 (in the text of this application, the counting of the row starts from the 0th row) has an error , needs to be replaced.

As shown in Figure 2, at this time, switch off SW ₁ <0> in row 1, and close SW ₁ <1>. And make SW ₂ <0>, ... SW _m-1 <0> open, SW ₂ <1>, ... SW _m-1 <1> closed for all the following rows. That is to say, row 1 is replaced by row 2, row 2 is replaced by row 3, and so on, and row m-1 is finally replaced by row 0 of redundant row 12.

As can be seen from Fig. 2, the first row in error in storage row 11 has been disconnected from all row control signals and is no longer used. For ease of understanding, delete the unused line number of the first line in Figure 2, and use the second line before replacement as the current first line, and so on. That is to say, redundant lines are reduced from 3 lines to 2 lines.

In the next test, if there is still an error in the line, it is assumed that the xth line has an error, and the SW _x <1> of this line, and the SW _x+1 <1>, SW _x+2 of all lines below this line <1>,...SW _m-1 <1> is disconnected, SW _x <2> of this row, and SW _x+1 <2>, SW _x+2 of all rows below this row <2>, ... SW _m-1 <2> closed. Finally row m-1 is replaced by row 1 of the redundant row. And so on, until all the rows are tested.

If a third defective line is found, assuming that the defective line is the fth line, set SW _f <2> of this line, and SW _f+1 <2>, SW _f+2 <2 of all lines below this line >,...SW _m-1 <2> is disconnected, SW _f <3> of this row, and SW _f+1 <3>, SW _f+2 <3 of all rows below this row >, ... SW _m-1 <3> closed. Finally row m-1 is replaced by row 2 of the redundant row.

In this way, after the test is completed, all the wrong lines have been replaced, and there is no need to compare the addresses every time when reading and writing the memory, which improves the reading and writing speed.

In this embodiment, the row switches are used to replace them in order, but in practical applications, they can also be replaced out of order, as long as all the behaviors after the replacement are free of defective rows.

Each row switch in FIG. 1 is a switch with a control terminal, and the control terminal of each row switch is connected to a corresponding information storage circuit, and is controlled to be turned on or off by a switch control signal output by the information storage circuit.

The information storage circuit in this embodiment can be implemented by a non-volatile memory, which outputs the stored row switch on or off as a control signal to the corresponding row switch to control the row switch on or off. The information storage circuit can also be realized by a circuit composed of phase-change materials. The row switch selection circuit in this embodiment is realized by a logic circuit, specifically, it can be realized by a decoding circuit.

Figure 3 shows the structure of an information storage circuit made of phase-change materials and its connection with logic circuits and writing circuits. As shown in FIG. 3 , the information storage circuit includes: three switches S31 - S33 , two phase change materials 35 and 36 , a PMOS transistor 39 , an NMOS transistor 40 and an inverter 41 .

Wherein the first end of the first switch S31 is connected to the writing circuit 31 , and the second end is connected to the first end of the first phase change material 35 . The first end of the first phase change material 35 is also connected to the drain of the PMOS transistor 39 , and the second end thereof is connected to the first end of the second phase change material 36 and connected to the switch control signal line. The source of the PMOS transistor 39 is connected to the power supply. The second end of the second phase change material 36 is connected to the drain of the NMOS transistor 40 . The source of the NMOS transistor 40 is grounded. The second switch S32 is connected in parallel with the first phase change material 35 , and the third switch S33 is connected in parallel with the second phase change material 36 .

The logic circuit 34 in FIG. 3 is the row switch selection circuit, which receives the row control signal 32 and the switch selection signal 33 sent by the test software, and outputs the row switch selection signal to the information storage circuit corresponding to the selected row switch.

The row switch selection signal output by the logic circuit 34 in FIG. 3 is output to the first terminal of the inverter 41 , and the second terminal of the inverter 41 is connected to the gate of the PMOS transistor 39 . The row switch selection signal is also output to the gate of the NMOS transistor 40 at the same time.

The row switches in this embodiment are all switches with a control terminal, and the switch control signal line of each information storage circuit is connected to the control terminal of the corresponding row switch to control the corresponding row switch to be turned on or off.

In the circuit shown in Figure 3, the purpose of the first switch S31, the second switch S32 and the third switch S33 is to write 0 or 1 to the phase-change memory material, so as to store the information of whether the corresponding switch is turned on or off. In phase change material 35 and phase change material 36 . Due to the non-volatility of the phase change material, the information will not be lost when the memory array defect test is completed and the power is turned off. Afterwards, when the system is powered on normally, the switch is automatically turned on or off according to the information stored in the phase change materials 35 and 36, and finally the replacement of the wrong row (column) by the redundant row (column) is realized.

When performing a defect test on the storage array, the default state of the first switch S31 , the second switch S32 and the third switch S33 is off, as shown in FIG. 3 . The row control signal 32 and the switch gating signal 33 come from the output of the test program. According to the output of the two through the logic circuit 34, it can be specifically determined that a certain switch connected to a certain row control signal (WL<x>) is currently connected. (Which one of SW _x <0>-SW _x <3>) is turned on or off.

When the test program finds an error in a certain line and wants to turn off a certain line switch of a certain line, perform the following steps:

Step 1, output the row switch selection signal (strobe signal) to the information storage circuit 38 corresponding to the selected row switch after the row control signal 32 and the switch gating signal 33 are passed through the logic circuit 34, and go to select the one to write data in. The first phase change material 35 and the second phase change material 36 .

That is to say, the logic circuit 34 receives the row control signal 32 and the switch selection signal 33 input during the test, for each row, selects the information storage circuit 38 corresponding to the currently closed row switch, and outputs the row switch selection signal to the selected information storage circuit 38 , turning on the PMOS transistor 39 and the NMOS transistor 40 , thereby selecting the first phase change material 35 and the second phase change material 36 into which data is to be written.

For example: In Figure 2, it is assumed that the row of SW ₁ <0> in row 1 is defective, and SW ₀ <0> and SW ₁ <0> connected to WL<0>-WL<m-1> are selected in this step ...SW _m-1 <0>.

Step 2, the test program controls to turn on the first switch S31 and the third switch S33 in each selected information storage circuit 38, turn off the second switch S32, and write "0" to the first phase change material 35 by the writing circuit 31 .

In this step, since the first switch S31 and the third switch S33 are turned on, the write circuit 31 writes "0" to the first phase change material 35, and the write signal is grounded through the third switch S33, thus shielding the second phase change Material 36.

The state of the circuit at this time is shown in FIG. 4a. In FIG. 4a, only the state of one selected information storage circuit 38 is shown. Actually, the states of all the selected information storage circuits 38 are the same, so no repeated description is given here.

Step 3: The test program controls to turn on the second switch S32 in each selected information storage circuit 38 , turn off the third switch S33 , and write "1" to the second phase change material 36 by the writing circuit 31 .

In this step, since the first switch S31 and the second switch S32 are turned on, the first phase change material 35 is shielded, and the writing signal writes "1" to the second phase change material 36 through the first switch S31 and the second switch S32. ".

The state of the circuit at this time is shown in FIG. 4b. In FIG. 4b, only the state of one selected information storage circuit 38 is shown, and the states of all the selected information storage circuits 38 are actually the same, and the description will not be repeated here.

At this time, the phase change material 35 has a high resistance value, and the phase change material 36 has a low resistance value.

Step 4, turning off the first switch S31 , the second switch S32 and the third switch S33 in each selected information storage circuit 38 .

During normal operation, the first switch S31, the second switch S32 and the third switch S33 in the information storage circuit 38 are turned off, the PMOS transistor 39 and the NMOS transistor 40 are turned on, and the output switch control signal 37 is low level, The corresponding row switches controlled are turned off.

Here, by writing "0" to the phase change material 35 and "1" to the phase change material 36, the information that the corresponding row switch has been turned off is stored in the phase change material 35 and the phase change material 36 . In this way, when the system works normally, the corresponding row switch is in the off state.

The above four steps are used to remove defective rows, and the following steps will realize the function of replacing defective rows with non-defective rows and redundant rows.

Step 5, output the row switch selection signal (strobe signal) to the information storage circuit 38 corresponding to the selected row switch after the row control signal 32 and the switch strobe signal 33 are passed through the logic circuit 34, and go to select the one to write data in. The first phase change material 35 and the second phase change material 36 .

In this step, the logic circuit 34 receives the row control signal 32 and the switch selection signal 33 input during the test, and for each row, selects an information storage circuit 38 corresponding to a row switch with the same serial number connected to a non-defective row, and outputs the row switch The selection signal is sent to the selected information storage circuit 38 to select the first phase change material 35 and the second phase change material 36 in which data is to be written.

For example: in Figure 2, it is assumed that the row of SW ₁ <0> in row 1 is defective, and SW ₀ <1> and SW ₁ <1> connected to WL<0>-WL<m-1> are selected in this step ...SW _m-1 <1>.

Step 6, the test program controls the first switch S31 and the third switch S33 in each selected information storage circuit 38 to be turned on, the second switch S32 is turned off, and the writing circuit 31 writes "1" to the first phase change material 35 .

The principle of this step is the same as the above step 2, only the written data is not "0" but "1".

Step 7: The test program controls to turn on the second switch S32 in each selected information storage circuit 38 , turn off the third switch S33 , and write "0" to the second phase change material 36 by the write circuit 31 .

The principle of this step is the same as the above step 3, only the written data is not "1" but "0".

At this time, the phase change material 35 has a low resistance value, and the phase change material 36 has a high resistance value.

Step 8, turning off the first switch S31 , the second switch S32 and the third switch S33 in each selected information storage circuit 38 .

Here, by writing “1” to the phase change material 35 and “0” to the phase change material 36 , the information that the corresponding row switch has been turned on is stored in the phase change material 35 and the phase change material 36 . In this way, when the system is working normally, the corresponding row switch is in a conducting state.

After the above steps 5-8, the function of replacing defective rows with non-defective rows and redundant rows is realized.

Second preferred embodiment

This embodiment is realized by adding redundant columns. The phase change memory of this embodiment is the same as the phase change memory of the prior art in that it has a write circuit, a storage array and Q redundant columns. The difference lies in that It includes multiple information storage circuits and a column switch selection circuit.

The Q redundant columns in this embodiment are arranged continuously with the storage rows of the storage array. Each column control line of the memory array is connected with Q+1 row switches. Wherein, the 0th column switch is connected in series with the corresponding column control line, one end of the 1st to Qth column switches is connected to the corresponding column control line, and the other end is sequentially connected to the next 1 to Q column control lines of the corresponding column. Wherein, each column switch is correspondingly connected to an information storage circuit. The column switch selection circuit is connected with all the information storage circuits, and all the information storage circuits are connected with the writing circuit.

When it is tested that a certain column of the storage array is defective, the column switch selection circuit is first used to select the information storage circuit corresponding to the currently closed column switch for the defective column and all columns after the defective column, and the write circuit is selected. The column switch shutdown information is stored in the information storage circuit, and the information storage circuit outputs a switch control signal to turn off the corresponding column switch; and then through the column switch selection circuit, for the defective column and all columns after the defective column, select An information storage circuit corresponding to a column switch with the same serial number connected to a non-defective column, the write circuit stores the conduction information of the column switch in the selected information storage circuit, and the information storage circuit outputs a switch control signal to turn on Corresponding column switch.

FIG. 5 shows the connection relationship between the column switch, the storage array and the redundant column in the phase change memory of this embodiment, and the column switch in FIG. 5 is in a default state.

As shown in FIG. 5 , the storage array of the phase change memory in this embodiment has m storage rows, n storage columns 21 , and m*n phase change storage cells 20 in total. The phase change memory has three redundant columns 22 arranged consecutively behind n storage columns 21 .

In FIG. 5 , four column switches SW_B _i <j> are connected to the column control line BL<i> of each storage column, where i is from 0 to n-1, and j is from 0 to 3. For example: the column control line BL<0> of the 0th storage column is connected to SW_B ₀ <0>-SW_B ₀ <3>, a total of 4 column switches; ......, the control line BL< of the n-1th column n-1> is connected with SW_B _n-1 <0>-SW_B _n-1 <3>. Among them, the 4 column switches of each storage column are respectively connected to the column and the 3 columns below the column, that is, the 0th column switch is connected in series with the column control line, and one end of the 1st to 3rd column switches is connected to the The control line of the column in which it is located, and the other end is connected to the control lines of the next 1 to 3 columns of the column in turn. The redundant column is used as the spare column of the storage column, and is connected with the corresponding column switch in the same way, for example, the column switch SW_B _n-2 <0>-SW_B _n-2 <3> will be respectively connected to the n-2th column and The n-1th column below this column and two redundant columns (redundant examples marked as 0 and 1 in the figure); column switches SW_B _n-1 <0>-SW_B _n-1 <3> will be respectively connected to the first Column n-1 and 3 redundant columns below that column.

Figure 5 shows the default state of the column switch, specifically SW_B<0>...SW_B _n-1 <0> of each storage column is turned on, SW_B ₀ <1>-SW_B ₀ <3>, ......, SW_B _n-1 <1>-SW_B _n-1 <3> off. At this time, each column control signal BL<0>...BL<n-1> controls its corresponding column. The above is taking 3 redundant columns as an example. If it is assumed that there are h redundant columns (h≤n), and each column control signal is connected to g switches, then g needs to satisfy g=h+1.

When a certain error is found during the test, it is assumed to be the first column in the storage column 21 (the storage column where the number 1 is located in Figure 5 (in the text of this application, the counting of the rows starts from the 0th column) Something went wrong and needs to be replaced.

As shown in Figure 6, at this time, the SW_B ₁ <0> of the first column is opened, and SW_B ₁ <1> is closed. And make SW_B ₂ <0>, ......SW_B _n-1 <0> of all the following columns open, SW_B ₂ <1>, ......SW_B _n-1 <1> closed. That is to say, column 1 is replaced by column 2, column 2 is replaced by column 3, and so on, and column n-1 is finally replaced by column 0 of redundant column 22.

In this embodiment, the structure of the information storage circuit and its connection relationship with the writing circuit and the logic circuit are the same, the difference is that the control signal output by each information storage circuit is used to control the column switch connected to it. Its specific working principle is also exactly the same, and will not be repeated here.

It can be seen from the above embodiments that when the present invention finds defective rows or columns during testing, the information of these rows or columns is directly stored in the phase change material, so that the information can be preserved when the power is turned off. During normal operation, the on-off of the corresponding switch is controlled by reading the information in the phase-change material, and the defective row or column is directly replaced by the corresponding redundant row or column in the circuit. In this way, it is not necessary to compare addresses every time when reading and writing, which improves the reading and writing speed and saves the comparison circuit.

Claims (11)

1. the phase transition storage with redundant circuit comprises write circuit, a storage array and P redundant row or Q redundant columns, it is characterized in that: also comprise a plurality of information storage circuits, row or row switch selection circuit;

A said P redundant row or Q redundant columns are arranged in after the row or column of storage array continuously;

Each row control line of said storage array is connected with P+1 capable switch or each row control line is connected with Q+1 row switch; Said the 0th capable switch or row switch be connected on the institute be expert at or the row control line on; The 1st to P capable switch or the 1st end to Q row switch are connected to institute and are expert at or the row control line, on following 1 to P capable or 1 to the Q row control line that the other end is connected to successively that institute is expert at or is listed as;

Information storage circuit of the corresponding connection of said each row switch or each row switch; Said row or row switch select circuit to link to each other with all information storage circuits; Said all information storage circuits link to each other with write circuit;

When testing out storage array delegation or showing defective; Select circuit through row or row switch earlier; To defectiveness capable or row and defectiveness is capable or row after all row or row, select the capable switch or the corresponding information storage circuit of row switch of current closure, by write circuit storage line or row switch shutoff information in the information storage circuit of selecting; And said information storage circuit output switch control signal turn-offs corresponding capable switch or row switch; Select circuit through row or row switch again; To defectiveness capable or row and defectiveness is capable or row after all row or row; Select or row capable switch or a row switch corresponding information storage circuit that link to each other, same sequence number capable with zero defect; By write circuit storage line or row switch conduction information in the information storage circuit of selecting, and said information storage circuit output switch control signal, capable switch or row switch that conducting is corresponding.

2. phase transition storage as claimed in claim 1 is characterized in that: said information storage circuit is a nonvolatile memory; Row that it will be stored or row switch conduction or shutoff information are exported to coupled capable switch or row switch as control signal.

3. phase transition storage as claimed in claim 1; It is characterized in that: said row or row switch select circuit to be realized by logical circuit; Row of importing during its acceptance test or row control signal and switch are selected signal, and output row or row switch select signal to capable switch of selecting or the corresponding information storage circuit of row switch.

4. phase transition storage as claimed in claim 3 is characterized in that: said information storage circuit comprises: three switches, two phase-change materials, PMOS pipe, NMOS pipe and phase inverters; First end of said first switch links to each other with write circuit, and second end links to each other with first end of first phase-change material; First end of first phase-change material also links to each other with the drain electrode of PMOS pipe, and its second end links to each other with first end of second phase-change material, and connects the switch controlling signal line; The source electrode of PMOS pipe links to each other with power supply; Second end of second phase-change material links to each other with the drain electrode of NMOS pipe; The source ground of NMOS pipe; Said second switch is parallelly connected with first phase-change material; Said the 3rd switch is connected between switch controlling signal line and the ground;

Said row or row switch select the row of circuit output or row switch to select signal to output to first end of phase inverter and the grid of NMOS pipe, and second end of phase inverter is connected to the grid of PMOS pipe.

5. phase transition storage as claimed in claim 3 is characterized in that: described logical circuit is a decoding scheme.

6. like each described phase transition storage of claim 1-5, it is characterized in that: said capable switch or row switch are the switch with control end; The control end information storage circuit corresponding with it of said each row switch or row switch links to each other.

7. a phase transition storage is realized redundant method, it is characterized in that: adopt the described phase transition storage of claim 1; When testing out storage array delegation or showing defective, carry out following steps:

A, select circuit through row or row switch; To defectiveness capable or row and defectiveness is capable or row after all row or row; Select the capable switch or the corresponding information storage circuit of row switch of current closure; By write circuit storage line or row switch shutoff information in the information storage circuit of selecting, and said information storage circuit output switch control signal, turn-off corresponding capable switch or row switch;

B, select circuit through row or row switch; To defectiveness capable or row and defectiveness is capable or row after all row or row; Select or row capable switch or a row switch corresponding information storage circuit that link to each other, same sequence number capable with zero defect; By write circuit storage line or row switch conduction information in the information storage circuit of selecting, and said information storage circuit output switch control signal, capable switch or row switch that conducting is corresponding.

8. method as claimed in claim 7; It is characterized in that: said row or row switch select circuit to be realized by logical circuit; Row of importing during its acceptance test or row control signal and switch are selected signal, and output row or row switch select signal to capable switch of selecting or the corresponding information storage circuit of row switch.

9. method as claimed in claim 8 is characterized in that: said information storage circuit comprises: three switches, two phase-change materials, PMOS pipe, NMOS pipe and phase inverters; First end of said first switch links to each other with write circuit, and second end links to each other with first end of first phase-change material; First end of first phase-change material also links to each other with the drain electrode of PMOS pipe, and its second end links to each other with first end of second phase-change material, and connects the switch controlling signal line; The source electrode of PMOS pipe links to each other with power supply; Second end of second phase-change material links to each other with the drain electrode of NMOS pipe; The source ground of NMOS pipe; Said second switch is parallelly connected with first phase-change material; Said the 3rd switch is connected between switch controlling signal line and the ground;

Said row or row switch select the row of circuit output or row switch to select signal to output to first end of phase inverter and the grid of NMOS pipe, and second end of phase inverter is connected to the grid of PMOS pipe.

10. method as claimed in claim 9 is characterized in that: said steps A comprises:

Row of importing when A1, logical circuit acceptance test or row control signal and switch are selected signal; To defectiveness capable or row and defectiveness is capable or row after all row or row; Select the corresponding information storage circuit of capable switch or row switch of current closure, the capable or row switch of output two-way selects signal to give the information storage circuit of selecting;

First switch and the 3rd switch in each information storage circuit that A2, conducting are selected turn-off second switch, by write circuit first phase-change material are write 0;

Second switch in each information storage circuit that A3, conducting are selected turn-offs the 3rd switch, by write circuit second phase-change material is write 1;

First, second, third switch in each information storage circuit that A4, shutoff are selected, switch controlling signal line output cut-off signals is given corresponding capable switch or row switch, capable switch or row switch that shutoff is corresponding.

11. method as claimed in claim 10 is characterized in that: said step B comprises:

B1, logical circuit receive row or the row control signal and the switch selection signal of input; To defectiveness capable or row and defectiveness is capable or row after all row or row; Select or row capable switch or a row switch corresponding information storage circuit that link to each other, same sequence number capable with zero defect, the capable or row switch of output two-way is selected the information storage circuit of signal to selection;

First switch and the 3rd switch in each information storage circuit that B2, conducting are selected turn-off second switch, by write circuit first phase-change material are write 1;

Second switch in each information storage circuit that B3, conducting are selected turn-offs the 3rd switch, by write circuit second phase-change material is write 0;

First, second, third switch in each information storage circuit that B4, shutoff are selected, switch controlling signal line output Continuity signal is given corresponding capable switch or row switch, the capable switch or the row switch of conducting correspondence.

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