CN114228725A - Vehicle-mounted control system and unmanned vehicle - Google Patents
Vehicle-mounted control system and unmanned vehicle Download PDFInfo
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B60—VEHICLES IN GENERAL
- B60W—CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE OR DIFFERENT FUNCTION; CONTROL SYSTEMS SPECIALLY ADAPTED FOR HYBRID VEHICLES; ROAD VEHICLE DRIVE CONTROL SYSTEMS FOR PURPOSES NOT RELATED TO THE CONTROL OF A PARTICULAR SUB-UNIT
- B60W50/00—Details of control systems for road vehicle drive control not related to the control of a particular sub-unit, e.g. process diagnostic or vehicle driver interfaces
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B60—VEHICLES IN GENERAL
- B60W—CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE OR DIFFERENT FUNCTION; CONTROL SYSTEMS SPECIALLY ADAPTED FOR HYBRID VEHICLES; ROAD VEHICLE DRIVE CONTROL SYSTEMS FOR PURPOSES NOT RELATED TO THE CONTROL OF A PARTICULAR SUB-UNIT
- B60W50/00—Details of control systems for road vehicle drive control not related to the control of a particular sub-unit, e.g. process diagnostic or vehicle driver interfaces
- B60W2050/0001—Details of the control system
- B60W2050/0002—Automatic control, details of type of controller or control system architecture
- B60W2050/0004—In digital systems, e.g. discrete-time systems involving sampling
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Abstract
The application discloses on-vehicle control system and unmanned vehicle. The vehicle-mounted control system comprises: a memory; the first processing unit is connected with the memory and used for performing data reading and writing operations on the memory; the first processing unit is realized based on logic resources of the FPGA; the second processing unit is connected with the first processing unit and the memory and is used for carrying out data reading and writing operations on the memory; wherein the first processing unit and the second processing unit share data addresses in the memory. By the above manner, the resource consumption of the second processing unit can be reduced.
Description
Technical Field
The application relates to the technical field of unmanned driving, in particular to a vehicle-mounted control system and an unmanned vehicle.
Background
In the context of unmanned vehicles, the onboard control system on an unmanned vehicle typically has two processors, one as a master and the other as a slave.
The inventor has found that reading and writing of data from and to the slave processor can be realized only by the master processor, and the master processor is influenced to a certain extent in the process.
Disclosure of Invention
In order to solve the above problem, the present application provides an in-vehicle control system and an unmanned vehicle that can reduce resource consumption of a second processing unit.
In order to solve the technical problem, the application adopts a technical scheme that: there is provided an in-vehicle control system including: a memory; the first processing unit is connected with the memory and used for performing data reading and writing operations on the memory; the first processing unit is realized based on logic resources of the FPGA; the second processing unit is connected with the first processing unit and the memory and is used for carrying out data reading and writing operations on the memory; wherein the first processing unit and the second processing unit share data addresses in the memory.
Wherein, on-vehicle control system still includes: the sensor is connected with the first processing unit and used for transmitting sensor data to the first processing unit; the first processing unit is used for storing the sensor data to a target shared address of the memory; the second processing unit is used for reading the sensor data from the target shared address.
The first processing unit is specifically used for storing the sensor data to a target shared address of the memory for multiple times; and after the last storage is finished, sending a storage finishing instruction to the second processing unit.
The second processing unit is specifically configured to determine a target shared address in the memory, and send the target shared address to the first processing unit.
The number of the target shared addresses is multiple; the first processing unit is used for storing the sensor data to the memory according to the sequence of the target shared addresses; the second processing unit is used for reading the sensor data according to the sequence of the target shared addresses.
After the target shared addresses are used up, the first processing unit is used for writing the sensor data into the idle target shared addresses when the second processing unit is detected to read the sensor data in any target shared address.
Wherein, the number of the sensors is a plurality; the first processing unit includes: the data interfaces are used for being respectively connected with the sensors; and the preprocessing units are respectively connected with the data interfaces and are used for respectively performing parallel preprocessing on corresponding sensor data and storing the preprocessed sensor data to a target shared address.
The second processing unit is connected with the first processing unit through a PCIE interface.
Wherein, the memory is DDR.
In order to solve the above technical problem, another technical solution adopted by the present application is: there is provided an unmanned vehicle comprising an onboard control system as provided in the preceding claims.
The beneficial effects of the embodiment of the application are that: be different from prior art, the on-vehicle control system that this application provided, this on-vehicle control system includes: a memory; the first processing unit is connected with the memory and used for performing data reading and writing operations on the memory; the first processing unit is realized based on logic resources of the FPGA; the second processing unit is connected with the first processing unit and the memory and is used for carrying out data reading and writing operations on the memory; wherein the first processing unit and the second processing unit share data addresses in the memory. Through the mode, on one hand, the connection relation among the memory, the first processing unit and the second processing unit is changed, the process that the first processing unit needs to store data through interrupting the second processing unit in the related technology is improved, the interruption frequency of the second processing unit in the data storage process is reduced, and further the resource consumption of the second processing unit is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic structural diagram of a first embodiment of an onboard control system provided by the present application;
FIG. 2 is a schematic structural diagram of a second embodiment of an onboard control system provided by the present application;
FIG. 3 is a schematic structural diagram of a third embodiment of an onboard control system provided by the present application;
FIG. 4 is a schematic structural diagram of an embodiment of an unmanned vehicle as provided herein.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
The inventor researches for a long time to find that the reading and writing of the data from the slave processor can be realized only by the master processor, the master processor needs to be interrupted in the process, and then the data reading and writing of the master processor are carried out, so that the influence on the master processor is caused to a certain extent, and based on the influence, any one of the following technical schemes is proposed to solve the problem.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a first embodiment of an onboard control system provided by the present application. The in-vehicle control system 10 includes: a memory 11, a first processing unit 12 and a second processing unit 13.
The first processing unit 12 is connected to the memory 11, and is configured to perform data read-write operation on the memory 11; the first processing unit 12 is implemented based on a logic resource of an FPGA (Field Programmable Gate Array).
The FPGA adopts a concept of a Logic Cell array lca (Logic Cell array), and includes three parts, namely, a configurable Logic module clb (configurable Logic block), an input Output module iob (input Output block), and an internal connection (Interconnect). A Field Programmable Gate Array (FPGA) is a programmable device that has a different structure than traditional logic circuits and gate arrays (such as PAL, GAL and CPLD devices). The FPGA utilizes small lookup tables (16 × 1RAM) to realize combinational logic, each lookup table is connected to the input end of a D flip-flop, and the flip-flops drive other logic circuits or drive I/O (input/output) circuits, so that basic logic unit modules capable of realizing both combinational logic functions and sequential logic functions are formed, and the modules are connected with each other or connected to an I/O (input/output) module by utilizing metal connecting wires. The logic of the FPGA is implemented by loading programming data into the internal static memory cells, the values stored in the memory cells determine the logic function of the logic cells and the way of the connections between the modules or between the modules and the I/O and finally the functions that can be implemented by the FPGA, which allows an unlimited number of programming.
The second processing unit 13 is connected with the first processing unit 12 and the memory 11, and is used for performing data reading and writing operations on the memory 11; wherein the first processing unit 12 and the second processing unit 13 share data addresses in the memory 11.
In some embodiments, the data addresses in the memory 11 may be pre-processed to determine shared data addresses and non-shared data addresses. In particular, the determination of the shared data address may be performed by the second processing unit 13. For example, the second processing unit 13 first determines the current free data address in the memory 11. And then determining the shared data address from the idle data addresses according to a preset proportion. If the number of the current idle addresses is 500 and the preset proportion is 20%, 100 idle addresses are determined as the shared data addresses. After determining the shared data address, the shared data address is sent to the first processing unit 12 so that the first processing unit 12 can know the specific shared data address. It will be appreciated that the preset ratio may be dynamically set according to the specific number of free data addresses in the memory 11. For example, when the number of idle data addresses is small, the preset ratio is adjusted to be low, and when the number of idle data addresses is large, the preset ratio is adjusted to be high.
In an application scenario, when the first processing unit 12 receives data a, it may store the data a directly into the shared data address. The second processing unit 13 may also acquire the data a in the shared data address.
In another application scenario, when the first processing unit 12 needs to read the data a, the data a can be directly read from the shared data address without sending an interrupt instruction to the second processing unit 13, so as to interrupt the second processing unit 13. At this time, the second processing unit 13 does not need to respond to the interrupt instruction, so that interaction with the first processing unit 12 is reduced, resource consumption of the second processing unit 13 is reduced, the second processing unit 13 can continue to process other tasks, and processing efficiency is improved.
In the present embodiment, the in-vehicle control system 10 includes: a memory 11; the first processing unit 12 is connected with the memory 11 and is used for performing data reading and writing operations on the memory 11; the first processing unit 12 is implemented based on logic resources of the FPGA; the second processing unit 13 is connected with the first processing unit 12 and the memory 11 and is used for performing data reading and writing operations on the memory 11; wherein the first processing unit 12 and the second processing unit 13 share data addresses in the memory 11. Through the manner, on one hand, the connection relation among the memory 11, the first processing unit 12 and the second processing unit 13 is changed, the process that the first processing unit 12 needs to interrupt the second processing unit 13 to store data in the related art is improved, the interruption frequency of the second processing unit 13 in the data storage process is reduced, and further the resource consumption of the second processing unit 13 is reduced, on the other hand, the first processing unit 12 directly reads and writes data in the memory 11, and the data reading and writing are completed without interrupting the second processing unit 13, so that the time of the second processing unit 13 for processing the data is reduced, and the timeliness and the value of the data are improved.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a second embodiment of the vehicle-mounted control system provided in the present application. The in-vehicle control system 10 includes: memory 11, a first processing unit 12, a second processing unit 13 and a sensor 14.
The sensor 14 is connected to the first processing unit 12 for transmitting sensor data to the first processing unit 12. In some embodiments, the sensor 14 may be a radar sensor and/or an image sensor.
The first processing unit 12 is used to store the sensor data to the target shared address of the memory 11.
When the second processing unit 13 needs to use the sensor data, the second processing unit 13 is configured to read the sensor data from the target shared address.
In an application scenario, the first processing unit 12 is specifically configured to store the sensor data to the target shared address of the memory 11 for multiple times; and after the last store is completed, send a store complete instruction to the second processing unit 13.
For example, the target shared address includes a target shared address a, a target shared address B, and a target shared address C. The first processing unit 12 divides the sensor data into 3 pieces and stores the pieces of sensor data in the target shared address. After the third copy is stored to the target shared address, the first processing unit 12 sends a storage completion instruction to the second processing unit 13.
In this process, the first processing unit 12 is equivalent to sending an interrupt instruction to the second processing unit 13 only once, and compared with a manner in which an interrupt instruction needs to be sent to the second processing unit 13 every time data is stored in the related art, so that the second processing unit 13 stores data, the first processing unit 12 directly reads and writes data from and into the memory 11, and data reading and writing do not need to be completed by interrupting the second processing unit 13, so that time for processing data by the second processing unit 13 is reduced, and timeliness and value of data are improved.
In another application scenario, the second processing unit 13 is specifically configured to determine a target shared address in the memory 11, and send the target shared address to the first processing unit 12. When knowing the target shared address, the first processing unit 12 can then directly read the corresponding data from the target shared address or write the corresponding data to the target shared address. Data reading and writing are finished without interrupting the second processing unit 13, so that the time of the second processing unit 13 for processing the data is reduced, and the timeliness and the value of the data are improved.
In another application scenario, the number of target shared addresses is multiple; the first processing unit 12 is used for storing the sensor data to the memory 11 according to the sequence of the target shared addresses; the second processing unit 13 is configured to read the sensor data in the order of the target shared addresses.
For example, the target shared address includes a target shared address a, a target shared address B, and a target shared address C. The storage order is A-C. The first processing unit 12 is configured to store the sensor data in the memory 11 according to the sequence of the target shared addresses, that is, the first processing unit 12 is configured to store the sensor data to the target shared address a first, store the sensor data to the target shared address B after the target shared address a is completely occupied, and store the sensor data to the target shared address C after the target shared address B is completely occupied.
Meanwhile, the second processing unit 13 may perform data reading in the order of storage. For example, the second processing unit 13 first reads data from the target shared address a, and after the reading is completed, the target shared address a may be subjected to an erasing operation, so that the target shared address a is a free address, and the second processing unit 13 writes data in the free target shared address a again.
In another application scenario, after the plurality of target shared addresses are used up, the first processing unit 12 is configured to write the sensor data into a free target shared address when detecting that the second processing unit 13 reads the sensor data from any target shared address.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a third embodiment of the vehicle-mounted control system provided in the present application. The in-vehicle control system 10 includes: memory 11, a first processing unit 12, a second processing unit 13 and a sensor 14. The number of the sensors 14 is plural.
The first processing unit 12 includes: a plurality of data interfaces 121 and a plurality of preprocessing units 122. The plurality of data interfaces 121 are used to connect the plurality of sensors 14, respectively. The plurality of preprocessing units 122 are respectively connected to the plurality of data interfaces 121, and are configured to respectively perform parallel preprocessing on the corresponding sensor data, and store the preprocessed sensor data to the target shared address in the memory 11.
In this embodiment, the plurality of preprocessing units 122 are used to perform parallel preprocessing on the corresponding sensor data, so that the sensor data corresponding to each sensor 14 can be processed synchronously, delay on the sensor data is reduced, resource occupation on the second processing unit 13 can be reduced, data preprocessing on the sensor data can be performed in real time, overall caching on the sensor data is not required, processing time on the sensor data can be reduced, real-time performance of the sensor data is ensured, and timeliness of vehicle control is improved.
In any of the above embodiments, the second processing unit 13 is connected to the first processing unit 12 through a PCIE (peripheral component interconnect express) interface. The memory 11 is a DDR (Double rate synchronous random access memory). In other embodiments, the Memory 11 may also be other types of memories, such as a DRAM (Dynamic Random Access Memory), an MRAM (magnetic Random Access Memory), and the like.
In the related technology, based on PCIE data interaction, one-time data transmission has one-time interrupt signal, so that the accuracy of universal data interaction is ensured. The application can customize a PCIE transmission mechanism. By using the second processing unit 13 to allocate the shared data address, even if the first processing unit 12 transmits one frame of data for a plurality of times, the second processing unit 13 is notified without interruption, and the second processing unit 13 is notified after the data transmission is completed. The interrupt response of the second processing unit 13 is reduced, and the processing efficiency of the second processing unit 13 is greatly improved.
Referring to fig. 4, fig. 4 is a schematic structural diagram of an embodiment of the unmanned vehicle provided by the present application. The unmanned vehicle 40 includes an onboard control system 10. Wherein, this on-vehicle control system 10 includes: a memory 11, a first processing unit 12 and a second processing unit 13.
The first processing unit 12 is connected to the memory 11, and is configured to perform data read-write operation on the memory 11; the first processing unit 12 is implemented based on a logic resource of an FPGA (Field Programmable Gate Array).
The second processing unit 13 is connected with the first processing unit 12 and the memory 11, and is used for performing data reading and writing operations on the memory 11; wherein the first processing unit 12 and the second processing unit 13 share data addresses in the memory 11.
In some embodiments, the data addresses in the memory 11 may be pre-processed to determine shared data addresses and non-shared data addresses. In particular, the determination of the shared data address may be performed by the second processing unit 13. For example, the second processing unit 13 first determines the current free data address in the memory 11. And then determining the shared data address from the idle data addresses according to a preset proportion. If the number of the current idle addresses is 500 and the preset proportion is 20%, 100 idle addresses are determined as the shared data addresses. After determining the shared data address, the shared data address is sent to the first processing unit 12 so that the first processing unit 12 can know the specific shared data address. It will be appreciated that the preset ratio may be dynamically set according to the specific number of free data addresses in the memory 11. For example, when the number of idle data addresses is small, the preset ratio is adjusted to be low, and when the number of idle data addresses is large, the preset ratio is adjusted to be high.
In an application scenario, when the first processing unit 12 receives data a, it may store the data a directly into the shared data address. The second processing unit 13 may also acquire the data a in the shared data address.
In another application scenario, when the first processing unit 12 needs to read the data a, the data a can be directly read from the shared data address without sending an interrupt instruction to the second processing unit 13, so as to interrupt the second processing unit 13. At this time, the second processing unit 13 does not need to respond to the interrupt instruction, so that interaction with the first processing unit 12 is reduced, resource consumption of the second processing unit 13 is reduced, the second processing unit 13 can continue to process other tasks, and processing efficiency is improved.
In the present embodiment, the in-vehicle control system 10 in the unmanned vehicle 40 includes: a memory 11; the first processing unit 12 is connected with the memory 11 and is used for performing data reading and writing operations on the memory 11; the first processing unit 12 is implemented based on logic resources of the FPGA; the second processing unit 13 is connected with the first processing unit 12 and the memory 11 and is used for performing data reading and writing operations on the memory 11; wherein the first processing unit 12 and the second processing unit 13 share data addresses in the memory 11. Through the manner, on one hand, the connection relation among the memory 11, the first processing unit 12 and the second processing unit 13 is changed, the process that the first processing unit 12 needs to interrupt the second processing unit 13 to store data in the related art is improved, the interruption frequency of the second processing unit 13 in the data storage process is reduced, and further the resource consumption of the second processing unit 13 is reduced, on the other hand, the first processing unit 12 directly reads and writes data in the memory 11, and the data reading and writing are completed without interrupting the second processing unit 13, so that the time of the second processing unit 13 for processing the data is reduced, and the timeliness and the value of the data are improved.
In summary, according to the present application, PCIE transmission and shared data address transmission are customized through any of the above embodiments. The data transmission efficiency is improved, the burden of the second processing unit 13 is greatly reduced, the second processing unit 13 can be used for processing more other modules, and the problem of resource shortage of the second processing unit 13 in the unmanned vehicle can be solved.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, and for example, the division of the circuits or units is only one type of division of logical functions, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made according to the content of the present specification and the accompanying drawings, or which are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. An in-vehicle control system, characterized by comprising:
a memory;
the first processing unit is connected with the memory and is used for performing data reading and writing operations on the memory; the first processing unit is realized based on logic resources of an FPGA;
the second processing unit is connected with the first processing unit and the memory and is used for carrying out data reading and writing operations on the memory;
wherein the first processing unit and the second processing unit share a data address in the memory.
2. The on-board control system of claim 1, further comprising:
the sensor is connected with the first processing unit and used for transmitting sensor data to the first processing unit;
the first processing unit is used for storing the sensor data to a target shared address of the memory;
the second processing unit is used for reading the sensor data from the target shared address.
3. The on-board control system of claim 2, wherein the first processing unit is specifically configured to store the sensor data to the target shared address of the memory a plurality of times; and after the last storage is finished, sending a storage finishing instruction to the second processing unit.
4. The on-board control system of claim 2, wherein the second processing unit is specifically configured to determine the target sharing address in the memory and send the target sharing address to the first processing unit.
5. The on-vehicle control system according to claim 2, characterized in that the number of the target shared addresses is plural;
the first processing unit is used for storing the sensor data to the memory according to the sequence of the target shared addresses;
the second processing unit is configured to read the sensor data in an order from the target shared address.
6. The vehicle-mounted control system according to claim 5, wherein after the plurality of target sharing addresses are used up, the first processing unit is configured to write the sensor data into the idle target sharing address when detecting that the second processing unit reads the sensor data in any one of the target sharing addresses.
7. The on-board control system according to claim 2, characterized in that the number of the sensors is plural;
the first processing unit includes:
a plurality of data interfaces for connecting a plurality of said sensors, respectively;
the preprocessing units are respectively connected with the data interfaces and used for respectively performing parallel preprocessing on the corresponding sensor data and storing the preprocessed sensor data to the target shared address.
8. The vehicle-mounted control system according to claim 1, wherein the second processing unit is connected to the first processing unit through a PCIE interface.
9. The on-board control system of claim 1, wherein the memory is DDR.
10. An unmanned vehicle, characterized in that the unmanned vehicle comprises an on-board control system according to any of claims 1-9.
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