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CN114221647B - Adaptive drive circuit, IO interface circuit and chip, electronic equipment - Google Patents

Adaptive drive circuit, IO interface circuit and chip, electronic equipment Download PDF

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Publication number
CN114221647B
CN114221647B CN202111490203.XA CN202111490203A CN114221647B CN 114221647 B CN114221647 B CN 114221647B CN 202111490203 A CN202111490203 A CN 202111490203A CN 114221647 B CN114221647 B CN 114221647B
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circuit
current limiting
limiting device
driving
output
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CN114221647A (en
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张阳
刘勇江
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Chengdu Haiguang Microelectronics Technology Co Ltd
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Chengdu Haiguang Microelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

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  • Computer Hardware Design (AREA)
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  • General Engineering & Computer Science (AREA)
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Abstract

本申请涉及一种自适应驱动电路、IO接口电路及芯片、电子设备，属于电子电路技术领域。该自适应驱动电路，包括：驱动主体电路、分压电路；驱动主体电路，用于输出驱动信号；所述分压电路的第一端用于连接第一电源，所述分压电路的第二端接地，所述分压电路的输出端与所述驱动主体电路连接，所述分压电路用于输出作为所述驱动主体电路中输出晶体管的控制电源，以使所述驱动主体电路的上拉能力与下拉能力在不同PVT条件下一致。该驱动主体电路的上拉能力与下拉能力在不同PVT条件下保持一致，且相对于传统驱动电路来说，能减小PMOS管的最大导通电阻阻值，进而可以减小整个驱动电路的版图面积。

The present application relates to an adaptive driving circuit, an IO interface circuit and a chip, and an electronic device, and belongs to the field of electronic circuit technology. The adaptive driving circuit includes: a driving main circuit, a voltage divider circuit; the driving main circuit is used to output a driving signal; the first end of the voltage divider circuit is used to connect to a first power supply, the second end of the voltage divider circuit is grounded, the output end of the voltage divider circuit is connected to the driving main circuit, and the voltage divider circuit is used to output a control power supply as an output transistor in the driving main circuit, so that the pull-up capability and pull-down capability of the driving main circuit are consistent under different PVT conditions. The pull-up capability and pull-down capability of the driving main circuit are consistent under different PVT conditions, and compared with the traditional driving circuit, the maximum on-resistance of the PMOS tube can be reduced, thereby reducing the layout area of the entire driving circuit.

Description

Self-adaptive driving circuit, IO interface circuit, chip and electronic equipment
Technical Field
The application belongs to the technical field of electronic circuits, and particularly relates to a self-adaptive driving circuit, an IO interface circuit, a chip and electronic equipment.
Background
The IO (Input Output) interface circuit is widely applied to various IO interface chips (such as a processor, a memory, etc.), and whether the IO interface circuit works normally directly determines the availability of the whole chip. And the driving circuit is used as an important component of the IO interface circuit, and the quality of the output signal of the driving circuit directly determines the quality of the output signal of the IO interface circuit.
The voltage withstand capability of a MOS (Metal Oxide Semiconductor ) transistor decreases with the progress of the semiconductor process, so that a device voltage withstand problem is usually solved by using a cascode MOS transistor structure. The conventional driving circuit is shown in fig. 1, and includes two independent power supplies VDDH and VDDL, wherein the maximum voltage difference that all MOS devices can withstand is VDDL, and in the figure, the control signal pre_pgate is a square wave control signal of VDDL to VDDH, and the control signal pre_ngate is a square wave control signal of 0 to VDDL. The resistor R1 and the PMOS tubes P1 and P2 form a driving pull-up branch, and the resistor R2 and the NMOS tubes N1 and N2 form a driving pull-down branch.
When the PAD signal is switched (from low level to high level or from high level to low level), the MOS transistor works as a switching transistor in a deep linear region due to the resistors R1 and R2. The pull-up resistance at the final PAD is the sum of R1 and the on-resistance of the MOS transistors P1 and P2 working in the deep linear region. The pull-down resistance at PAD is the sum of R2 and the on-resistance of MOS transistors N1 and N2 working in the deep linear region. The |VGS|voltage of the P1 pipe is VDDH-VDDL when the P1 pipe is conducted, the |VGS|voltage of the P2 pipe is vp1-VDDL, the |VGS|voltage of the N1 pipe is VDDL-vn1, the |VGS|voltage of the N2 pipe is VDDL, wherein vp1 is the voltage of the source end of the P2 pipe, vp1 is approximately equal to VDDH, vn1 is the voltage of the source end of the N1 pipe, and vn1 is approximately equal to 0.
Since VDDH and VDDL are different power supplies, under different PVT (Process Voltage Temperature, process, voltage, temperature combinations), the gate-source voltages of PMOS transistors are (VDDHmin-VDDLmax) to (VDDHmax-VDDLmin), and the gate-source voltages of NMOS transistors are VDDLmin to VDDLmax. Therefore, the gate-source voltage range of the NMOS tube is (VDDLmax-VDDLmin), and the gate-source voltage range of the PMOS tube is (VDDHmax-VDDHmin + VDDLmax-VDDLmin). The pull-up capability of the driving pull-up branch and the pull-down capability of the driving pull-down branch in the driving circuit are not matched under different PVT conditions, which can greatly deteriorate the output signal quality of the driving circuit. In addition, because the influence of the gate-source voltage of the PMOS tube is larger under different PVT conditions, the deviation of the output on-resistance of the driving pull-up branch circuit under different PVT conditions is large, and particularly when the gate-source voltage difference of the PMOS tube is small, if the maximum on-resistance of the PMOS tube is required to meet the design requirement, the area of the PMOS tube needs to be increased, so that the layout area of the whole driving circuit is increased.
Disclosure of Invention
In view of the above, the present application is directed to providing an adaptive driving circuit, an IO interface circuit, a chip, and an electronic device, so as to solve the problems that the pull-up capability and the pull-down capability of the existing driving circuit are not matched under different PVT conditions, and the output on-resistance of the driving pull-up branch circuit is greatly deviated under different PVT conditions.
Embodiments of the present application are implemented as follows:
In a first aspect, an embodiment of the present application provides an adaptive driving circuit, including a driving main circuit and a voltage division circuit, where the driving main circuit is configured to output a driving signal, a first end of the voltage division circuit is configured to connect to a first power supply, a second end of the voltage division circuit is grounded, an output end of the voltage division circuit is connected to the driving main circuit, and the voltage division circuit is configured to output a control power supply serving as an output transistor in the driving main circuit, so that a pull-up capability and a pull-down capability of the driving main circuit are consistent under different PVT conditions. In the embodiment of the application, the self-adaptive regulation technology is adopted, the voltage division circuit is utilized to divide the first power supply (such as VDDH), and the voltage obtained by the voltage division is used as the control power supply of the output transistor in the driving main circuit, so that the dynamic regulation function of the control power supply of the output transistor in the driving main circuit along with the power supply VDDH is realized, the control power supply can be dynamically changed along with the power supply VDDH and is influenced by different PVT conditions to be consistent, the pull-up capacity and the pull-down capacity of the driving main circuit can be kept consistent under different PVT conditions, and the maximum on resistance value of the PMOS tube can be reduced, so that the layout area of the whole driving circuit can be reduced.
With reference to one possible implementation manner of the first aspect, the voltage dividing circuit includes a voltage dividing base circuit and an operational amplifier, a first end of the voltage dividing base circuit is used for being connected with the first power supply, a second end of the voltage dividing base circuit is grounded, the voltage dividing base circuit is used for outputting an internal power supply, a first input end of the operational amplifier is connected with an output end of the voltage dividing base circuit, a second input end of the operational amplifier is connected with an output end of the operational amplifier, and an output end of the operational amplifier outputs a control power supply serving as an output transistor in the driving main circuit. In the embodiment of the application, the operational amplifier is equivalent to a unit gain buffer (buffer), and can provide enough driving capability by adding a unit gain so as to enhance the driving capability of the voltage division basic circuit.
With reference to one possible implementation manner of the first aspect, the voltage dividing base circuit includes a first current limiting device and a second current limiting device, wherein a first end of the first current limiting device is connected with the first power supply, a second end of the first current limiting device is grounded through the second current limiting device, the second end of the first current limiting device is further connected with a first input end of the operational amplifier, and the second end of the first current limiting device is an output end of the voltage dividing base circuit. In the embodiment of the application, the purpose of partial pressure can be realized by adopting common components, namely the first current limiting device and the second current limiting device, and the cost can be saved while the purpose is realized.
With reference to a possible implementation manner of the first aspect embodiment, a resistance value of the first current limiting device is consistent with a resistance value of the second current limiting device. In the embodiment of the application, the resistance values of the first current limiting device and the second current limiting device are consistent, so that the voltage after voltage division is equal to 0.5×vddh, and vddh is the first power supply.
With reference to one possible implementation manner of the first aspect, the voltage dividing base circuit includes a first output end and a second output end, where the first output end is used for outputting a first internal power supply, the second output end is used for outputting a second internal power supply, and correspondingly, the operational amplifier includes a first operational amplifier and a second operational amplifier, the first input end of the first operational amplifier is connected with the first output end, the second input end of the first operational amplifier is connected with the output end of the first operational amplifier, the output end of the first operational amplifier outputs a control power supply serving as an output transistor in a driving pull-up branch in the driving main circuit, the first input end of the second operational amplifier is connected with the second output end, the second input end of the second operational amplifier is connected with the output end of the second operational amplifier, and the output end of the second operational amplifier outputs a control power supply serving as an output transistor in a driving pull-down branch in the driving main circuit. In the embodiment of the application, by outputting two internal power supplies, one of which is used as a control power supply for driving the output transistor in the pull-up branch and the other of which is used as a control power supply for driving the output transistor in the pull-down branch, the body effect influence of the output transistor can be eliminated.
With reference to one possible implementation manner of the first aspect, the voltage dividing base circuit includes a first current limiting device, a second current limiting device and a third current limiting device, wherein a first end of the first current limiting device is connected with the first power supply, a second end of the first current limiting device is connected with a first end of the second current limiting device, the second end of the second current limiting device is grounded through the third current limiting device, the second end of the first current limiting device is further connected with a first input end of the second operational amplifier, the second end of the first current limiting device is the second output end, the second end of the second current limiting device is further connected with the first input end of the first operational amplifier, and the second end of the second current limiting device is the first output end. In the embodiment of the application, the purpose of partial pressure can be realized by adopting the first current limiting device, the second current limiting device and the third current limiting device, and the application has the advantages of simple structure and easy realization.
With reference to one possible implementation manner of the first aspect, the voltage dividing base circuit includes a first current limiting device, a second current limiting device, a third current limiting device and a fourth current limiting device, wherein a first end of the first current limiting device is connected with the first power supply, a second end of the first current limiting device is grounded through the second current limiting device, the second end of the first current limiting device is also connected with a first input end of the first operational amplifier, the second end of the first current limiting device is the first output end, the first end of the third current limiting device is connected with the first power supply, the second end of the third current limiting device is grounded through the fourth current limiting device, the second end of the third current limiting device is also connected with the first input end of the second operational amplifier, and the second end of the third current limiting device is the second output end. In the embodiment of the application, 4 current limiting devices are adopted to form two paths of voltage dividing branches to obtain two internal power supplies, so that the adjustment of each internal power supply is more flexible.
With reference to a possible implementation manner of the first aspect, the current limiting device in the voltage division basic circuit includes a current limiting resistor or a MOS transistor, and if the current limiting device is a MOS transistor, a drain electrode and a gate electrode of the MOS transistor are used together as a connection terminal. In the embodiment of the application, the common current limiting resistor or the MOS tube is adopted to form the voltage dividing circuit, so that the design cost of the circuit can be saved while the aim of the application is fulfilled.
With reference to one possible implementation manner of the first aspect embodiment, the magnitude of the control power output by the first op-amp as the output transistor in the driving pull-up leg is 0.5×vddh-V1, the magnitude of the control power output by the second op-amp as the output transistor in the driving pull-down leg is 0.5×vddh+v2, vddh is the first power supply, V1 is a first preset threshold value, and V2 is a second preset threshold value. In the embodiment of the application, the influence of the body effect of the output transistor is eliminated by outputting 2 power supplies with specific sizes, so that the signal quality output by the driving circuit can be further improved.
In a second aspect, an embodiment of the present application further provides an IO interface circuit, including a control logic circuit and an adaptive driving circuit as provided in the foregoing first aspect embodiment and/or in combination with any one of the possible implementation manners of the first aspect embodiment, where the control logic circuit is configured to provide a driving signal for the adaptive driving circuit.
In a third aspect, an embodiment of the present application further provides an IO interface chip integrated with the IO interface circuit provided in the embodiment of the second aspect.
In a fourth aspect, an embodiment of the present application further provides an electronic device, including a body and the adaptive driving circuit provided by the foregoing first aspect embodiment and/or any one of possible implementation manners of the foregoing first aspect embodiment, or the IO interface circuit provided by the foregoing second aspect embodiment.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. The above and other objects, features and advantages of the present application will become more apparent from the accompanying drawings. Like reference numerals refer to like parts throughout the several views of the drawings. The drawings are not intended to be drawn to scale, with emphasis instead being placed upon illustrating the principles of the application.
Fig. 1 is a schematic circuit diagram of a conventional driving circuit.
Fig. 2 shows a schematic structural diagram of an adaptive driving circuit according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of another adaptive driving circuit according to an embodiment of the present application.
Fig. 4 is a schematic circuit diagram of an adaptive driving circuit according to an embodiment of the present application.
Fig. 5 shows a schematic structural diagram of another adaptive driving circuit according to an embodiment of the present application.
Fig. 6 is a schematic circuit diagram of another adaptive driving circuit according to an embodiment of the present application.
Fig. 7 is a schematic circuit diagram of another adaptive driving circuit according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, relational terms such as "first," "second," and the like may be used solely to distinguish one entity or action from another entity or action in the description of the application without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, article or apparatus that comprises the element.
Furthermore, the term "and/or" in the present application is merely an association relation describing the association object, and indicates that three kinds of relations may exist, for example, a and/or B may indicate that a exists alone, and a and B exist together, and B exists alone.
In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "connected" and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, integrally connected, electrically connected, directly connected, indirectly connected through an intermediate medium, or communicating between the two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In view of the fact that the pull-up capability of the driving pull-up branch circuit and the pull-down capability of the driving pull-down branch circuit in the existing driving circuit are not matched under different PVT (Process Voltage Temperature, combination of process, voltage and temperature) conditions, the problem of greatly deteriorating the output signal quality of the driving circuit is solved, and the problem that the output on-resistance of the driving pull-up branch circuit deviates greatly under different PVT conditions is solved, if the maximum on-resistance of the PMOS tube meets the design requirement when the gate-source voltage difference of the PMOS tube is small, the area of the PMOS tube needs to be increased, and the layout area of the whole driving circuit is increased is solved. The embodiment of the application provides a self-adaptive driving circuit, which adopts a self-adaptive regulation technology, utilizes a voltage division circuit to divide a first power supply (such as VDDH) and takes the voltage obtained by the voltage division as a control power supply of an output transistor in a driving main body circuit, so as to realize the dynamic regulation function of the control power supply of the output transistor in the driving main body circuit along with the power supply VDDH, not only can keep the pull-up capacity and the pull-down capacity of the driving main body circuit consistent under different PVT conditions, but also can reduce the maximum on-resistance of a PMOS (P-channel metal oxide semiconductor) tube, thereby reducing the layout area of the whole driving circuit.
For easy understanding, the adaptive driving circuit according to the embodiment of the present application will be described with reference to fig. 2. The adaptive driving circuit includes a voltage dividing circuit and a driving body circuit.
The driving main circuit is used for outputting driving signals and comprises a PMOS tube P1, a PMOS tube P2, a resistor R1, an NMOS tube N2 and a resistor R2. The resistor R1 and the PMOS tubes P1 and P2 form a driving pull-up branch, the resistor R2 and the NMOS tubes N1 and N2 form a driving pull-down branch, and the resistance of the resistor R1 is consistent with that of the resistor R2. The transistors P2 and N1 are output transistors in the driving body circuit. In fig. 2, pre_pgate is a square wave control signal of vddl_1 to vddh, and pre_ngate is a square wave control signal of 0to vddl_1.
The control power supply for driving the output transistor in the main circuit is not a VDDL power supply independent of VDDH any more, but is a power supply vddl_1 obtained by dividing a first power supply (such as VDDH), and under different PVT conditions, vddl_1 can dynamically change along with the power supply VDDH and is affected by different PVT conditions.
The gate-source voltage |VGS| of the P1 tube is VDDH-VDDL_1, the |VGS| of the P2 tube is vp1-VDDL_1, the |VGS| of the N1 tube is VDDL_1-vn1, the |VGS| of the N2 tube is VDDL_1, wherein vp1 is the voltage of the source end of the P2 tube, vp1 is approximately equal to VDDH, vn1 is the voltage of the source end of the N1 tube, and vn1 is approximately equal to 0. Assuming that vddl_1 is 0.5×vddh, so that the gate source voltage |vgs| of the PMOS transistor is 0.5×vddhmin to 0.5×vddhmax, and the gate source voltage |vgs| of the NMOS transistor is also 0.5×vddhmin to 0.5×vddhmax, since the gate source voltage |vgs| of the NMOS transistor is equal to the gate source voltage |vgs| of the PMOS transistor, the on-resistance of the NMOS transistor is equal to the on-resistance of the PMOS transistor under different PVT conditions, that is, the on-resistance of the driving pull-up branch is equal to the on-resistance of the driving pull-down branch under different PVT conditions, so that the pull-up capability and the pull-down capability of the driving main circuit are equal under different PVT conditions. The on-resistance of the NMOS tube is equal to that of the PMOS tube under different PVT conditions, so that the pull-up capacity and the pull-down capacity of the drive circuit are the same, and the output signal quality of the drive circuit is improved.
The on-resistance formula of the MOS transistor working in the linear region is as follows:
Mu is the carrier mobility of the MOS tube, cox is the capacitance of the MOS gate oxide layer, W is the channel width of the MOS tube, L is the channel length of the MOS tube, |VGS| is the gate-source voltage of the MOS tube, and VTH is the threshold voltage of the MOS tube.
Meanwhile, the on-resistance of the PMOS tube has small deviation relative to the traditional driving circuit under different PVT conditions, and the minimum gate-source voltage of the PMOS tube is changed from (VDDHmin-VDDLmax) to 0.5 xVDDH min relative to the traditional driving circuit under different PVT conditions, the gate-source voltage of the PMOS tube of the driving main circuit is larger, so that the maximum on-resistance of the PMOS tube is smaller than that of the traditional driving circuit, and the area of the driving circuit layout can be reduced when the effect same as that of the maximum output resistance of the driving pull-up branch of the traditional driving circuit is obtained. It should be noted that, under different PVT conditions, the influence on the power supply voltage is large, the fluctuation range can reach 10%, that is, the voltage values under different PVT conditions can fluctuate within 10% of the standard value, for example, assuming that the standard value is 2, the maximum value can be 2.2, and the minimum value is 1.8.
For better understanding, the application is illustrated below with respect to the gate-source voltage of the PMOS transistor of the conventional driving circuit, if VDDH is 4, and vddl=0.5 VDDH is also assumed, then VDDHmin =4×0.9=3.6, vddlmax=2×1.1=2.2, and the minimum gate-source voltage of the PMOS transistor of the conventional driving circuit VDDHmin-VDDLmax =3.6-2.2=1.4, and the minimum gate-source voltage of the PMOS transistor of the application is 0.5×vddhmin=0.5×3.6=1.8, compared with the conventional driving circuit, the gate-source voltage of the PMOS transistor of the driving main circuit of the application is larger, so that the maximum on-resistance of the PMOS transistor is smaller than that of the conventional driving circuit.
The first end of the voltage dividing circuit is used for being connected with the first power supply VDDH, the second end of the voltage dividing circuit is grounded, the output end of the voltage dividing circuit is connected with the driving main circuit, and the voltage dividing circuit is used for outputting a control power supply serving as an output transistor (a transistor P2 and a transistor N1) in the driving main circuit.
In an alternative embodiment, the voltage dividing circuit comprises a voltage dividing basic circuit and an operational amplifier, and the circuit schematic diagram of the voltage dividing basic circuit and the operational amplifier is shown in fig. 3. The first end of the voltage division basic circuit is used for being connected with a first power supply, the second end of the voltage division basic circuit is grounded, and the voltage division basic circuit is used for outputting an internal power supply. The first input end of the operational amplifier is connected with the output end of the voltage division basic circuit, the second input end of the operational amplifier is connected with the output end of the operational amplifier, and the output end of the operational amplifier is output as a control power supply for driving an output transistor in the main body circuit. Optionally, the first input terminal of the operational amplifier is a non-inverting input terminal, and the second input terminal of the operational amplifier is an inverting input terminal. The above-mentioned operational amplifier is equivalent to a unity gain buffer circuit, and by further adding a unity gain buffer circuit, it is able to provide sufficient driving capability to enhance the driving capability of the voltage division basic circuit.
In an embodiment where the voltage dividing base circuit includes only one output terminal, the voltage dividing base circuit includes a first current limiting device (as denoted by R3) and a second current limiting device (as denoted by R4), and the circuit schematic is shown in fig. 4. The first end of the first current limiting device is connected with a first power supply, the second end of the first current limiting device is grounded through the second current limiting device, the second end of the first current limiting device is also connected with the first input end of the operational amplifier, and the second end of the first current limiting device is the output end of the voltage dividing basic circuit. Optionally, the resistance of the first current limiting device is consistent with the resistance of the second current limiting device, such that vddl_1 is 0.5×vddh.
Considering that the vp1 voltage is not completely equal to VDDH, and the vn1 voltage is not completely equal to 0, that is, the voltages of the source end and the substrate end of the P2 tube and the source end and the substrate end of the N1 tube are not equal, due to the influence of the MOS transistor body effect, the threshold voltages of the P2 tube and the N1 tube may be increased, and the on-resistance of the P2 tube and the N1 tube may be increased. In order to counteract the effect of the threshold voltage on the on-resistance, the voltage divider circuit may be utilized to generate 2 internal power supplies vddl_1 and vddl_2, wherein vddl_1 is equal to (0.5×vddh-V1) and vddl_2 is equal to (0.5×vddh+v2) to eliminate the body effect.
Wherein V1 is a first preset threshold, V2 is a second preset threshold, optionally v1=vddh-vp1+Δvth, v2=vn1+Δvth, Δvth is a threshold voltage variation, where vp1 is the voltage at the source end of the P2 tube, vn1 is the voltage at the source end of the N1 tube,Gamma is the bulk effect coefficient, VSB is the source-liner voltage difference, Φ F＝(kT/q)ln(Nsub/ni), k is the boltzmann constant, T is the temperature, q is the charge, N sub is the doping concentration of the substrate, and ni is the intrinsic carrier concentration. Since Δvth is small and negligible, v1=vddh-vp 1 and v2=vn 1 in one embodiment.
In yet another embodiment, the voltage dividing base circuit includes a first output terminal for outputting the first internal power supply (vddl_1) and a second output terminal for outputting the second internal power supply (vddl_2), and the operational amplifier includes a first operational amplifier (e.g., buffer 1) and a second operational amplifier (e.g., buffer 2), and the circuit schematic is shown in fig. 5. The first input end of the first operational amplifier is connected with the first output end, the second input end of the first operational amplifier is connected with the output end of the first operational amplifier, and the output end of the first operational amplifier is output as a control power supply for driving an output transistor (P2) in a pull-up branch in a main driving circuit. The first input end of the second operational amplifier is connected with the second output end, the second input end of the second operational amplifier is connected with the output end of the second operational amplifier, and the output end of the second operational amplifier is output as a control power supply for driving an output transistor (N1) in a pull-down branch in a main driving circuit.
In one embodiment, when the voltage division basic circuit comprises 2 output ends, the voltage division basic circuit comprises a first current limiting device (shown as R3), a second current limiting device (shown as R4) and a third current limiting device (shown as R5), and the circuit schematic diagram of the voltage division basic circuit is shown in FIG. 6. The first end of the first current limiting device is connected with a first power supply, the second end of the first current limiting device is connected with the first end of the second current limiting device, the second end of the second current limiting device is grounded through the third current limiting device, the second end of the first current limiting device is also connected with the first input end of the second operational amplifier, the second end of the first current limiting device is a second output end, the second end of the second current limiting device is also connected with the first input end of the first operational amplifier, and the second end of the second current limiting device is a first output end.
In yet another embodiment, where the voltage dividing base circuit includes 2 outputs, the voltage dividing base circuit includes a first current limiting device (as indicated by R3), a second current limiting device (as indicated by R4), a third current limiting device (as indicated by R5), and a fourth current limiting device (as indicated by R6), the circuit schematic of which is shown in FIG. 7. The first end of the third current limiting device is connected with the first power supply, the second end of the third current limiting device is grounded through a fourth current limiting device, the second end of the third current limiting device is also connected with the first input end of the second operational amplifier, and the second end of the third current limiting device is the second output end.
The current limiting device in the voltage dividing basic circuit can be a resistor, a MOS tube, a diode and the like. If the current limiting device is a MOS tube, the drain electrode and the grid electrode of the MOS tube are used as one connecting terminal together, and the source electrode of the MOS tube is used as the other connecting terminal. The MOS tube can be an NMOS tube or a PMOS tube, when the MOS tube is an NMOS tube, the drain electrode and the grid electrode of the MOS tube are grounded, the source electrode of the MOS tube is connected with a first power supply, when the MOS tube is a PMOS tube, the drain electrode and the grid electrode of the MOS tube are connected with the first power supply, and the source electrode of the MOS tube is grounded.
It should be noted that, in an alternative embodiment, the voltage dividing circuit may include only the voltage dividing base circuit. At this time, the voltage dividing circuit is equivalent to the voltage dividing base circuit, and therefore the voltage dividing circuit including the voltage dividing base circuit and the operational amplifier described above is not to be construed as limiting the present application.
Based on the same inventive concept, the embodiment of the application also provides an IO interface circuit, which comprises a control logic circuit and the self-adaptive driving circuit. The control logic circuit is used for providing a driving signal for the adaptive driving circuit. For example, the control logic circuit is configured to provide the pre_pgate drive signal and the pre_ngate drive signal to the adaptive drive circuit in fig. 2.
The implementation principle and the generated technical effects of the adaptive driving circuit provided by the embodiment of the IO interface circuit are the same as those of the embodiment of the adaptive driving circuit, and for the sake of brief description, reference may be made to the corresponding content in the embodiment of the adaptive driving circuit where the embodiment of the IO interface circuit is not mentioned.
Based on the same inventive concept, the embodiment of the application also provides an IO interface chip, which is integrated with the self-adaptive driving circuit. The IO interface chip may be various IO interface chips commonly used at present, such as a memory, a processor and the like.
The Processor may be a general-purpose Processor including a central processing unit (Central Processing Unit, CPU), a network Processor (Network Processor, NP), a digital signal Processor (DIGITAL SIGNAL Processor, DSP), an Application SPECIFIC INTEGRATED Circuit (ASIC), and a field programmable gate array (Field Programmable GATE ARRAY, FPGA). A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The Memory may be, but is not limited to, random access Memory (Random Access Memory, RAM), read Only Memory (ROM), programmable Read Only Memory (Programmable Read-Only Memory, PROM), erasable Read Only Memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable Read Only Memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.
The implementation principle and the generated technical effects of the adaptive driving circuit provided by the embodiment of the IO interface chip are the same as those of the embodiment of the adaptive driving circuit, and for the sake of brief description, reference may be made to corresponding contents in the embodiment of the adaptive driving circuit where the embodiment of the IO interface chip is not mentioned.
Based on the same inventive concept, the embodiment of the application also provides electronic equipment, which comprises a body and the IO interface circuit or the IO interface chip. The electronic device may be any electronic device including an IO interface circuit or an IO interface chip, for example, may be a mobile phone, a tablet, a computer, a server, or the like.
The implementation principle and the technical effects of the adaptive driving circuit provided by the embodiment of the electronic device are the same as those of the embodiment of the adaptive driving circuit, and for the parts, which are not mentioned in the embodiment section of the electronic device, reference may be made to the corresponding parts in the embodiment of the adaptive driving circuit.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (8)

1. An adaptive drive circuit, comprising:
The driving main circuit is used for outputting a driving signal, wherein a power supply of the driving main circuit is a first power supply, the driving main circuit comprises a driving pull-up branch and a driving pull-down branch which are connected in parallel, the driving pull-up branch comprises a P-type output transistor, the driving pull-down branch comprises an N-type output transistor, and the P-type output transistor and the N-type output transistor are output transistors in the driving main circuit;
The first end of the voltage dividing circuit is used for being connected with a first power supply, the second end of the voltage dividing circuit is grounded, the output end of the voltage dividing circuit is connected with the driving main circuit, the voltage dividing circuit is used for outputting a control power supply serving as an output transistor in the driving main circuit, and the gate source voltage of the P-type output transistor is the same as the gate source voltage of the N-type output transistor, so that the pull-up capacity and the pull-down capacity of the driving main circuit are consistent under different PVT conditions;
The magnitude of the control power outputted by the voltage dividing circuit as the output transistor in the driving pull-up branch is 0.5×vddh-V1, the magnitude of the control power outputted by the voltage dividing circuit as the output transistor in the driving pull-down branch is 0.5×vddh+v2, VDDH is the first power supply, V1 is a first preset threshold and VDDH-vp1, V2 is a second preset threshold and vn1, vp1 is the source voltage of the P-type output transistor, and vn1 is the source voltage of the N-type output transistor.
2. The adaptive driving circuit according to claim 1, wherein the voltage dividing circuit includes:
The voltage division basic circuit comprises a first output end and a second output end, wherein the first end of the voltage division basic circuit is used for being connected with the first power supply, the second end of the voltage division basic circuit is grounded, the voltage division basic circuit comprises the first output end and the second output end, the first output end is used for outputting a first internal power supply, and the second output end is used for outputting a second internal power supply;
the first input end of the first operational amplifier is connected with the first output end, the second input end of the first operational amplifier is connected with the output end of the first operational amplifier, and the output end of the first operational amplifier is output to serve as a control power supply of an output transistor in a driving pull-up branch in the driving main body circuit;
The first input end of the second operational amplifier is connected with the second output end, the second input end of the second operational amplifier is connected with the output end of the second operational amplifier, and the output end of the second operational amplifier is output as a control power supply of an output transistor in a driving pull-down branch in the driving main body circuit.
3. The adaptive driving circuit according to claim 2, wherein the voltage dividing base circuit includes:
A first current limiting device, a second current limiting device, a third current limiting device;
The first end of the first current limiting device is connected with the first power supply, the second end of the first current limiting device is connected with the first end of the second current limiting device, the second end of the second current limiting device is grounded through the third current limiting device, the second end of the first current limiting device is also connected with the first input end of the second operational amplifier, the second end of the first current limiting device is the second output end, the second end of the second current limiting device is also connected with the first input end of the first operational amplifier, and the second end of the second current limiting device is the first output end.
4. The adaptive driving circuit according to claim 2, wherein the voltage dividing base circuit includes:
The first end of the first current limiting device is connected with the first power supply, the second end of the first current limiting device is grounded through the second current limiting device, the second end of the first current limiting device is also connected with the first input end of the first operational amplifier, and the second end of the first current limiting device is the first output end;
the first end of the third current limiting device is connected with the first power supply, the second end of the third current limiting device is grounded through the fourth current limiting device, the second end of the third current limiting device is also connected with the first input end of the second operational amplifier, and the second end of the third current limiting device is the second output end.
5. The adaptive driving circuit according to claim 2, wherein the magnitude of the control power outputted by the first operational amplifier as the output transistor in the driving pull-up branch is 0.5×vddh-V1, and the magnitude of the control power outputted by the second operational amplifier as the output transistor in the driving pull-down branch is 0.5×vddh+v2, vddh being the first power.
6. An IO interface circuit comprising control logic circuitry and an adaptive drive circuit according to any one of claims 1 to 5, the control logic circuitry being arranged to provide drive signals to the adaptive drive circuit.
7. An IO interface chip integrated with the IO interface circuit of claim 6.
8. An electronic device comprising a body and the IO interface circuit of claim 6 or the IO interface chip of claim 7.
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