CN114220871A - Vertical III-nitride power semiconductor device structure with groove isolation layer and preparation method thereof - Google Patents
Vertical III-nitride power semiconductor device structure with groove isolation layer and preparation method thereof Download PDFInfo
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Abstract
The invention provides a vertical III-nitride power semiconductor device structure with a groove isolation layer, which sequentially comprises the following components from top to bottom: the cathode electrode, heavily doped N type nitride substrate region, lightly doped N type nitride drift region, heavily doped P type nitride district, anode electrode, be provided with the isolation layer between heavily doped P type nitride district and the vertical contact surface of lightly doped N type nitride drift region. The arrangement of the trench isolation layer structure optimizes the electric field distribution in the device, effectively improves the reverse performance of the device and ensures the excellent forward characteristic.
Description
Technical Field
The invention relates to a vertical III-nitride power semiconductor device structure with a groove isolation layer and a preparation method thereof, belonging to the technical field of semiconductor devices.
Background
Third-generation semiconductors represented by silicon carbide and group III nitrides have a wide application prospect in the fields of high-frequency communication, power electronics, and the like, because of their excellent characteristics such as large forbidden band width, high critical breakdown field strength, high thermal conductivity, high electron saturation drift rate, and the like, as compared with first-generation semiconductors represented by silicon and second-generation semiconductors represented by gallium arsenide.
At present, a nitride device that can be widely used is mainly a gallium nitride-based lateral High Electron Mobility Transistor (HEMT). However, the main disadvantage of the lateral device is that the reverse breakdown voltage of the device is proportional to the electrode spacing in the lateral direction of the device, which results in a larger device size in high-voltage working scene applications, which greatly increases the process manufacturing cost of the device. In order to solve the problem, the full-vertical device can realize larger reverse breakdown voltage by increasing the thickness of a vertical drift layer of the device, simultaneously effectively avoid the current crowding effect in a transverse structure and a quasi-vertical structure, and reduce the forward on-resistance.
Schottky barrier diodes are important components of modern power electronic systems because they have the advantages of reduced voltage, fast switching speed, etc. In order to meet the application of consumer electronics and high-frequency communication devices, higher requirements are put forward on the traditional Schottky diode in the application scenes of high voltage and high power, and the performance limit of the device is more and more prominent. In a high reverse bias scenario, the Schottky Barrier Diode (SBD) tends to generate a significant barrier lowering effect due to the accumulation of a strong electric field under the schottky contact barrier, thereby generating a large reverse leakage current, which limits the reverse breakdown characteristics of the schottky barrier diode.
The above problems can be solved by adopting a hybrid PiN junction barrier schottky diode (MPS diode) new structure. Compared with the traditional plane Schottky barrier diode, the gallium nitride vertical type mixed PiN junction barrier Schottky diode can effectively modulate the electric field distribution below the Schottky contact barrier, and can form good electric field shielding effect on the Schottky contact barrier by utilizing the superposition of depletion regions of adjacent PN junctions, thereby avoiding the problems of large leakage current and early breakdown caused by barrier reduction effect. However, if a good depletion region protection is to be formed, the distance between adjacent PN junctions is required to be designed to be as small as possible, and a small channel width will exhibit a large forward on-resistance under forward bias conditions, which is not favorable for forward conduction of the device.
The present invention has been made to solve the above problems.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a vertical III-nitride power semiconductor device structure with a groove isolation layer and a preparation method thereof by adjusting the distance between adjacent PN junctions on the premise of effectively ensuring that the forward characteristic is not degraded. The arrangement of the trench isolation layer structure optimizes the electric field distribution in the device, effectively improves the reverse performance of the device and ensures the excellent forward characteristic.
The technical scheme of the invention is as follows:
a vertical III-nitride power semiconductor device structure with a trench isolation layer, comprising in order from the bottom: the cathode electrode, heavily doped N type nitride substrate region, lightly doped N type nitride drift region, heavily doped P type nitride district, anode electrode, be provided with the isolation layer between heavily doped P type nitride district and the vertical contact surface of lightly doped N type nitride drift region.
Preferably, according to the invention, the isolation layer is silicon dioxide, silicon nitride, hafnium oxide, aluminum nitride or aluminum oxide.
According to the invention, preferably, isolation layers are arranged between two vertical contact surfaces of the heavily doped P-type nitride region and the lightly doped N-type nitride drift region, and the transverse thickness of each isolation layer is 50 nm-300 nm; preferably, the lateral thickness of each spacer layer is 50nm to 150nm, more preferably 50 nm.
According to the invention, the lightly doped N-type nitride drift region is preferably composed of a lightly doped N-type nitride drift layer and a lightly doped N-type nitride protrusion; the lightly doped N-type nitride protrusion is of a cuboid structure, the lightly doped N-type nitride protrusion is arranged in the middle position above the lightly doped N-type nitride drift layer along the length direction of the lightly doped N-type nitride drift layer, and the lightly doped N-type nitride protrusion and the lightly doped N-type nitride drift layer form a convex vertical section; the heavily doped P-type nitride regions are arranged on the two sides of the lightly doped N-type nitride protrusion and on the upper surface of the lightly doped N-type nitride drift layer, and the thickness of the heavily doped P-type nitride regions is the same as that of the lightly doped N-type nitride protrusion.
Preferably, the thickness of the lightly doped N-type nitride protrusion is 0.5-3.0 μm, and the width is 1-10 μm; preferably, the width of the lightly doped N-type nitride protrusion is 1 μm to 5 μm, and more preferably 1 μm.
Preferably, the height of the isolation layer is the same as the thickness of the lightly doped N-type nitride protrusion.
Preferably, the sum of the width of one side of the heavily doped P-type nitride region, the thickness of the single isolation layer, and half of the width of the lightly doped N-type nitride protrusion is equal to half of the width of the lightly doped N-type nitride drift layer.
Preferably, the doping element of the heavily doped P-type nitride region is magnesium ion, and the effective doping concentration is 1e16cm-3～3e17cm-3(ii) a Preferably, the effective doping concentration is 1e16cm-3～2e17cm-3More preferably 1e17cm-3。
According to the invention, the doping element of the lightly doped N-type nitride drift region is preferably silicon, and the doping concentration is 5 x 1014～3×1016cm-3Preferably, the doping concentration is 2e16cm-3。
According to a preferred embodiment of the present invention, the anode electrode includes a schottky contact anode electrode and an ohmic contact anode electrode; the Schottky contact anode electrode is arranged on the top surface of the lightly doped N-type nitride drift region and the upper surface of the isolation layer; the ohmic contact anode electrode is arranged on the upper surface of the heavily doped P-type nitride region.
Preferably, the heavily doped N-type nitride substrate region is a heavily doped N-type gallium nitride substrate region, the lightly doped N-type nitride drift region is a lightly doped N-type gallium nitride drift region, and the heavily doped P-type nitride region is a heavily doped P-type gallium nitride region.
According to the invention, the parameters of the material types, the thicknesses and the like of the cathode electrode, the heavily doped N-type nitride substrate region, the lightly doped N-type nitride drift region, the anode electrode and the like can be obtained according to the prior art.
The preparation method of the vertical III-nitride power semiconductor device structure with the groove isolation layer comprises the following steps:
(1) preparing a heavily doped N-type nitride substrate region by using an MOCVD method;
(2) homoepitaxy lightly doped N-type nitride drift regions on the heavily doped N-type nitride substrate region by using an MOCVD method;
(3) etching groove regions on two sides of the upper surface of the lightly doped N-type nitride drift region by using a dry etching process; then carrying out damage treatment on the etched surface;
(4) depositing an isolation layer at the bottom and the side wall of the trench by Plasma Enhanced Chemical Vapor Deposition (PECVD), and then removing the isolation layer at the bottom of the trench by anisotropic Reactive Ion Etching (RIE);
(5) epitaxially growing a heavily doped P-type nitride region at the bottom of the trench;
(6) and preparing a cathode electrode and an anode electrode by using an electron beam evaporation plating instrument.
Preferably, in step (4), the reaction gas of the Plasma Enhanced Chemical Vapor Deposition (PECVD) chamber is hydrogen diluted Silane (SiH)4) And oxygen (O)2)。
Preferably, in step (4), the reactant of anisotropic Reactive Ion Etching (RIE) is boron trichloride (BCl)3) And chlorine (Cl)2)。
Preferably, in step (5), the step of growing the heavily doped P-type nitride region by using the MOCVD method includes:
firstly, silicon dioxide is used as a hard mask to shield the top surface of an unetched lightly doped N-type nitride drift region and the upper surface of an isolation layer, ammonia is respectively used as a nitrogen source, magnesium chloride is used as a doping source, and H2As a carrier gas, a layer of P-type nitride is homoepitaxially grown on the upper surfaces of the lightly doped N-type nitride drift regions and on two sides of the isolation layer by adopting an MOCVD method;
secondly, annealing in situ in the MOCVD furnace, activating P-type doped magnesium ions, and growing to form a heavily doped P-type nitride region; the annealing temperature is 400-1500 ℃, and the annealing time is 10-90 min.
Preferably, in step (5), the step of growing the heavily doped P-type nitride region by using a multiple epitaxy and ion implantation process comprises:
firstly, silicon dioxide is used as a hard mask to shield the top surface of an unetched lightly doped N-type nitride drift region and the upper surface of an isolation layer, ammonia is respectively used as a nitrogen source, and SiH is used as3CH3As a doping source, H2As a carrier gas, MOCVD method is adoptedA layer of N-type nitride is epitaxially grown on the upper surfaces of the lightly doped N-type nitride drift regions on both sides of the isolation layer, and the doping concentration of silicon is 5 × 1014～3×1016cm-3Preferably, the doping concentration is 2e16cm-3；
Utilizing an ion implanter to implant Mg ions in the N-type nitride region formed in the step I;
thirdly, performing rapid thermal annealing treatment in the gas atmosphere of one or more than two of nitrogen, ammonia, argon and hydrogen in any proportion; the annealing temperature is 400-1500 ℃, and the annealing time is 10-90 min;
and fourthly, repeating the steps from the first step to the third step until the heavily doped P-type nitride region with the specified thickness is generated.
Preferably, in step (5), the step of growing the heavily doped P-type nitride region by using a low temperature Pulse Sputter Deposition (PSD) process comprises: .
Firstly, silicon dioxide is used as a hard mask to shield the top surface of an unetched lightly doped N-type nitride drift region and the upper surface of an isolation layer, ammonia is respectively used as a nitrogen source, magnesium chloride is used as a doping source, and H2As carrier gas, a layer of P-type nitride is homoepitaxially grown on the upper surfaces of the lightly doped N-type nitride drift regions and on two sides of the isolation layer by adopting a PSD (position sensitive detector) method;
secondly, activating P-type doped magnesium ions through in-situ annealing in the furnace, and growing to form a heavily doped P-type nitride region; the annealing temperature is 400-1500 ℃, and the annealing time is 10-90 min.
Other processes of the invention are carried out according to the prior art.
The invention has the following technical characteristics and beneficial effects:
1. the invention provides a nitride vertical type mixed PiN junction barrier Schottky diode with a groove isolation layer, which effectively improves the reverse characteristic, and has the following specific beneficial effects: under the condition of reverse bias, the critical breakdown electric field intensity of the isolation layer with high forbidden band width is high, and the difference of dielectric constants can attract and bear a strong electric field, so that the electric field distribution in the device is optimized, and the reverse performance of the device is effectively improved; due to the existence of the groove isolation layer, electric field shielding protection of the Schottky barrier electrode is enhanced, the device structure can have wider transverse Schottky electrode width, the forward on-resistance is reduced to a great extent, and the forward performance is improved.
2. The preparation method of the invention is applicable to group III nitride systems, the process is relatively simple, and the specific process conditions, deposition temperatures, and the like are well known to those skilled in the art.
3. According to the invention, the structural parameters of the device are analyzed by means of TCAD simulation assistance, so that a large amount of time and cost can be saved, and the preparation of the subsequent process can be better guided.
4. The optimal electrical breakdown characteristic of the hybrid Pin junction barrier Schottky diode is realized by continuously optimizing structural parameters (the doping concentration of the heavily doped P-type nitride region, the Schottky contact width and the transverse thickness of the isolating layer). Through a large amount of simulation calculation analysis, in the nitride vertical type mixed Pin junction barrier Schottky diode structure with the trench isolation layer, the reverse voltage endurance capability of the device can be greatly improved on the premise of keeping the size of the device unchanged, so that the device can be applied to a higher voltage scene. Therefore, the nitride vertical type hybrid Pin junction barrier Schottky diode structure with the trench isolation layer is very promising to be applied to high-frequency, high-voltage and high-power electronic and integrated systems in the future, and the gallium nitride vertical type power device is shown to be a new generation of ideal substitute products for breaking through the physical limit of the traditional power device.
Drawings
Fig. 1 is a schematic structural view of a vertical group iii gallium nitride power semiconductor device having a trench isolation layer according to example 1;
fig. 2 is a schematic structural view of a conventional gallium nitride vertical-type power semiconductor device in comparative example 1;
FIG. 3 is a graph showing the relationship between the doping concentration of the heavily doped P-type nitride region and the reverse breakdown voltage of the device in test example 1;
FIG. 4 is a graph showing the relationship between the Schottky contact anode electrode width and the device reverse breakdown voltage in test example 2;
fig. 5 is a graph of the lateral thickness of the isolation layer and the reverse breakdown voltage of the device in experimental example 3.
Detailed Description
The invention is described in further detail below with reference to the figures and the embodiments.
The methods mentioned in the examples are all the existing methods unless otherwise specified; the reagents and materials used are commercially available, unless otherwise specified.
Example 1
A vertical III-group gallium nitride power semiconductor device structure with a groove isolation layer is shown in figure 1 and sequentially comprises a cathode electrode, a heavily doped N-type gallium nitride substrate region, a lightly doped N-type gallium nitride drift region, a heavily doped P-type gallium nitride region and an anode electrode from bottom to top; isolation layer silicon dioxide is respectively arranged between two vertical contact surfaces of the heavily doped P-type gallium nitride region and the lightly doped N-type gallium nitride drift region, the transverse thickness of each isolation layer is 50nm, and the height of each isolation layer is 1.5 mu m.
The doping element of the lightly doped N-type gallium nitride drift region is silicon, and the doping concentration is 2e16cm-3. The lightly doped N-type gallium nitride drift region consists of a lightly doped N-type gallium nitride drift layer and a lightly doped N-type gallium nitride protrusion; the lightly doped N-type gallium nitride protrusion is of a cuboid structure, the lightly doped N-type gallium nitride protrusion is arranged in the middle position above the lightly doped N-type gallium nitride drift layer along the length direction of the lightly doped N-type gallium nitride drift layer, and the lightly doped N-type gallium nitride protrusion and the lightly doped N-type gallium nitride drift layer form a convex vertical section. The thickness of the lightly doped N-type gallium nitride drift layer is 13.5 mu m, the thickness of the lightly doped N-type gallium nitride protrusion is 1.5 mu m, the width of the lightly doped N-type gallium nitride protrusion is 1 mu m, and the length of the lightly doped N-type gallium nitride protrusion is the same as that of the lightly doped N-type gallium nitride drift layer.
The heavily doped P-type gallium nitride regions are arranged on the upper surface of the lightly doped N-type gallium nitride drift layer and on two sides of the lightly doped N-type gallium nitride protrusion, the thickness of the heavily doped P-type gallium nitride regions is the same as that of the lightly doped N-type gallium nitride protrusion, and the heavily doped P-type gallium nitride regions are 1.5 mu m. The doping element of the heavily doped P-type gallium nitride region is magnesium ion, and the effective doping concentration is 1e17cm-3。
The sum of the width of one side of the heavily doped P-type nitride region, the thickness of the single isolation layer, and half of the width of the lightly doped N-type nitride protrusion is equal to half of the width of the lightly doped N-type nitride drift layer.
The cathode electrode is: Ti/Al/Ni/Au, corresponding to a thickness of 20/150/50/60 nm.
The doping source of the heavily doped N-type gallium nitride substrate region is silicon, and the doping concentration is 5e18cm-3The thickness was 2 μm.
The anode electrode comprises a Schottky contact anode electrode and an ohmic contact anode electrode, the anode electrode is made of Pd/Au, and the corresponding thickness is 20/100 nm; the Schottky contact anode electrode is arranged on the top surface of the lightly doped N-type gallium nitride drift region and the upper surface of the isolation layer; the ohmic contact anode electrode is arranged on the upper surface of the heavily doped P-type gallium nitride region.
Example 2
A method for fabricating a vertical iii-gan power semiconductor device structure with a trench isolation layer as in embodiment 1, wherein a heavily doped P-type gan region is grown by a double epitaxy process, comprising the steps of:
(1) using trimethyl gallium (TMGa), ammonia (NH) respectively3) As Ga source and N source, SiH3CH3As a source of N-type impurities, H2As carrier gas, heavily doped N-type GaN substrate region with low defect and low dislocation and silicon doping concentration of 5e18cm with thickness of 2 μm is realized in MOCVD-3；
(2) Using trimethyl gallium (TMGa), ammonia (NH) respectively3) As Ga source and N source, SiH3CH3As a source of N-type impurities, H2As carrier gas, a layer of lightly doped N-type gallium nitride drift region with the thickness of 15 μm is homoepitaxially formed on the surface of the heavily doped N-type gallium nitride substrate region by using the MOCVD method, and the doping concentration of silicon is 2e16cm-3；
(3) Utilization of SiO on epitaxial wafers2As a hard mask plate, the mask plate can shield part of the epitaxial wafer from being etchedIn Cl2/BCl3Etching the stepped groove region by utilizing Inductively Coupled Plasma (ICP) in the mixed atmosphere of/Ar;
(4) after dry etching, a large amount of peaks and burrs with slopes exist on the surface of the material, a sample is placed into 25 wt% of TMAH solution, and the sample is treated at 85 ℃ for 1 hour to remove surface damage caused by etching: then putting the sample into acetone to be heated to 85 ℃, and heating in a water bath for 10 minutes; ultrasonically cleaning the isopropanol for 5 minutes, flushing the isopropanol for 6 times by using deionized water, drying the isopropanol by using a hot plate after blowing dry by using nitrogen; heating an ammonia water solution with the concentration of 25 wt% to 85 ℃ in a water bath, putting the sample into the water bath, and heating the sample in the water bath for 10 minutes; taking out a sample from the ammonia water, washing the sample for 6 times by using deionized water, removing the ammonia water on the surface, stopping the surface treatment effect of the ammonia water, drying the sample by using a hot plate after drying; testing the etching depth and the etching appearance by using an atomic force microscope;
(5) depositing an isolation layer on the bottom and the side wall of the trench by Plasma Enhanced Chemical Vapor Deposition (PECVD), wherein the reaction gas of the chamber is hydrogen diluted Silane (SiH)4) And oxygen (O)2) Then using anisotropic Reactive Ion Etching (RIE) to remove the isolation layer at the bottom of the trench, wherein the reactant is boron trichloride (BCl)3) And chlorine (Cl)2)；
(6) Carrying out secondary epitaxial growth of a heavily-doped P-type gallium nitride region by using MOCVD (metal organic chemical vapor deposition), wherein the material layers have clear outlines and are uniformly distributed, and the method comprises the following steps:
firstly, silicon dioxide is used as a hard mask to shield the top surface of an unetched lightly doped N-type gallium nitride drift region and the upper surface of an isolation layer, ammonia gas is used as a nitrogen source, magnesium chloride is used as a doping source, trimethyl gallium (TMGa) is used as a Ga source, H and H are used as Ga sources2As carrier gas, a layer of P-type gallium nitride is epitaxially grown on the upper surfaces of the lightly doped N-type gallium nitride drift regions and on two sides of the isolation layer in a homogeneous manner by adopting an MOCVD method;
secondly, annealing in situ in the MOCVD furnace, activating P-type doped magnesium ions, and growing to form a heavily doped P-type gallium nitride region; the annealing temperature is 850 ℃, the annealing time is 25min, and the annealing atmosphere is nitrogen.
(7) And preparing a cathode electrode and an anode electrode by using an electron beam evaporation plating instrument.
Example 3
A method of fabricating the vertical iii-gan power semiconductor device structure with trench isolation layer of embodiment 1, as described in embodiment 2, except that: in the step (6), a heavily doped P-type gallium nitride region is grown by utilizing a process of multiple times of epitaxy and ion implantation, and the specific steps are as follows:
firstly, silicon dioxide is used as a hard mask to shield the top surface of an unetched lightly doped N-type gallium nitride drift region and the upper surface of an isolation layer, ammonia is respectively used as a nitrogen source, and SiH is used as3CH3As doping source, trimethylgallium (TMGa) as Ga source, H2As carrier gas, a layer of N-type gallium nitride with the thickness of 0.3-0.6 μm is homoepitaxially grown on the upper surfaces of the lightly doped N-type gallium nitride drift regions and on both sides of the isolation layer by using an MOCVD method, and the doping concentration of silicon is 2e16cm-3；
Utilizing an ion implanter to implant Mg ions in the N-type gallium nitride region formed in the step I; setting the power energy of ion implantation to be 150-300 keV and the implantation depth to be 0.3-0.6 μm;
thirdly, carrying out rapid thermal annealing treatment in a nitrogen atmosphere; the annealing temperature is 850 ℃, the annealing time is 25min, and the annealing atmosphere is nitrogen.
And fourthly, repeating the steps from the first step to the third step until a heavily doped P-type gallium nitride region with the specified thickness of 1.5 mu m is generated.
The ion implantation process has no interface between the implanted layer and the substrate, high binding strength, high adhesion and no change in the size and surface smoothness of the device.
The other steps and conditions were identical to those of example 2.
Example 4
A method of fabricating the vertical iii-gan power semiconductor device structure with trench isolation layer of embodiment 1, as described in embodiment 2, except that: in the step (6), a heavily doped P-type gallium nitride region is grown by using a low-temperature Pulse Sputtering Deposition (PSD) process, and the specific steps are as follows:
utilizeSilicon dioxide is used as a hard mask to shield the top surface of the unetched lightly doped N-type gallium nitride drift region and the upper surface of the isolation layer, ammonia gas is used as a nitrogen source, magnesium cyclopentadienyl is used as a doping source, trimethyl gallium (TMGa) is used as a Ga source, H and H are respectively used as the Ga source2As carrier gas, a layer of P-type gallium nitride is epitaxially grown on the upper surface of the lightly doped N-type gallium nitride drift region on both sides of the isolation layer by PSD method at 480 deg.C under nitrogen/argon (N)2/Ar)；
Secondly, activating P-type doped magnesium ions through in-situ annealing in the furnace, and growing to form a heavily doped P-type gallium nitride region; the annealing temperature is 850 ℃, the annealing time is 25min, and the annealing atmosphere is nitrogen.
The PSD is used for sputtering growth, the growth quality is high, and is close to the quality of MOCVD secondary epitaxial growth.
The other steps and conditions were identical to those of example 2.
Comparative example 1
A conventional group iii gan vertical power semiconductor device structure is shown in fig. 2, as described in example 1, except that: an isolation layer is not arranged between vertical contact surfaces of the heavily doped P-type gallium nitride region and the lightly doped N-type gallium nitride drift region, but is in direct contact with the heavily doped P-type gallium nitride region; the other structures and parameters were in accordance with example 1.
The concrete structure is as follows: the cathode electrode, the heavily doped N-type gallium nitride substrate region, the lightly doped N-type gallium nitride drift region, the heavily doped P-type gallium nitride region and the anode electrode are sequentially arranged from bottom to top.
The doping element of the lightly doped N-type gallium nitride drift region is silicon, and the doping concentration is 2e16cm-3. The lightly doped N-type gallium nitride drift region consists of a lightly doped N-type gallium nitride drift layer and a lightly doped N-type gallium nitride protrusion; the lightly doped N-type gallium nitride protrusion is of a cuboid structure, the lightly doped N-type gallium nitride protrusion is arranged in the middle position above the lightly doped N-type gallium nitride drift layer along the length direction of the lightly doped N-type gallium nitride drift layer, and the lightly doped N-type gallium nitride protrusion and the lightly doped N-type gallium nitride drift layer form a convex vertical section. The thickness of the lightly doped N-type GaN drift layer is 13.5 μm, and the lightly doped N-type GaNThe thickness of the protrusion is 1.5 μm, the width of the lightly doped N-type GaN protrusion is 1 μm, and the length of the lightly doped N-type GaN protrusion is the same as that of the lightly doped N-type GaN drift layer.
The heavily doped P-type gallium nitride regions are arranged on the upper surface of the lightly doped N-type gallium nitride drift layer and on two sides of the lightly doped N-type gallium nitride protrusion, and the thickness of the heavily doped P-type gallium nitride regions is equal to that of the lightly doped N-type gallium nitride protrusion and is 1.5 mu m. The doping element of the heavily doped P-type gallium nitride region is magnesium ion, and the effective doping concentration is 1e17cm-3。
The sum of the width of one side of the heavily doped P-type nitride region, the thickness of the single isolation layer, and half of the width of the lightly doped N-type nitride protrusion is equal to half of the width of the lightly doped N-type nitride drift layer.
The cathode electrode is: Ti/Al/Ni/Au, corresponding to a thickness of 20/150/50/60 nm.
The doping source of the heavily doped N-type gallium nitride substrate region is silicon, and the doping concentration is 5e18cm-3The thickness was 2 μm.
The anode electrode comprises a Schottky contact anode electrode and an ohmic contact anode electrode, the anode electrode is made of Pd/Au, and the corresponding thickness is 20/100 nm; the Schottky contact anode electrode is arranged on the top surface of the lightly doped N-type gallium nitride drift region; the ohmic contact anode electrode is arranged on the upper surface of the heavily doped P-type gallium nitride region.
The above-mentioned conventional iii-gan vertical power semiconductor device structure is prepared as described in embodiment 2, except that: step (5) is omitted; the other steps and conditions were identical to those of example 2.
Test example 1
Variation of the Mg ion doping concentration of the heavily doped P-type GaN region in example 1 (variation range 1e16 cm)-3～3e17cm-3) The relationship between the reverse breakdown voltage and the doping concentration of the resulting device is shown in fig. 3. It can be seen that, when the concentration is low, the depletion effect of the heavily doped P-type gallium nitride region is weak, which cannot play a good role in electric field shielding protection, and when the concentration is too high, local electric field aggregation occurs near the heavily doped P-type gallium nitride region,leading to premature breakdown of the device, all of which show poor reverse breakdown characteristics. Further, the optimum magnesium ion doping concentration is 1e17cm-3。
Test example 2
The schottky contact anode electrode width (varying range of 1 to 10 μm), i.e., the width of the lightly doped N-type gallium nitride protrusion, of the semiconductor devices in example 1 and comparative example 1, i.e., the MPS diode with the trench isolation layer and the MPS diode without the trench isolation layer, was varied, and the relationship between the reverse breakdown voltage and the schottky contact anode electrode width of the resulting devices was as shown in fig. 4. The Mg doping concentration of the heavily doped P-type GaN region is set to be the optimal value of 1e17cm-3. It can be seen that the increase in the width of the schottky electrode, without the trench isolation layer, results in a decrease in reverse breakdown voltage; further, the structure having the trench isolation layer will exhibit a smaller drop in reverse breakdown voltage; furthermore, the existence of the trench isolation layer can effectively improve the reverse breakdown voltage of the device.
Test example 3
The lateral thickness of the isolation layer in variation example 1 (variation range 50-300 nm), i.e., the lateral thickness of each isolation layer, the reverse breakdown voltage of the resulting device, and the lateral thickness of the isolation layer are plotted in fig. 5. The Mg doping concentration of the heavily doped P-type GaN region is set to 1e17cm-3. The larger the lateral thickness of the isolation layer is, the poorer the reverse breakdown characteristic of the device is; further, when the material of the isolation layer is silicon dioxide, the lateral thickness of the isolation layer is preferably 50 nm; furthermore, the increase of the thickness of the isolation layer can lead the depletion effect of p-GaN on the channel current carrier of the groove to be weakened, and the effect influence of the p-GaN is reduced.
Claims (10)
1. A vertical iii-nitride power semiconductor device structure with a trench isolation layer, comprising in order from the bottom: the cathode electrode, heavily doped N type nitride substrate region, lightly doped N type nitride drift region, heavily doped P type nitride district, anode electrode, be provided with the isolation layer between heavily doped P type nitride district and the vertical contact surface of lightly doped N type nitride drift region.
2. The vertical group iii nitride power semiconductor device structure with a trench isolation layer as claimed in claim 1, wherein the isolation layer is silicon dioxide, silicon nitride, hafnium oxide, aluminum nitride or aluminum oxide.
3. The vertical group iii nitride power semiconductor device structure with a trench isolation layer as claimed in claim 1, wherein an isolation layer is disposed between two vertical contact surfaces of the heavily doped P-type nitride region and the lightly doped N-type nitride drift region, each isolation layer having a lateral thickness of 50nm to 300 nm; preferably, the lateral thickness of each spacer layer is 50nm to 150nm, more preferably 50 nm.
4. The vertical group iii-nitride power semiconductor device structure with a trench isolation layer of claim 1, wherein the lightly doped N-type nitride drift region is comprised of a lightly doped N-type nitride drift layer and a lightly doped N-type nitride protrusion; the lightly doped N-type nitride protrusion is of a cuboid structure, the lightly doped N-type nitride protrusion is arranged in the middle position above the lightly doped N-type nitride drift layer along the length direction of the lightly doped N-type nitride drift layer, and the lightly doped N-type nitride protrusion and the lightly doped N-type nitride drift layer form a convex vertical section; the heavily doped P-type nitride regions are arranged on the two sides of the lightly doped N-type nitride protrusion and on the upper surface of the lightly doped N-type nitride drift layer, and the thickness of the heavily doped P-type nitride regions is the same as that of the lightly doped N-type nitride protrusion.
5. The vertical group iii nitride power semiconductor device structure with a trench isolation layer of claim 4, comprising one or more of the following conditions:
i. the thickness of the lightly doped N-type nitride protrusion is 0.5-3.0 μm, and the width is 1-10 μm; preferably, the width of the lightly doped N-type nitride protrusion is 1 μm to 5 μm, and more preferably 1 μm;
ii. The height of the isolation layer is the same as the thickness of the lightly doped N-type nitride protrusion;
iii, the sum of the width of one side of the heavily doped P-type nitride region, the thickness of the single isolation layer, and half of the width of the lightly doped N-type nitride protrusion is equal to half of the width of the lightly doped N-type nitride drift layer.
6. The structure of claim 1, wherein the heavily doped P-type nitride region is doped with magnesium ions at an effective doping concentration of 1e16cm-3～3e17cm-3(ii) a Preferably, the effective doping concentration is 1e16cm-3～2e17cm-3More preferably 1e17cm-3。
7. The vertical group iii nitride power semiconductor device structure with a trench isolation layer of claim 1, comprising one or more of the following conditions:
i. the doping element of the lightly doped N-type nitride drift region is silicon, and the doping concentration is 5 multiplied by 1014～3×1016cm-3Preferably, the doping concentration is 2e16cm-3；
ii. The anode electrode comprises a Schottky contact anode electrode and an ohmic contact anode electrode; the Schottky contact anode electrode is arranged on the top surface of the lightly doped N-type nitride drift region and the upper surface of the isolation layer; the ohmic contact anode electrode is arranged on the upper surface of the heavily doped P-type nitride region;
and iii, the heavily doped N-type nitride substrate region is a heavily doped N-type gallium nitride substrate region, the lightly doped N-type nitride drift region is a lightly doped N-type gallium nitride drift region, and the heavily doped P-type nitride region is a heavily doped P-type gallium nitride region.
8. A method of fabricating a vertical ill-nitride power semiconductor device structure with trench isolation as claimed in any of claims 1-7, comprising the steps of:
(1) preparing a heavily doped N-type nitride substrate region by using an MOCVD method;
(2) homoepitaxy lightly doped N-type nitride drift regions on the heavily doped N-type nitride substrate region by using an MOCVD method;
(3) etching groove regions on two sides of the upper surface of the lightly doped N-type nitride drift region by using a dry etching process; then carrying out damage treatment on the etched surface;
(4) depositing an isolation layer at the bottom and the side wall of the trench by Plasma Enhanced Chemical Vapor Deposition (PECVD), and then removing the isolation layer at the bottom of the trench by anisotropic Reactive Ion Etching (RIE);
(5) epitaxially growing a heavily doped P-type nitride region at the bottom of the trench;
(6) and preparing a cathode electrode and an anode electrode by using an electron beam evaporation plating instrument.
9. The method of fabricating a vertical group iii nitride power semiconductor device structure with a trench isolation layer as claimed in claim 8, comprising one or more of the following conditions:
i. in the step (4), the reaction gas of the Plasma Enhanced Chemical Vapor Deposition (PECVD) chamber is hydrogen diluted Silane (SiH)4) And oxygen (O)2)；
ii. In the step (4), the reactant of the anisotropic Reactive Ion Etching (RIE) is boron trichloride (BCl)3) And chlorine (Cl)2)。
10. The method of claim 8, wherein in step (5), the heavily doped P-type nitride region is formed by one of the following methods:
i. the step of growing the heavily doped P-type nitride region by the MOCVD method includes:
firstly, silicon dioxide is used as a hard mask to shield the top surface of an unetched lightly doped N-type nitride drift region and the upper surface of an isolation layer, ammonia is respectively used as a nitrogen source, magnesium chloride is used as a doping source, and H2As carrier gas, the MOCVD method is adopted to separate the layersA layer of P-type nitride is epitaxially grown on the upper surfaces of the lightly doped N-type nitride drift regions on two sides;
secondly, annealing in situ in the MOCVD furnace, activating P-type doped magnesium ions, and growing to form a heavily doped P-type nitride region; the annealing temperature is 400-1500 ℃, and the annealing time is 10-90 min;
ii. The step of growing the heavily doped P-type nitride region using a multiple epitaxy and ion implantation process includes:
firstly, silicon dioxide is used as a hard mask to shield the top surface of an unetched lightly doped N-type nitride drift region and the upper surface of an isolation layer, ammonia is respectively used as a nitrogen source, and SiH is used as3CH3As a doping source, H2Using MOCVD method to homoepitaxially grow a layer of N-type nitride on the upper surface of the lightly doped N-type nitride drift region on both sides of the isolation layer as carrier gas, wherein the doping concentration of silicon is 5 × 1014～3×1016cm-3Preferably, the doping concentration is 2e16cm-3；
Utilizing an ion implanter to implant Mg ions in the N-type nitride region formed in the step I;
thirdly, performing rapid thermal annealing treatment in the gas atmosphere of one or more than two of nitrogen, ammonia, argon and hydrogen in any proportion; the annealing temperature is 400-1500 ℃, and the annealing time is 10-90 min;
fourthly, repeating the step one to the step three until a heavily doped P-type nitride region with the specified thickness is generated;
iii, the step of growing the heavily doped P-type nitride region by using a low temperature Pulse Sputter Deposition (PSD) process comprises:
firstly, silicon dioxide is used as a hard mask to shield the top surface of an unetched lightly doped N-type nitride drift region and the upper surface of an isolation layer, ammonia is respectively used as a nitrogen source, magnesium chloride is used as a doping source, and H2As carrier gas, a layer of P-type nitride is homoepitaxially grown on the upper surfaces of the lightly doped N-type nitride drift regions and on two sides of the isolation layer by adopting a PSD (position sensitive detector) method;
secondly, activating P-type doped magnesium ions through in-situ annealing in the furnace, and growing to form a heavily doped P-type nitride region; the annealing temperature is 400-1500 ℃, and the annealing time is 10-90 min.
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