CN114205989B - Circuit board and method for manufacturing the same - Google Patents
Circuit board and method for manufacturing the same Download PDFInfo
- Publication number
- CN114205989B CN114205989B CN202010979240.6A CN202010979240A CN114205989B CN 114205989 B CN114205989 B CN 114205989B CN 202010979240 A CN202010979240 A CN 202010979240A CN 114205989 B CN114205989 B CN 114205989B
- Authority
- CN
- China
- Prior art keywords
- conductive
- layer
- conductive layer
- circuit board
- block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000463 material Substances 0.000 claims abstract description 35
- 239000000853 adhesive Substances 0.000 claims abstract description 34
- 230000001070 adhesive effect Effects 0.000 claims abstract description 34
- 239000010410 layer Substances 0.000 claims description 170
- 239000012790 adhesive layer Substances 0.000 claims description 28
- 239000007791 liquid phase Substances 0.000 claims description 19
- 238000005245 sintering Methods 0.000 claims description 13
- 230000001052 transient effect Effects 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000002923 metal particle Substances 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims 1
- 230000017525 heat dissipation Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000008719 thickening Effects 0.000 description 2
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
本揭示内容的一些实施方式提供一种电路板以及制造电路板的方法，包含以下步骤。提供第一导电层；提供粘着材料以及至少一个导电块，其中粘着材料具有导电性；使用粘着材料将至少一个导电块粘合于第一导电层的一表面上；提供绝缘层；设置绝缘层于第一导电层的表面上以及至少一个导电块上；以及设置第二导电层于绝缘层上。本揭示内容提供的电路板，为内部导电块的厚度以及线路图案的设计提供更大的弹性。
Some embodiments of the present disclosure provide a circuit board and a method for manufacturing the circuit board, comprising the following steps: providing a first conductive layer; providing an adhesive material and at least one conductive block, wherein the adhesive material has conductivity; using the adhesive material to adhere the at least one conductive block to a surface of the first conductive layer; providing an insulating layer; disposing the insulating layer on the surface of the first conductive layer and on the at least one conductive block; and disposing a second conductive layer on the insulating layer. The circuit board provided by the present disclosure provides greater flexibility in the design of the thickness of the internal conductive block and the circuit pattern.
Description
Technical Field
The present disclosure relates to a circuit board and a method of manufacturing the same. In particular, the present disclosure relates to circuit boards with embedded conductive blocks and methods of making the same.
Background
The current method for manufacturing the circuit board with the embedded conductive block (with local thickening) mainly comprises the steps of electroplating a conductive layer in two ways, firstly forming a through hole in an insulating layer of a substrate, filling a conductive material in the through hole, and then forming a conductive layer on the insulating layer and the upper surface and the lower surface of the conductive material filled in the through hole.
However, the thickness of the plating in the first method has a limit such as failing to form a conductive bump structure having a thickness of more than 200 μm. The second method is limited by the thickness of the substrate, which is known in the art, resulting in a limited thickness of the conductive bumps. Therefore, in the current method of embedding the conductive block, there is a limit in the thickening amplitude of the conductive block.
On the other hand, in the second mode, if the conductive layer needs to be further patterned to form a circuit, the patterned region needs to avoid the portion filled with the conductive material, which limits the design flexibility of the circuit pattern.
Therefore, how to make the conductive block embedded in the circuit board have the elasticity of thickness adjustment and to improve the elasticity of the patterned region of the conductive layer is a problem to be solved.
Disclosure of Invention
One aspect of the present disclosure is a circuit board including a first conductive layer, at least one adhesive layer, at least one conductive bump, an insulating layer, and a second conductive layer. At least one adhesive layer is disposed on a surface of the first conductive layer, and the at least one adhesive layer has conductivity. At least one conductive bump comprising a top surface and a bottom surface opposite the top surface, wherein the bottom surface contacts the at least one adhesive layer and is adhered to the first conductive layer via the at least one adhesive layer. And the insulating layer covers the surface of the first conductive layer and at least one conductive block. The second conductive layer is arranged on the insulating layer.
In some embodiments, the thickness of the first conductive layer is at least one HTP200513CN page 2/8 relative to the first conductive layer
The ratio of the thicknesses of the adhesive layer and the at least one conductive bump is greater than 1:15.
In some embodiments, the sum of the thicknesses of the first conductive layer, the at least one adhesive layer, and the at least one conductive bump is 20 micrometers to 3 millimeters.
In some embodiments, the first conductive layer has a thickness greater than 3 microns.
In some embodiments, the thickness of the at least one adhesion layer is less than 5 microns.
In some embodiments, the at least one adhesion layer contacts a surface area of the bottom surface of the at least one conductive bump, not exceeding the surface area of the bottom surface of the at least one conductive bump.
In some embodiments, the plurality of conductive bumps are different in size, shape, or both.
In some embodiments, the conductive bump further comprises at least one conductive post penetrating the second conductive layer and the insulating layer and extending to the top surface of the at least one conductive bump.
In some embodiments, the top of the at least one conductive pillar is coplanar with the second conductive layer.
In some embodiments, the at least one conductive post is a conductive post and the at least one conductive bump is a conductive bump, the conductive post being located on the conductive bump.
In some embodiments, the at least one conductive post is a plurality of conductive posts and the at least one conductive bump is a conductive bump, the plurality of conductive posts being located on the conductive bump.
In some embodiments, the first conductive layer is a patterned first conductive layer, the second conductive layer is a patterned second conductive layer, or a combination thereof.
In some embodiments, the material of the at least one adhesion layer comprises metal particles.
One aspect of the present disclosure is a method of manufacturing a circuit board including providing a first conductive layer, providing an adhesive material and at least one conductive bump, wherein the adhesive material has conductivity, adhering the at least one conductive bump to a surface of the first conductive layer using the adhesive material, providing an insulating layer, disposing the insulating layer on the surface of the first conductive layer and on the at least one conductive bump, and disposing a second conductive layer on the insulating layer.
In some embodiments, the step of adhering the at least one conductive bump to the surface of the first conductive layer using an adhesive material includes heating the adhesive material to cause the adhesive material to be in a fluid state and adhering the at least one conductive bump to the surface of the first conductive layer using the adhesive material.
In some embodiments, an insulating layer is disposed on the surface of the first conductive layer and at least one HTP200513CN page 3/8
The step of forming the conductive block includes removing a portion of the insulating layer, forming at least one recess recessed upward, covering and accommodating the at least one conductive block in the at least one recess, and laminating the insulating layer, the at least one conductive block, and the first conductive layer.
In some embodiments, the method further comprises forming at least one conductive post penetrating the second conductive layer and the insulating layer and extending to the top surface of the at least one conductive bump.
In some embodiments, the step of forming at least one conductive post includes removing a portion of the insulating layer and a portion of the second conductive layer to expose a top surface of the at least one conductive bump to form at least one blind via, and filling the at least one blind via with a conductive material to contact the second conductive layer to form the at least one conductive post.
In some embodiments, the step of disposing the second conductive layer on the insulating layer includes patterning the first conductive layer and the second conductive layer.
It is to be understood that both the foregoing general description and the following detailed description are examples and are intended to provide further explanation of the disclosure as claimed.
Drawings
The present disclosure will be more fully understood from the following detailed description of the embodiments, taken together with the accompanying drawings.
Fig. 1A-1G exemplarily depict a flow of manufacturing a circuit board in some embodiments according to the present disclosure.
Fig. 2A-2B schematically depict a process for manufacturing a circuit board including conductive posts in accordance with some embodiments of the present disclosure.
Fig. 3A-3B schematically depict a process for manufacturing a circuit board including conductive pillars in accordance with further embodiments of the present disclosure.
Fig. 4 schematically depicts a flow for manufacturing a circuit board containing traces in some embodiments according to the present disclosure.
Fig. 5 schematically depicts a process for manufacturing a circuit board including traces and conductive posts in some embodiments according to the present disclosure.
[ Main element symbols description ]
100 Circuit board 110 conductive layer
111 First conductive layer 1111 surface
112 Second conductive layer 113 patterned first conductive layer
114 Patterning the second conductive layer 120, an adhesion layer
130 Conductive block 131 first conductive block
132 Second conductive block 133 third conductive block
134 Top surface 135 top surface
140 Insulating layer 150 conductive column
A is a groove B is a blind hole
Detailed Description
It is to be understood that the various implementations or embodiments provided below may implement different features of the subject matter of this disclosure. Embodiments of specific components and arrangements are presented to simplify the present disclosure and are not limiting. These are, of course, merely examples and are not intended to be limiting. For example, the recitation of a first feature being formed on a second feature described below includes the two being in direct contact, or the two being spaced apart by other additional features than being in direct contact. Furthermore, the present disclosure may repeat reference numerals and/or symbols in various embodiments. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
The terms used in this specification generally have a general meaning in the art and in the context of the use. Examples of embodiments used in this specification, including any terms discussed herein, are illustrative only and do not limit the scope and meaning of the present disclosure or any exemplary terms. As such, the present disclosure is not limited to some embodiments provided in the present specification.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present embodiments.
In this document, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Herein, the terms "comprising," "including," "having," and the like are to be construed as open-ended, i.e., to mean including, but not limited to.
Fig. 1A-1G exemplarily depict a flow of manufacturing a circuit board in some embodiments according to the present disclosure.
First, please refer to fig. 1A. A first conductive layer 111 is provided. In some embodiments, the first conductive layer 111 is a metal, such as copper (copper foil), but not limited thereto. In some embodiments, the first conductive layer has a thickness greater than 3 microns, such as, but not limited to, 3 microns to 10 microns (3 microns, 4 microns, 5 microns, 6 microns, 7 microns, 8 microns, 9 microns, or 10 microns).
Next, please refer to fig. 1B and fig. 1C. An adhesive material having conductivity is coated on the surface 1111 of the first conductive layer 111 as the adhesive layer 120, and the conductive block 130 is adhered to the surface 1111 of the first conductive layer 111. In some embodiments, an adhesive material may be applied to the bottom surface of the conductive block 130, and the conductive block 130 may be adhered to the surface 1111 of the first conductive layer 111.
In some embodiments, the surface area of the adhesive layer 120 contacting the bottom surface of the conductive block 130 does not exceed the surface area of the bottom surface of the conductive block 130, i.e., the adhesive layer 120 does not exceed the bottom surface of the conductive block 130. In some embodiments, the adhesive material comprises a conductive paste with a conductive substance, such as a transient liquid phase sintering (TRANS I ENT Liqu ID PHASE SI NTER I NG; TLPS) adhesive material. The transient liquid phase sintering adhesive material comprises a combination of metal particles (such as copper and tin) and a solvent, and is characterized in that after the combination of metal particles capable of generating a liquid phase at an adhesive interface by heating, the liquid phase flow is formed, and then the liquid phase gradually rises along with the progress of reaction diffusion, so that the melting point of the adhesive layer 120 exceeds the adhesive temperature, the adhesive layer 120 is solidified, and the effect of adhering the first conductive layer 111 is achieved. The adhesive layer 120 formed by the transient liquid phase sintering adhesive material has high reliability, low resistance (excellent electrical conductivity, resistivity may be less than 1x10 -6 Ω·m) and high heat conduction (thermal conductivity greater than 20W/mk) effects, and can conduct the conductive block 130 and the first conductive layer 111 and assist heat dissipation of the conductive block 130. In an embodiment, the transient liquid phase sintering adhesive material is heated to a temperature higher than 150 ℃ and lower than the melting point (e.g., 160 ℃, 170 ℃, 180 ℃, 190 ℃, or 200 ℃) of the first conductive layer 111 and the conductive bump 130, but not limited thereto, such that the transient liquid phase sintering adhesive material is in a liquid phase flowing state. In one embodiment, the adhesion layer 120 has a thickness of less than 5 microns, such as 0.01 microns to 5 microns, such as1 micron, 2 microns, 3 microns, 4 microns, or HTP200513CN page 6/8 of any of the foregoing
Numerical values, but are not limited thereto.
In some embodiments, the conductive block 130 is not limited in size and shape. In one embodiment, the conductive bumps 130 may be the same size or shape, and in another embodiment, the conductive bumps 130 may be different sizes or shapes (e.g., the first conductive bumps 131, the second conductive bumps 132, and the third conductive bumps 133 of fig. 1C). In one embodiment, the conductive block 130 may be an elongated extension structure, such as a conductive pad or line.
In some embodiments, the sum of the thicknesses of the first conductive layer 111, the adhesive layer 120, and the conductive block 130 may be 20 micrometers to 3 millimeters, such as 20 micrometers, 40 micrometers, 60 micrometers, 80 micrometers, 100 micrometers, 200 micrometers, 400 micrometers, 600 micrometers, 800 micrometers, 1 millimeter, 2 millimeters, 3 millimeters, or any of the foregoing ranges, but is not limited thereto. It should be noted that, by using the adhesive layer 120 and bonding the conductive block 130 to the first conductive layer 111 and then bonding other components, the conductive block 130 is not limited by the thickness of the conventional circuit board, and a more flexible application is provided for the structure of the circuit board embedded with the conductive block 130. For example, in some embodiments, thicker conductive blocks 130 may be used such that the ratio of the thickness of the first conductive layer 111 to the thickness of the first conductive layer 111, the adhesive layer 120, and the conductive blocks 130 is less than 1:15, such as 1:15 to 1:30 (e.g., 1:16, 1:17, 1:18, 1:19, 1:20, 1:21, 1:22, 1:23, 1:24, 1:25, 1:26, 1:27, 1:28, 1:29, 1:30, or ratios in any of the foregoing), but is not limited thereto.
Next, please refer to fig. 1D to fig. 1G. In fig. 1D, an insulating layer 140 is provided. In fig. 1E, a portion of the insulating layer 140 is removed, and a recess a is formed on the surface of the insulating layer 140, which is recessed upward and can accommodate the conductive bump 130. In fig. 1F and 1G, the insulating layer 140 is disposed on the surface 1111 of the first conductive layer 111 and the conductive bump 130, such that the conductive bump 130 is accommodated in the groove a, and at the same time, the second conductive layer 112 is provided and the second conductive layer 112 is disposed on the insulating layer 140, thereby obtaining the circuit board 100.
In some embodiments, the material and thickness of the second conductive layer 112 may be the same as or similar to the first conductive layer 111.
In other embodiments, the step of disposing the insulating layer 140 on the surface 1111 of the first conductive layer 111 and the conductive block 130 may be performed by forming the groove a capable of accommodating the conductive block 130 on the first insulating layer, and then covering the first insulating layer containing the groove a on the conductive block 130 and the first conductive HTP200513CN 7/8 th page of the conductive layer 111, so that the groove a accommodates the conductive block 130. One or more second insulating layers, which have not been subjected to a recess forming process, are then disposed on the first insulating layer including the recess a according to the desired thickness of the insulating layer 140. Finally, the second conductive layer 112 is disposed on the second insulating layer or the uppermost second insulating layer, thereby obtaining the circuit board 100. In some embodiments, the steps of disposing the insulating layer 140 on the surface 1111 of the first conductive layer 111 and the conductive bump 130 and disposing the second conductive layer 112 on the insulating layer 140 include using a thermal compression method to simultaneously compress the first conductive layer 111, the insulating layer 140, the conductive bump 130 and the second conductive layer 112 to obtain the circuit board 100, wherein the first conductive layer 111, the conductive bump 130, the adhesive layer 120 and the second conductive layer 112 have conductivity and are electrically connected to each other to form a conductive structure.
Turning to fig. 2A-2B, a process for fabricating a circuit board including conductive pillars 150 in accordance with some embodiments of the present disclosure is illustratively described.
First, referring to fig. 2A, a portion of the insulating layer 140 and a portion of the second conductive layer 112 are removed, exposing the top surface 134 of the conductive block 130 to form a blind hole B. Next, referring to fig. 2B again, a conductive material is filled into the blind holes B to form conductive pillars 150. That is, the conductive pillars 150 penetrate through the second conductive layer 112 and the insulating layer 140, and extend onto the top surface 134 of the conductive block 130. In some embodiments, the conductive pillars 150 may not be disposed on the top surface 135 of a portion of the conductive bumps 130 (e.g., the third conductive bumps 133).
In some embodiments, the conductive material may be the same as the material of conductive layer 110, such as copper. In some embodiments, the blind holes B may be formed by laser or selective etching, and the second conductive layer 112 is used as a plating seed layer to fill the blind holes B with a conductive material, thereby forming the conductive pillars 150. In some embodiments, the tops of the conductive pillars 150 are coplanar with the second conductive layer 112.
The conductive pillars 150 are used to assist in heat dissipation of the conductive block 130, and one skilled in the art can selectively form one or more conductive pillars 150 on the conductive block 130 according to heat dissipation requirements, cost, and subsequent processing.
In some embodiments, please refer to fig. 3A-3B, which schematically illustrate a process of manufacturing a circuit board 100 including conductive pillars 150 according to other embodiments of the present disclosure, wherein in addition to one conductive pillar 150 being formed on one conductive block 130, a plurality of conductive pillars 150 are formed on one conductive block 130, which is currently characterized by enlarging the HTP200513CN page 8/8 for the conductive block 130 that is prone to heat during use
Heat dissipation area. Fig. 3A illustrates that one blind hole B is formed on the first conductive block 131, and two blind holes B are formed on the second conductive block 132, respectively. Fig. 3B illustrates filling the blind via B with a conductive material to form a conductive pillar 150. In some embodiments, fig. 3A and 3B may be similar to the methods described in fig. 2A and 2B, forming blind holes B and conductive pillars 150.
That is, the circuit board 100 in the present disclosure may include the conductive pillars 150 on the conductive block 130, a plurality of conductive pillars 150 on the conductive block 130, no conductive pillars 150 on the conductive block 130, or the above arrangement.
In some embodiments, please refer to fig. 4, the first conductive layer 111, the second conductive layer 112, or both may be patterned by photolithography and etching to form a patterned first conductive layer 113, a patterned second conductive layer 114, or both the patterned first conductive layer 113 and the patterned second conductive layer 114 for wiring.
For example, the first conductive layer 111 and the second conductive layer 112 may be further patterned in the circuit board 100 including the conductive block 130, forming the patterned first conductive layer 113 and the patterned second conductive layer 114. Referring to fig. 5, the first conductive layer 111 and the second conductive layer 112 may be further patterned in the circuit board 100 including the conductive bumps 130 and the conductive pillars 150. It is emphasized that, due to some embodiments of the present disclosure, the conductive bump 130 does not penetrate the insulating layer 140 and the second conductive layer 112, and a portion of the conductive bump 130 does not have the conductive post 150 (e.g., the third conductive bump 133) thereon. Therefore, the second conductive layer 112 is not limited to the position of the conductive bump 130 when patterning.
The circuit board and the method for manufacturing the circuit board according to some embodiments of the present disclosure utilize conductive adhesive materials to adhere the conductive layer and the conductive bump, and compared with the conventional electroplating method for forming the conductive bump on the conductive layer or filling the conductive material into the through hole of the insulating layer in the substrate, the thickness of the conductive bump of the present disclosure is not limited by the substrate or the electroplating method, and has better flexibility, and the patterning position of the conductive layer is not limited by the position of the conductive bump, so as to provide more various design changes for the circuit pattern.
While the present disclosure has been described in detail with respect to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.
Claims (17)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010979240.6A CN114205989B (en) | 2020-09-17 | 2020-09-17 | Circuit board and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010979240.6A CN114205989B (en) | 2020-09-17 | 2020-09-17 | Circuit board and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114205989A CN114205989A (en) | 2022-03-18 |
| CN114205989B true CN114205989B (en) | 2025-03-11 |
Family
ID=80644689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010979240.6A Active CN114205989B (en) | 2020-09-17 | 2020-09-17 | Circuit board and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114205989B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104703384A (en) * | 2013-12-10 | 2015-06-10 | 旭德科技股份有限公司 | Circuit board and manufacturing method thereof |
| JP2017063102A (en) * | 2015-09-24 | 2017-03-30 | イビデン株式会社 | Printed wiring board and manufacturing method of the same |
| KR20190092085A (en) * | 2018-01-30 | 2019-08-07 | 삼성전자주식회사 | Emi shielding structure and manufacturing method for the same |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3867523B2 (en) * | 2000-12-26 | 2007-01-10 | 株式会社デンソー | Printed circuit board and manufacturing method thereof |
| CN100511661C (en) * | 2007-02-01 | 2009-07-08 | 上海交通大学 | Microelectronic element with elastic conductive projection and method of manufacture |
| CN101360398B (en) * | 2007-07-31 | 2010-06-02 | 欣兴电子股份有限公司 | Circuit board structure with concave conductive column and manufacturing method thereof |
| US10361178B2 (en) * | 2015-09-29 | 2019-07-23 | Infineon Technologies Austria Ag | Interconnection structure, LED module and method |
-
2020
- 2020-09-17 CN CN202010979240.6A patent/CN114205989B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104703384A (en) * | 2013-12-10 | 2015-06-10 | 旭德科技股份有限公司 | Circuit board and manufacturing method thereof |
| JP2017063102A (en) * | 2015-09-24 | 2017-03-30 | イビデン株式会社 | Printed wiring board and manufacturing method of the same |
| KR20190092085A (en) * | 2018-01-30 | 2019-08-07 | 삼성전자주식회사 | Emi shielding structure and manufacturing method for the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114205989A (en) | 2022-03-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2011501410A (en) | Robust multilayer wiring elements and assembly with embedded microelectronic elements | |
| JP2014239200A (en) | Novel end terminal part and coupling part of chip and substrate | |
| TWI255466B (en) | Polymer-matrix conductive film and method for fabricating the same | |
| JP2004158545A (en) | Multilayer substrate and its manufacturing method | |
| JP6444269B2 (en) | Electronic component device and manufacturing method thereof | |
| TW201507556A (en) | Thermally enhanced wiring board with thermal pad and electrical post | |
| JP6741419B2 (en) | Semiconductor package and manufacturing method thereof | |
| JP2016157919A (en) | Method for fabricating electronic module and electronic module | |
| JP2010109180A (en) | Method of manufacturing substrate with built-in semiconductor device | |
| CN114205989B (en) | Circuit board and method for manufacturing the same | |
| TWI736421B (en) | Circuitboard and manufacture method thereof | |
| CN107770946A (en) | Printed wiring board and its manufacture method | |
| JP4443349B2 (en) | Manufacturing method of multilayer wiring board | |
| JP6100617B2 (en) | Multi-layer wiring board and probe card board | |
| JP6473897B2 (en) | Manufacturing method of semiconductor device | |
| JP6058321B2 (en) | Wiring board manufacturing method | |
| JP3862454B2 (en) | Metal-based multilayer circuit board | |
| JP2015159242A (en) | Wiring board, and multilayer wiring board including the same | |
| JP7119583B2 (en) | Printed wiring board and manufacturing method thereof | |
| JP2005045228A (en) | Circuit board with built-in electronic component and its manufacturing method | |
| JP5836751B2 (en) | Thin film wiring board | |
| JP2006049536A (en) | Multilayer circuit board | |
| WO2000049652A1 (en) | Bonding material, semiconductor device, method of manufacturing semiconductor device, circuit board and electronic device | |
| JP2013191678A (en) | Multilayer wiring board | |
| US9673063B2 (en) | Terminations |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |