CN114171492B

CN114171492B - Semiconductor structure

Info

Publication number: CN114171492B
Application number: CN202010956199.0A
Authority: CN
Inventors: 罗正玮; 张介斌; 黄凯易; 叶达勋
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2020-09-11
Filing date: 2020-09-11
Publication date: 2025-01-21
Anticipated expiration: 2040-09-11
Also published as: CN114171492A

Abstract

A semiconductor structure includes a first inductor, a second inductor, and a first input/output (I/O) pad. The first I/O pad couples the first inductor and the second inductor. The first I/O pad, the magnetic field center axis of the first inductor, and the magnetic field center axis of the second inductor are sequentially arranged along a first direction.

Description

Semiconductor structure

Technical Field

The present invention relates generally to semiconductor structures, and more particularly to semiconductor structures for integrated inductors.

Background

The inductor is an important component for realizing the functions of impedance matching and the like in the integrated circuit, and with the development of the integrated circuit, the integrated inductor gradually replaces the traditional separated component and is widely used in the integrated circuit. However, as the size of integrated circuits is scaled smaller, the arrangement of components in an integrated circuit is becoming more and more important in addition to the complexity of the fabrication of the integrated circuit. Therefore, maintaining the same performance while using less area to configure the integrated inductor without increasing the process complexity has become an extremely desirable problem in the art.

Disclosure of Invention

The invention discloses a semiconductor structure, which comprises a first inductor, a second inductor and a first input/output (I/O) pad. The first I/O pad is coupled to the first inductor and the second inductor. The first I/O pad, the magnetic field central axis of the first inductor and the magnetic field central axis of the second inductor are sequentially arranged along the first direction.

The invention further discloses a semiconductor structure comprising a first inductor and a second inductor. The first inductor has a first portion, a second portion and a third portion. The second inductor has a fourth portion, a fifth portion and a sixth portion. The first portion, the second portion and the third portion surround the fourth portion. The fourth, fifth and sixth portions surround the first portion.

The semiconductor structure can arrange the integrated inductor in a small area without affecting the efficiency, and forms a symmetrical structure. Compared with the prior art, the semiconductor structure of the invention can reduce the arrangement area of the integrated inductor, and the complexity of manufacturing the integrated inductor is reduced because the semiconductor structure has a symmetrical structure.

Drawings

Fig. 1 is a schematic diagram of a semiconductor structure in some embodiments of the invention.

Fig. 2 is a schematic diagram of a semiconductor structure in some embodiments of the invention.

Fig. 3A to 3D are layout diagrams of an inductor structure according to some embodiments of the invention.

Fig. 4A to 4D are layout diagrams of inductor structures according to some embodiments of the invention.

Detailed Description

Reference is made to fig. 1. Fig. 1 is a schematic illustration of an embodiment of a semiconductor structure 10 in some embodiments of the application. The semiconductor structure 10 is used to reduce attenuation of high frequency signals through input/output (I/O) pads in an integrated circuit, in other words, bandwidth and high frequency gain of the signals can be improved. The semiconductor structure 10 in fig. 1 includes two I/O pads (I/O pad 11, I/O pad 12) corresponding to two inductors (I/O pad 11 corresponds to and couples inductors L1 and L2, I/O pad 12 corresponds to and couples inductors L3 and L4), inductors L1 and L3 are coupled to the circuit 14, and inductors L2 and L4 are coupled to the circuit 13. In some embodiments, the circuits 13 and 14 may be transmitter (transmitter) circuits or receiver (receiver) circuits, but are not limited thereto. It should be noted that the embodiment of fig. 1 is not intended to limit the number of I/O pads, and the basic unit of the semiconductor structure of the present application is one I/O pad and two corresponding inductors, and two I/O pads are shown in fig. 1 to more clearly show their relative positions.

For the I/O pad 11, by changing the inductance (inductance) of the inductor L1 and the inductor L2, the input impedance of the signal can be changed, and by proper design, the bandwidth and the high frequency gain of the signal can be improved by implementing impedance matching, and in the related art, the inductor L1 and the inductor L2 are also called peak-to-peak (peak) inductors. In some embodiments, the inductance L1 and the inductance L2 may have the same or different inductance values. As the area of the die is continuously reduced along with the progress of the manufacturing process, the width of the I/O pad and the distance between the I/O pads are also reduced along with the reduction, and the inductor structure of the application can reduce the whole area of the inductor L1 and the inductor L2, so that the whole inductor L1 and the inductor L2 have narrower width to conform to the width of the current narrower I/O pad and the distance between the I/O pads, and the peak-to-peak inductor can not limit the placement of the I/O pads.

Fig. 2 is a schematic diagram of a semiconductor structure 10 according to some embodiments of the present application, in which inductors L1 to L4 are shown in a layout view to facilitate the description of the present application. Reference numerals H1, H2, H3, and H4 respectively represent the approximate positions of the central axes of the magnetic fields generated by the inductors L1 to L4 when signals pass through. As shown in fig. 2, the I/O pad 11, the magnetic field center axis H1, and the magnetic field center axis H2 are sequentially arranged along the Y direction, and the I/O pad 12, the magnetic field center axis H3, and the magnetic field center axis H4 are sequentially arranged along the Y direction. The magnetic field central axis H1 and the magnetic field central axis H3 are sequentially arranged along the X direction, and the magnetic field central axis H2 and the magnetic field central axis H4 are sequentially arranged along the X direction.

The inductor L1, the inductor L2, and the I/O pad 11 have a width W1, a width W2, and a width W3, respectively, in the X direction. In some embodiments, widths W1 and W2 are no greater than W3. In some embodiments, as shown in FIG. 2, widths W1 and W2 are approximately equal. In some embodiments, the dimensions and configuration of I/O pad 11, inductor L1, inductor L2 are substantially the same as the dimensions and configuration of I/O pad 12, inductor L3, inductor L4.

The inductors L1 and L2 are disposed in multiple conductive layers, fig. 3A to 3D show layout diagrams of the structures of the inductor L1 (shown in fig. 2) in the different conductive layers according to the embodiment from a top view, and fig. 4A to 4D show layout diagrams of the structures of the inductor L2 (shown in fig. 2) in the different conductive layers. Specifically, fig. 3A shows a layout of windings of the complete inductor L1 on the conductive layer C1 and the conductive layer C2 (shown in an overlapping manner), fig. 3B shows a layout of windings of the inductor L1 on the conductive layer C1 only, fig. 3C shows a layout of vias of the inductor L1 on the connection layer CV interposed between the conductive layers C1 and C2 only, and fig. 3D shows a layout of windings of the inductor L1 on the conductive layer C2 only.

Referring to fig. 3A to 3D, the inductor L1 includes a first portion P1, a second portion P2 and a third portion P3. The first portion P1 is a main coil portion of the inductor L1, and the winding disposed on the conductive layer C1 is shown in fig. 3B, and the winding disposed on the conductive layer C2 is shown in fig. 3D. The second portion P2 and the third portion P3 are disposed on the conductive layer C2, as shown in fig. 3D. The conductive layer C1 and the conductive layer C2 are disposed over a substrate (not shown), and the conductive layer C1 is disposed over the conductive layer C2, i.e., the conductive layer C2 is disposed between the substrate and the conductive layer C1. In this embodiment, the conductive layer C1 comprises Aluminum, such as Aluminum redistribution layer (AL-redistribution layer, AL-RDL), and the conductive layer C2 comprises copper, such as Ultra THICK METAL (UTM) layer comprising copper, uppermost of the plurality of copper metal layers. However, the application is not so limited and in some embodiments, conductive layer C1 and conductive layer C2 may both be copper metal layers. The conductive layer C1 is coupled to the conductive layer C2 through the connection layer CV, and in this embodiment, the winding of the inductor L1 disposed on the conductive layer C1 and the winding of the inductor L1 disposed on the conductive layer C2 are connected to each other through the via hole (via) V1 and the via hole V2 on the connection layer CV.

The number of winding turns of the first portion P1 of the inductor L1 disposed on the conductive layer C1 and the number of winding turns of the first portion P2 disposed on the conductive layer C2 can be determined according to the requirement. Referring to fig. 3B, it can be seen more clearly that the winding of the first portion P1 disposed on the conductive layer C1 has a terminal N1 and a terminal N2, the terminal N1 is used to couple to the I/O pad 11 shown in the previous embodiment (fig. 1 and 2), and the terminal N2 is coupled to the winding of the first portion P1 disposed on the conductive layer C2 through the via V1 and the via V2 of fig. 3C. Referring to fig. 3D, it can be seen more clearly that the winding of the first portion P1 disposed on the conductive layer C2 has an end point N3, and the end point N3 is coupled to the winding of the first portion P1 disposed on the conductive layer C1 shown in fig. 3B through the via holes V1 and V2 of fig. 3C. The second portion P2 and the third portion P3 are extending portions of the inductor L1. The first portion P1, the second portion P2 and the third portion P3 of the inductor L1 are connected in the conductive layer C2, and the third portion P3 has a terminal N4 for coupling to the circuit 14. Based on the above arrangement, the I/O pad 11 is coupled to the inductor L1 through the conductive layer C1, and the inductor L1 is coupled to the circuit 14 shown in the previous embodiment (e.g., fig. 1 and 2) through the conductive layer C2.

In this embodiment, when a signal enters the inductor L1 from the terminal N1 and leaves the inductor L1 from the terminal N4 in the form of a positive current according to the winding direction of the winding of the inductor L1, a magnetic field having a Z direction (the direction out of the drawing plane) is generated at the magnetic field center axis H1 of the inductor L1.

Similarly, fig. 4A shows the layout of the windings of the complete inductor L2 on the conductive layer C1 and the conductive layer C2 (shown in an overlapping manner), fig. 4B shows the layout of the windings of the inductor L2 on the conductive layer C1 only, fig. 4C shows the layout of the vias of the inductor L2 on the connection layer CV between the conductive layers C1 and C2 only, and fig. 4D shows the layout of the windings of the inductor L2 on the conductive layer C2 only.

Referring to fig. 4A to 4D, the inductor L2 includes a fourth portion P4, a fifth portion P5 and a sixth portion P6. The fourth portion P4 is a main coil portion of the inductor L2, and the winding disposed on the conductive layer C1 is shown in fig. 4B, and the winding disposed on the conductive layer C2 is shown in fig. 4D. The fifth portion P5 and the sixth portion P6 are provided with a conductive layer C1, as shown in fig. 4B. The conductive layer C1 is coupled to the conductive layer C2 through the connection layer CV, and in this embodiment, the winding of the inductor L2 disposed on the conductive layer C1 and the winding of the inductor L2 disposed on the conductive layer C2 are connected to each other through the via hole V3 and the via hole V4 on the connection layer CV.

The number of winding turns of the fourth portion P4 of the inductor L2 disposed on the conductive layer C1 and the number of winding turns disposed on the conductive layer C2 can be determined according to the requirement. The fifth portion P5 and the sixth portion P6 are extending portions of the inductor L2. Referring to fig. 4B, it can be seen more clearly that the winding of the fourth portion P4 disposed on the conductive layer C1 is connected to the fifth portion P5 and the sixth portion P6 on the conductive layer C1, the sixth portion P6 has a terminal N5 for coupling to the I/O pad 11 of the previous embodiment (fig. 1 and 2), the fourth portion P4 further has a terminal N6, and the terminal N6 is coupled to the winding of the fourth portion P4 disposed on the conductive layer C2 through the via holes V3 and V4 of fig. 4C. Referring to fig. 4D, it can be seen more clearly that the winding disposed on the conductive layer C2 at the fourth portion P4 has an end N7 and an end N8, the end N7 is coupled to the winding disposed on the conductive layer C1 at the fourth portion P4 shown in fig. 4B through the vias V3 and V4 of fig. 4C, and the end N8 is coupled to the circuit 13 shown in the previous embodiment (e.g. fig. 1 and 2). Based on the above arrangement, the I/O pad 11 is coupled to the inductor L2 through the conductive layer C1, and the inductor L2 is coupled to the circuit 13 through the conductive layer C2.

In this embodiment, when a signal enters the inductor L2 from the terminal N5 and leaves the inductor L2 from the terminal N8 in the form of a positive current, a magnetic field having a-Z direction (a direction penetrating into the drawing) is generated at the magnetic field center axis H2 of the inductor L2 according to the winding direction of the winding of the inductor L2.

Thus, as can be seen when referring to fig. 3A and 4A together, the first portion P1, the second portion P2 and the third portion P3 surround three sides of the fourth portion P4, and the fourth portion P4, the fifth portion P5 and the sixth portion P6 surround three sides of the first portion P1. Since the terminal N1 of the inductor L1 and the terminal N5 of the inductor L2 are both coupled to the I/O pad 11, the terminal N1 and the terminal N5 may be co-point in some embodiments. And the terminal N4 of the inductor L1 is adjacent to but electrically separated from the terminal N8 of the inductor L2.

The inductor L1 and the inductor L2 receive signals at the I/O pad 11, and according to the winding directions of the inductor L1 and the inductor L2, the magnetic field generated by the inductor L1 is opposite to the magnetic field generated by the inductor L2. Generally, the high frequency signal is input to the chip in the form of a differential signal, for example, in fig. 2, I/O pad 11 and I/O pad 12 are differential pairs, so that the current I1 flowing into inductor L1 and inductor L2 has opposite polarity to the current I2 flowing into inductor L3 and inductor L4. For example, the current I1 is positive and the current I2 is negative, so that the magnetic field directions indicated in FIG. 2, namely the magnetic field center axis H1 and the magnetic field center axis H4, generate magnetic fields in the Z direction, and the magnetic field center axis H2 and the magnetic field center axis H3 generate magnetic fields in the-Z direction. Thus, the magnetic field generated by each inductor is opposite to the magnetic field generated by the adjacent inductor, for example, the magnetic field generated by the inductor L1 is opposite to the magnetic field generated by the adjacent inductor L2 and the adjacent inductor L3, which helps to suppress the radiation of the magnetic field (radiation) so as to avoid interfering with other electronic components. Therefore, the design of the peak-to-peak inductance corresponding to the adjacent I/O pads is not required to be changed for reducing the electromagnetic wave, and the basic units of the semiconductor structure of the present application, namely the inductances L1 and L2 (or the inductances L3 and L4) can be completely duplicated.

As previously described, in some embodiments, the dimensions and configuration of I/O pad 11, inductor L1, inductor L2 are substantially the same as the dimensions and configuration of I/O pad 12, inductor L3, and inductor L4. Therefore, according to the detailed description of the inductor L1 and the inductor L2 in the foregoing embodiments, those skilled in the art should understand the implementation of the inductor L3 and the inductor L4, which will not be described in detail later.

[ Symbolic description ]

10 Semiconductor structure

11:I/O pad

12:I/O pad

13 Circuit

14 Circuit

L1 inductance

L2 inductance

L3 inductor

L4 inductance

W1 width

W2 width

W3 width

H1 magnetic field center axis

H2 magnetic field center axis

H3 magnetic field center axis

H4 magnetic field center axis

X direction

Y direction

I1 current

I2 current

P1 part of

P2 part of

P3 part of

P4 part of

P5 part of

P6 part of

N1 end point

N2 endpoint

N3 endpoint

N4 endpoint

N5 endpoint

N6 endpoint

N7 end point

N8 endpoint

C1 conductive layer

C2 conductive layer

CV connecting layer

V1 via hole

V2 via hole

V3 via hole

V4 via hole

Claims

1. A semiconductor structure comprising:

Substrate;

First inductor;

a second inductor, wherein the first inductor and the second inductor are alternately disposed on a first conductive layer and a second conductive layer on the substrate, and the second conductive layer is located between the first conductive layer and the substrate; and

A first input-output pad is coupled to the first inductor and the second inductor.

The first input-output pad, the magnetic field center axis of the first inductor, and the magnetic field center axis of the second inductor are sequentially arranged along a first direction.

2. The semiconductor structure of claim 1, wherein

The direction of the magnetic field generated by the first inductor is opposite to the direction of the magnetic field generated by the second inductor.

The first inductor, the second inductor and the first input-output pad have a first width, a second width and a third width in a second direction perpendicular to the first direction, respectively, and the first width and the second width are less than or equal to the third width, and

The inductance value of the first inductor is different from the inductance value of the second inductor.

3. The semiconductor structure of claim 1 , further comprising:

a first circuit coupled to the first inductor; and

The second circuit is coupled to the second inductor.

4. The semiconductor structure of claim 1, wherein

The first input-output pad is coupled to the first inductor and the second inductor through the first conductive layer, and

The first conductive layer includes aluminum, and the second conductive layer includes copper.

5. The semiconductor structure of claim 1, further comprising:

The third inductor;

a fourth inductor; and

The second input-output pad is coupled to the third inductor and the fourth inductor.

wherein the third inductor is the same as the first inductor, the fourth inductor is the same as the second inductor, and the third inductor and the fourth inductor are adjacent to the first inductor and the second inductor respectively, and

The second input-output pad, the magnetic field center axis of the third inductor, and the magnetic field center axis of the fourth inductor are sequentially arranged along the first direction.

6. A semiconductor structure comprising:

Substrate;

A first inductor having a first portion, a second portion and a third portion, wherein the first portion is disposed on the first conductive layer and the second conductive layer of the semiconductor structure, the second portion and the third portion are disposed on the second conductive layer, and the second conductive layer is located between the substrate and the first conductive layer; and

The second inductor has a fourth portion, a fifth portion and a sixth portion, the fourth portion is disposed on the first conductive layer and the second conductive layer, and the fifth portion and the sixth portion are disposed on the first conductive layer.

The first part, the second part and the third part surround the fourth part, and the fourth part, the fifth part and the sixth part surround the first part.

7. The semiconductor structure as claimed in claim 6, wherein a first terminal of the first inductor is coupled to a second terminal of the second inductor, and the semiconductor structure further comprises:

A first input/output pad is coupled to the first terminal and the second terminal.

The width of the first inductor and the width of the second inductor are smaller than or equal to the width of the first input/output pad.

8. The semiconductor structure as described in claim 7, wherein the first terminal and the second terminal are arranged in the first conductive layer, wherein the third terminal of the first inductor is located on the other side relative to the first terminal, and the fourth terminal of the second inductor is located on the other side relative to the second terminal, and the third terminal and the fourth terminal are arranged in the second conductive layer.

9. The semiconductor structure of claim 7, further comprising:

The third inductor;

a fourth inductor; and

The first input/output pad, the first inductor, the second inductor, the second input/output pad, the third inductor, and the fourth inductor are arranged side by side, and

The first inductor and the fourth inductor generate a first magnetic field direction, and the second inductor and the third inductor generate a second magnetic field direction opposite to the first magnetic field direction.