CN114168315A - Multi-core-based message processing method and device, electronic equipment and storage medium - Google Patents
Multi-core-based message processing method and device, electronic equipment and storage medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
- G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
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- G06—COMPUTING; CALCULATING OR COUNTING
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Abstract
The embodiment of the invention provides a message processing method and device based on multiple cores, electronic equipment and a storage medium. The method comprises the following steps: sequentially dividing the message processing process into a plurality of subprograms, wherein each subprogram runs in one CPU core of a multi-core processor; receiving messages to be processed, and processing different messages to be processed in parallel, wherein each message to be processed is sequentially processed by a plurality of CPU cores running subprograms according to the sequence to obtain a processed message corresponding to the message to be processed. The message processing method based on multiple cores provided by the embodiment of the invention divides the message processing process into a plurality of subprograms, and each core runs one subprogram on equipment using a multi-core processor, so that the message processing can be simultaneously carried out on a plurality of cores, and the equipment can simultaneously process a plurality of messages, thereby effectively improving the message processing speed and the message throughput of the network node equipment.
Description
Technical Field
The embodiment of the invention relates to the technical field of communication, in particular to a message processing method and device based on multiple cores, electronic equipment and a storage medium.
Background
The Open System Interconnection (OSI) reference model is a network Interconnection model developed by the ISO organization in 1985, and the architecture standard defines a seven-layer framework for network Interconnection, including: physical layer, data link layer, network layer, transport layer, session layer, presentation layer, and application layer, i.e., the OSI open systems interconnection reference model.
Fig. 1 is a schematic diagram of an OSI seven-layer model in the prior art, and as shown in fig. 1, when a message needs to be transmitted between 2 nodes on a network according to the OSI model, one device node needs to package the message layer by layer from an application layer until the message reaches a physical layer, and the message is converted into an electrical signal through the physical layer and sent out. And the opposite end node receives the message from the physical layer and decapsulates the message layer by layer.
Fig. 2 is a schematic diagram of a process flow of packet decapsulation in the prior art, as shown in fig. 2, decapsulation processing of a received packet is usually performed by a program called a protocol stack running in a network device at present, and a characteristic of the protocol stack is that after processing of one packet is completed, a next packet can be processed, which results in a slow packet processing speed and a low packet throughput of the device.
Disclosure of Invention
Aiming at the defects in the prior art, the embodiment of the invention provides a message processing method and device based on multiple cores, electronic equipment and a storage medium.
In a first aspect, an embodiment of the present invention provides a multi-core based message processing method, including:
sequentially dividing the message processing process into a plurality of subprograms, wherein each subprogram runs in one CPU core of a multi-core processor;
receiving messages to be processed, and processing different messages to be processed in parallel, wherein each message to be processed is sequentially processed by a plurality of CPU cores running subprograms according to the sequence to obtain a processed message corresponding to the message to be processed.
Optionally, in the foregoing method, each of the messages to be processed sequentially passes through a plurality of CPU cores running subroutines according to the sequence, where the method includes:
a first CPU core in the CPU cores receives and processes a message to be processed to obtain a middle message;
each CPU core except the first CPU core in the plurality of CPU cores receives and processes the intermediate message processed by the last CPU core;
each CPU core except the last CPU core in the plurality of CPU cores sends the processed intermediate message to the next CPU core;
and after the last CPU core processes the corresponding intermediate message, obtaining a processed message corresponding to the message to be processed.
As with the above-described method, the first and second electrodes, optionally,
each CPU core except the last CPU core in the plurality of CPU cores sends the processed intermediate message to the next CPU core, and the method comprises the following steps:
each CPU core except the last CPU core in the plurality of CPU cores caches the processed intermediate message to a cache queue corresponding to the CPU core;
correspondingly, each CPU core of the plurality of CPU cores except for the first CPU core receives and processes the intermediate packet processed by the previous CPU core, including:
and each CPU core except the first CPU core in the plurality of CPU cores takes out the next intermediate message to be processed from the cache queue corresponding to the last CPU core and processes the intermediate message.
Optionally, in the method described above, the packet processing procedure includes a packet encapsulation procedure or a packet decapsulation procedure.
As in the foregoing method, optionally, if the packet processing process is a packet encapsulation process, the plurality of sub-programs sequentially include: an application layer subroutine, a presentation layer subroutine, a session layer subroutine, a transport layer subroutine, a network layer subroutine, a link layer subroutine, and a physical layer subroutine.
As in the foregoing method, optionally, if the packet processing procedure is a packet decapsulation procedure, the plurality of sub-programs sequentially include: a physical layer subroutine, a link layer subroutine, a network layer subroutine, a transport layer subroutine, a session layer subroutine, a presentation layer subroutine, and an application layer subroutine.
In a second aspect, an embodiment of the present invention provides a multi-core based packet processing apparatus, including:
the dividing module is used for sequentially dividing the message processing process into a plurality of subprograms, and each subprogram runs in one CPU core of the multi-core processor;
and the processing module is used for receiving messages to be processed and processing different messages to be processed in parallel, wherein each message to be processed is sequentially processed by a plurality of CPU cores running subprograms according to the sequence to obtain a processed message corresponding to the message to be processed.
As with the apparatus, optionally, the processing module is specifically configured to:
a first CPU core in the CPU cores receives and processes a message to be processed to obtain a middle message;
each CPU core except the first CPU core in the plurality of CPU cores receives and processes the intermediate message processed by the last CPU core;
each CPU core except the last CPU core in the plurality of CPU cores sends the processed intermediate message to the next CPU core;
and after the last CPU core processes the corresponding intermediate message, obtaining a processed message corresponding to the message to be processed.
As with the apparatus described above, optionally, the processing module is specifically configured to:
each CPU core except the last CPU core in the plurality of CPU cores caches the processed intermediate message to a cache queue corresponding to the CPU core;
and each CPU core except the first CPU core in the plurality of CPU cores takes out the next intermediate message to be processed from the cache queue corresponding to the last CPU core and processes the intermediate message.
Optionally, the packet processing procedure includes a packet encapsulation procedure or a packet decapsulation procedure.
Optionally, if the packet processing process is a packet encapsulation process, the plurality of sub-programs sequentially include: an application layer subroutine, a presentation layer subroutine, a session layer subroutine, a transport layer subroutine, a network layer subroutine, a link layer subroutine, and a physical layer subroutine.
Optionally, if the packet processing process is a packet decapsulation process, the plurality of sub-programs sequentially include: a physical layer subroutine, a link layer subroutine, a network layer subroutine, a transport layer subroutine, a session layer subroutine, a presentation layer subroutine, and an application layer subroutine.
In a third aspect, an embodiment of the present invention provides an electronic device, including:
the processor and the memory are communicated with each other through a bus; the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform a method comprising: sequentially dividing the message processing process into a plurality of subprograms, wherein each subprogram runs in one CPU core of a multi-core processor; receiving messages to be processed, and processing different messages to be processed in parallel, wherein each message to be processed is sequentially processed by a plurality of CPU cores running subprograms according to the sequence to obtain a processed message corresponding to the message to be processed.
In a fourth aspect, an embodiment of the present invention provides a storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the following method: sequentially dividing the message processing process into a plurality of subprograms, wherein each subprogram runs in one CPU core of a multi-core processor; receiving messages to be processed, and processing different messages to be processed in parallel, wherein each message to be processed is sequentially processed by a plurality of CPU cores running subprograms according to the sequence to obtain a processed message corresponding to the message to be processed.
The message processing method based on multiple cores provided by the embodiment of the invention divides the message processing process into a plurality of subprograms, and each core runs one subprogram on equipment using a multi-core processor, so that the message processing can be simultaneously carried out on a plurality of cores, and the equipment can simultaneously process a plurality of messages, thereby effectively improving the message processing speed and the message throughput of the network node equipment.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of the OSI seven-layer model in the prior art;
FIG. 2 is a schematic diagram illustrating a process of decapsulating a packet in the prior art;
fig. 3 is a schematic flowchart of a multi-core based message processing method according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a multi-core based packet encapsulation processing flow according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a multi-core-based message processing apparatus according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 3 is a schematic flowchart of a multi-core based message processing method according to an embodiment of the present invention, and as shown in fig. 3, the method includes:
step S31, dividing the message processing process into a plurality of subprograms in sequence, wherein each subprogram runs in one CPU core of the multi-core processor;
specifically, for the multi-core processor, in order to better utilize multi-core resources, the messages processed by the multi-core processor may be sequentially divided into a plurality of subroutines according to the sequence of the message processing process, where the number of the subroutines is less than or equal to the number of CPU cores of the multi-core processor, a minimum unit according to which the subroutines are divided may be a function that can be separately implemented in each of the CPU cores in the message processing process, and each subroutine is independently run in one of the CPU cores in the multi-core processor.
And step S32, receiving messages to be processed, and processing different messages to be processed in parallel, wherein each message to be processed is sequentially processed by a plurality of CPU cores running subprograms according to the sequence to obtain a processed message corresponding to the message to be processed.
Specifically, after receiving a message to be processed, the same message is sequentially processed by a plurality of CPU cores running subroutines, and after the subroutine in the last CPU core is processed, a processed message corresponding to the message is obtained, that is, for the same message, the messages are serially processed by each CPU core. And for different messages, parallel processing is carried out, namely when a first message is processed, a second message, a third message and the like can be processed, at most, messages with the number the same as that of CPU cores running the subprogram can be processed in parallel, and different CPU cores process different messages at the same time, so that multi-core resources are fully utilized, and the message processing efficiency is improved.
The message processing method based on multiple cores provided by the embodiment of the invention divides the message processing process into a plurality of subprograms, and each core runs one subprogram on equipment using a multi-core processor, so that the message processing can be simultaneously carried out on a plurality of cores, and the equipment can simultaneously process a plurality of messages, thereby effectively improving the message processing speed and the message throughput of the network node equipment.
On the basis of the foregoing embodiment, further, each of the to-be-processed packets is sequentially processed by a plurality of CPU cores running subroutines in the order, including:
a first CPU core in the CPU cores receives and processes a message to be processed to obtain a middle message;
each CPU core except the first CPU core in the plurality of CPU cores receives and processes the intermediate message processed by the last CPU core;
each CPU core except the last CPU core in the plurality of CPU cores sends the processed intermediate message to the next CPU core;
and after the last CPU core processes the corresponding intermediate message, obtaining a processed message corresponding to the message to be processed.
Specifically, N CPU cores running the subprogram are sequentially divided into core 1, core 2, …, and core N according to the subprogram execution order, where core 1 is the first CPU core, core 2 to core N-1 are intermediate CPU cores, and core N is the last CPU core. The method comprises the steps that a core 1 receives a message to be processed, the message to be processed is processed by the core 1 to obtain a middle message 1, the core 1 sends the middle message 1 to a core 2, the core 2 receives the middle message 1 sent by the core 1 and obtains a middle message 2 after being processed by the core 2, the core 2 sends the middle message 2 to a core 3, the core 3 receives the middle message 2 sent by the core 2 and obtains a middle message 3 after being processed by the core 3, the core 3 sends the middle message 3 to a core 4, and the like are carried out in sequence, other CPU cores except the core 1 sequentially receive the middle message processed by a last CPU core, except the core N, other CPU cores sequentially send the middle message processed to a next CPU core, the core N receives the middle message N-1 sent by the core N-1, and after being processed by the core N, the whole message processing flow is finished, and a final processed message of the message to be processed is obtained.
In practical application, except for the last CPU core, each core may buffer the processed intermediate packet into the buffer queue corresponding to the CPU core after processing the corresponding packet or intermediate packet, and the other CPU cores except for the first CPU core may take out the intermediate packet to be processed from the buffer queue corresponding to the last CPU core and process the intermediate packet, so that the characteristics of the queues are fully utilized, and packet processing is orderly. For example, message scheduling may be implemented by the coprocessor POW, the queue corresponding to each core is stored in the POW, and the CPU core completes the processing process of the message through interaction with the corresponding queue in the POW. When the core 1 finishes processing the message, the message is directly sent to the POW, after the message is sent, the next message is processed, at the moment, a subprogram operated by the core 2 detects that a new message enters the POW, the message is directly taken out from the POW for processing, after the processing is finished, the POW is hung back, and at the moment, the message is taken out by the core 3 and processed until the message processing is finished. The queues are used for distinguishing which step the current message is processed to, different queues are correspondingly placed after different subprograms are processed, after the queues are divided, the subprograms running on different cores can accurately take the message needing to be analyzed, and the queues are stored in the POW and managed by the POW, so that CPU resources are not consumed.
For example, when encapsulating a packet, the packet processing procedure may be sequentially divided into: an application layer subprogram, a presentation layer subprogram, a session layer subprogram, a transport layer subprogram, a network layer subprogram, a link layer subprogram, and a physical layer subprogram, that is, a conventional protocol stack program is divided into 7 subprograms, each subprogram is run on an independent CPU core, and it is assumed that each subprogram runs from top to bottom cores 0 to 6, respectively. The link layer subroutine and the physical layer subroutine may also be combined in the same CPU core, which is not limited herein.
Fig. 4 is a schematic diagram of a multi-core based packet encapsulation processing flow provided in an embodiment of the present invention, and as shown in fig. 4, an application layer subprogram on a core 0 applies for packet caching and fills an application layer data load, and after the application layer subprogram completes processing, the packet is put into a queue 1. After the message is enqueued, the message is taken out by the presentation layer subprogram running on the core 1, then the presentation layer data is filled, and after the presentation layer subprogram finishes processing, the message is put into the queue 2. And the subprograms on other cores sequentially process the messages processed by the previous subprogram. Finally, the packaged message reaches the physical layer, and the physical layer subprogram sends the message out. When the physical layer subprogram sends out the first message, the application layer subprogram processes the 7 th message in parallel, which means that the layer subprogram processes the 6 th message in parallel, … …, and the link layer subprogram processes the 2 nd message in parallel, thus, the pipeline mode concurrent processing of the messages is achieved. Similarly, when decapsulating a packet, the packet processing procedure may be sequentially divided into: each subprogram runs on an independent CPU core, and the processing process is opposite to the message encapsulation process and is not described again here.
The message processing method based on multiple cores provided by the embodiment of the invention divides the message processing process into a plurality of subprograms, and each core runs one subprogram on equipment using a multi-core processor, so that the message processing can be simultaneously carried out on a plurality of cores, and the equipment can simultaneously process a plurality of messages, thereby effectively improving the message processing speed and the message throughput of the network node equipment.
Based on the same inventive concept, an embodiment of the present invention further provides a multi-core based message processing apparatus, as shown in fig. 5, including: a dividing module 51 and a processing module 52, wherein:
the dividing module 51 is configured to sequentially divide a message processing process into a plurality of subroutines, where each subroutine operates in one of the CPU cores of the multi-core processor; the processing module 52 is configured to receive messages to be processed, and process different messages to be processed in parallel, where each message to be processed is sequentially processed by multiple CPU cores running subroutines according to the sequence, and then a processed message corresponding to the message to be processed is obtained.
As with the above apparatus, optionally, the processing module 52 is specifically configured to:
a first CPU core in the CPU cores receives and processes a message to be processed to obtain a middle message;
each CPU core except the first CPU core in the plurality of CPU cores receives and processes the intermediate message processed by the last CPU core;
each CPU core except the last CPU core in the plurality of CPU cores sends the processed intermediate message to the next CPU core;
and after the last CPU core processes the corresponding intermediate message, obtaining a processed message corresponding to the message to be processed.
As with the above apparatus, optionally, the processing module 52 is specifically configured to:
each CPU core except the last CPU core in the plurality of CPU cores caches the processed intermediate message to a cache queue corresponding to the CPU core;
and each CPU core except the first CPU core in the plurality of CPU cores takes out the next intermediate message to be processed from the cache queue corresponding to the last CPU core and processes the intermediate message.
Optionally, the packet processing procedure includes a packet encapsulation procedure or a packet decapsulation procedure.
Optionally, if the packet processing process is a packet encapsulation process, the plurality of sub-programs sequentially include: an application layer subroutine, a presentation layer subroutine, a session layer subroutine, a transport layer subroutine, a network layer subroutine, a link layer subroutine, and a physical layer subroutine.
Optionally, if the packet processing process is a packet decapsulation process, the plurality of sub-programs sequentially include: a physical layer subroutine, a link layer subroutine, a network layer subroutine, a transport layer subroutine, a session layer subroutine, a presentation layer subroutine, and an application layer subroutine.
The apparatus provided in the embodiment of the present invention is configured to implement the method, and its functions specifically refer to the method embodiment, which is not described herein again.
Fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, and as shown in fig. 6, the electronic device includes: a processor (processor)61, a memory (memory)62, and a bus 63;
wherein, the processor 61 and the memory 62 complete the communication with each other through the bus 63;
the processor 61 is configured to call program instructions in the memory 62 to perform the methods provided by the above-described method embodiments, including, for example: sequentially dividing the message processing process into a plurality of subprograms, wherein each subprogram runs in one CPU core of a multi-core processor; receiving messages to be processed, and processing different messages to be processed in parallel, wherein each message to be processed is sequentially processed by a plurality of CPU cores running subprograms according to the sequence to obtain a processed message corresponding to the message to be processed.
An embodiment of the present invention discloses a computer program product, which includes a computer program stored on a non-transitory computer readable storage medium, the computer program including program instructions, when the program instructions are executed by a computer, the computer can execute the methods provided by the above method embodiments, for example, the method includes: sequentially dividing the message processing process into a plurality of subprograms, wherein each subprogram runs in one CPU core of a multi-core processor; receiving messages to be processed, and processing different messages to be processed in parallel, wherein each message to be processed is sequentially processed by a plurality of CPU cores running subprograms according to the sequence to obtain a processed message corresponding to the message to be processed.
Embodiments of the present invention provide a non-transitory computer-readable storage medium, which stores computer instructions, where the computer instructions cause the computer to perform the methods provided by the above method embodiments, for example, the methods include: sequentially dividing the message processing process into a plurality of subprograms, wherein each subprogram runs in one CPU core of a multi-core processor; receiving messages to be processed, and processing different messages to be processed in parallel, wherein each message to be processed is sequentially processed by a plurality of CPU cores running subprograms according to the sequence to obtain a processed message corresponding to the message to be processed.
Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
The above-described embodiments of the apparatuses and the like are merely illustrative, wherein the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the embodiments of the present invention, and are not limited thereto; although embodiments of the present invention have been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (14)
1. A message processing method based on multiple cores is characterized by comprising the following steps:
sequentially dividing the message processing process into a plurality of subprograms, wherein each subprogram runs in one CPU core of a multi-core processor;
receiving messages to be processed, and processing different messages to be processed in parallel, wherein each message to be processed is sequentially processed by a plurality of CPU cores running subprograms according to the sequence to obtain a processed message corresponding to the message to be processed.
2. The method according to claim 1, wherein each of the messages to be processed sequentially passes through a plurality of CPU cores running subroutines in the order, including:
a first CPU core in the CPU cores receives and processes a message to be processed to obtain a middle message;
each CPU core except the first CPU core in the plurality of CPU cores receives and processes the intermediate message processed by the last CPU core;
each CPU core except the last CPU core in the plurality of CPU cores sends the processed intermediate message to the next CPU core;
and after the last CPU core processes the corresponding intermediate message, obtaining a processed message corresponding to the message to be processed.
3. The method of claim 2, wherein sending the processed intermediate packet to a next CPU core of each of the plurality of CPU cores except for a last CPU core comprises:
each CPU core except the last CPU core in the plurality of CPU cores caches the processed intermediate message to a cache queue corresponding to the CPU core;
correspondingly, each CPU core of the plurality of CPU cores except for the first CPU core receives and processes the intermediate packet processed by the previous CPU core, including:
and each CPU core except the first CPU core in the plurality of CPU cores takes out the next intermediate message to be processed from the cache queue corresponding to the last CPU core and processes the intermediate message.
4. The method of claim 1, wherein the packet processing procedure comprises a packet encapsulation procedure or a packet decapsulation procedure.
5. The method of claim 4, wherein if the packet processing procedure is a packet encapsulation procedure, the plurality of subroutines are in turn: an application layer subroutine, a presentation layer subroutine, a session layer subroutine, a transport layer subroutine, a network layer subroutine, a link layer subroutine, and a physical layer subroutine.
6. The method of claim 4, wherein if the packet processing procedure is a packet decapsulation procedure, the plurality of subroutines are in turn: a physical layer subroutine, a link layer subroutine, a network layer subroutine, a transport layer subroutine, a session layer subroutine, a presentation layer subroutine, and an application layer subroutine.
7. A message processing apparatus based on multiple cores is characterized by comprising:
the dividing module is used for sequentially dividing the message processing process into a plurality of subprograms, and each subprogram runs in one CPU core of the multi-core processor;
and the processing module is used for receiving messages to be processed and processing different messages to be processed in parallel, wherein each message to be processed is sequentially processed by a plurality of CPU cores running subprograms according to the sequence to obtain a processed message corresponding to the message to be processed.
8. The apparatus of claim 7, wherein the processing module is specifically configured to:
a first CPU core in the CPU cores receives and processes a message to be processed to obtain a middle message;
each CPU core except the first CPU core in the plurality of CPU cores receives and processes the intermediate message processed by the last CPU core;
each CPU core except the last CPU core in the plurality of CPU cores sends the processed intermediate message to the next CPU core;
and after the last CPU core processes the corresponding intermediate message, obtaining a processed message corresponding to the message to be processed.
9. The apparatus of claim 8, wherein the processing module is specifically configured to:
each CPU core except the last CPU core in the plurality of CPU cores caches the processed intermediate message to a cache queue corresponding to the CPU core;
and each CPU core except the first CPU core in the plurality of CPU cores takes out the next intermediate message to be processed from the cache queue corresponding to the last CPU core and processes the intermediate message.
10. The apparatus of claim 7, wherein the packet processing procedure comprises a packet encapsulation procedure or a packet decapsulation procedure.
11. The apparatus of claim 7, wherein if the packet processing procedure is a packet encapsulation procedure, the plurality of subroutines are in turn: an application layer subroutine, a presentation layer subroutine, a session layer subroutine, a transport layer subroutine, a network layer subroutine, a link layer subroutine, and a physical layer subroutine.
12. The apparatus of claim 7, wherein if the packet processing procedure is a packet decapsulation procedure, the plurality of subroutines are in turn: a physical layer subroutine, a link layer subroutine, a network layer subroutine, a transport layer subroutine, a session layer subroutine, a presentation layer subroutine, and an application layer subroutine.
13. An electronic device, comprising:
the processor and the memory are communicated with each other through a bus; the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform the method of any of claims 1 to 6.
14. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the method according to any one of claims 1 to 6.
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