CN114143628B - A multi-rate digital acquisition device and method - Google Patents

Abstract

The invention discloses a multi-rate digital acquisition device and method, belonging to the field of power system automation. The device includes: a multi-core processor plug-in, a data sending plug-in, a power plug-in, and a human-machine interface plug-in; the digital signal processor DSP includes : Receive decoding module, digital filtering module, linear interpolation module and combined transmission module; judge the frame format of the received sampling data by judging the sampling data according to the accessed digital signal sampling rate through the receiving decoding module; analyze the data frame reception time stamp , and cache the sampled data into partitions in the buffer; perform digital filtering processing on the sampled data in the data buffer area of the receiving decoding module through the digital filtering module, and update the sampling quality through the linear interpolation module. This invention solves the problem of output from the same device. The digital sampling signal rate is fixed, and then the received data is processed and forwarded at different rates to meet the different sampling rate requirements of different interactive devices.

Description

A multi-rate digital acquisition device and method

Technical field

The invention belongs to the field of power system automation, and specifically relates to a multi-rate digital acquisition device and method.

Background technique

Smart substations use electronic transformers or conventional transformers to convert primary current or voltage into digital signals through a merging unit, and then send them to secondary equipment such as protection and measurement and control through optical fibers. The digital sampling signal output by the merging unit has a fixed rate and cannot meet the requirements of different equipment in the station for different sampling rates of primary current or voltage. In addition, since the digital sampling rate output by the merging unit is only 4kHz, it cannot meet the high-rate collection requirements of primary current or voltage by other equipment, such as power quality monitoring terminals.

As renewable energy and wind power technology continue to develop at a rapid pace, flexible DC transmission technology has become more and more widely used. As a key device in the flexible DC grid, DC electronic transformers are required to provide high-rate sampling and multi-rate output. primary current or voltage digital signal.

Contents of the invention

Purpose of the invention: In order to overcome the deficiencies in the prior art, the present invention provides a collection method and device that can simultaneously output digital signals with different sampling rates to meet the requirements of different equipment in smart substations for different sampling rates of primary current or voltage, and is a flexible DC The network control and protection system provides high-rate sampling and multi-rate output primary current or voltage digital signals.

Technical solution: In the first aspect, the present invention provides a multi-rate digital acquisition method, which includes the following steps:

Receive different types of digital signals, determine the format of the sampling data frame according to the sampling rate configured when receiving the digital signal, and analyze the data frame confirmed by the CRC check code to obtain sampling data at different sampling rates and store the data cache area;

Perform digital filtering on the sampled data in the data cache area to filter out high-frequency interference data;

Read the sampling point time scale of the filtered sampling data, perform linear interpolation calculation on the sampling data based on the sampling point time scale, obtain a digital sampling value that meets the transmission rate requirements, and update the sampling data according to the digital sampling value;

Obtain the sending rate parameters of sampled data at different sampling rates. Based on the different sending rate parameters, update the sampling data in the sending buffer accordingly, and send the sampling data at different sampling rates to the sending register. According to the status of the sending register, the corresponding sending rate reaches Time output sampling data at different sampling rates.

In a further embodiment, when determining the sample data frame format:

Determine whether the sampling data frame is received according to the sampling rate; if not received, it is considered that the frame is lost and continues to receive;

If a sampling data frame is received, the frame format of the received sampling data is judged; if the data frame format is judged to be correct, the data frame reception time stamp is parsed, and the received time stamp is stored in the time stamp buffer; if the data frame is judged to be in correct format, The frame format is incorrect, continue to receive.

In a further embodiment, parsing the data frame after confirmation by the CRC check code includes:

Determine the CRC check code of the data frame from the received sampled data;

Determine whether the CRC check code is correct. If it is correct, it will be parsed according to the data frame definition format, and the sampled data at different sampling rates will be obtained and stored in the data buffer area; if it is incorrect, the optical fiber receiving module will be reset and the sampled data will be cleared.

In a further embodiment, the linear interpolation calculation process for the sampled data based on the sampling point time scale is as follows:

Search the interpolated sampling point time stamp in the time stamp buffer area;

Read the sampling data corresponding to the time scale in the data buffer area, and then perform linear interpolation calculation on the sampling data;

If the interpolated sampling point time stamp is not found, the digital sampling value is cleared and the sampling quality is set to invalid.

In a further embodiment, the sampled data at different sampling rates is output at the corresponding sending rate arrival time according to the sending register status:

If the status of the sending register is normal, it is judged whether the data sending time reaches the current sending rate arrival time. If it does, the sampling data is sent. If it does not arrive, the sampling data is not sent;

If the status of the sending register is abnormal, the optical fiber sending module will be reset; no sampling data will be sent.

In a second aspect, the present invention provides a multi-rate digital acquisition device, including: a multi-core processor plug-in, a data sending plug-in, a power plug-in, and a human-machine interface plug-in;

Wherein, the multi-core processor plug-in is connected to the human-machine interface plug-in, and the multi-core processor plug-in includes a central processing unit CPU and a digital signal processor DSP; the digital signal processor DSP includes: a receiving and decoding module, a digital filtering module, Linear interpolation module and combined sending module;

The receiving and decoding module is used to receive, judge, and analyze sampled data at different rates and store it in the data cache;

The digital filtering module is used to perform digital filtering processing on the sampled data in the data buffer area and filter high-frequency interference data;

The linear interpolation module is used to perform linear interpolation calculation on the sampling data based on the sampling point time scale, obtain a digital sampling value that meets the transmission rate requirements, and update the sampling data according to the digital sampling value;

The combined sending module is used to obtain the sending rate parameter of the sampling data, update the sending buffer sampling data to the sending register based on the sending rate parameter, and output the sampling data at different sampling rates at the corresponding sending rate arrival time according to the sending register status.

The central processing unit CPU is connected to the background monitoring system to manage and record the operation of the entire device;

The digital signal processor DSP is used to receive multiple digital sampling signals of different types through optical fibers and process and combine the data;

The data sending plug-in sends the combined digital sampling signals of different rates processed by the digital signal processor DSP;

The human-machine interface plug-in is used for information output of the multi-core processor plug-in;

The power plug-in is electrically connected to the multi-core processor plug-in, the data sending plug-in, the power plug-in, and the human-machine interface plug-in through the motherboard power supply circuit that is electrically connected thereto; and is used to provide power for the multi-core processor plug-in, the data sending plug-in, and all The human-machine interface plug-in is powered by the power supply described above.

In a further embodiment, the receiving and decoding module divides the time stamp buffer area and the data buffer area in the buffer.

In a further embodiment, the digital signal processor DSP is connected to the data sending plug-in through an I/O bus, and the data sending plug-in sends and processes the combined digital sampling signal at different sending rates; the I/O bus includes : Data bus and CAN bus, and connects multi-core processor plug-in, data sending plug-in and human-machine interface plug-in through I/O bus for data interaction.

In a further embodiment, the human-machine interface plug-in is used to input instructions to the multi-core processor plug-in through other input devices in the external substation or output data processed by the multi-core processor plug-in through the output device, as well as monitoring information from the monitoring background. .

Beneficial effects: Compared with the existing technology, the present invention has the following advantages:

(1) The problem of fixed rate of digital sampling signals output by the same device is solved through the receiving decoding module, digital filtering module, linear interpolation module and combined sending module, and then the sampling data received by the optical fiber module is calculated and processed through the multi-core processor plug-in Afterwards, the data is forwarded at different rates through the data sending plug-in to simultaneously meet the different requirements of different interactive devices for sampling rates, and to provide digital signals with different sampling rates for different devices.

(2) Connect other output devices in the substation through human-machine interface plug-ins to efficiently display the output collected data in real time, or control the collection process through input device definitions.

Description of the drawings

Figure 1 is a schematic structural diagram of the device according to the present invention;

Figure 2 is a flow chart of the receiving and decoding module in the present invention.

Figure 3 is a flow chart of the linear interpolation module in the present invention.

Figure 4 is a flow chart of the combined sending module in the present invention.

Detailed ways

In order to fully understand the technical content of the present invention, the technical solutions of the present invention are further introduced and explained below in conjunction with specific embodiments, but are not limited thereto.

Embodiment 1. A multi-rate digital acquisition device provided by the present invention is further described with reference to Figure 1, which includes: a multi-core processor plug-in, a data sending plug-in, a power plug-in, and a human-machine interface plug-in;

The multi-core processor plug-in is connected to the human-machine interface plug-in. The multi-core processor plug-in includes a central processing unit CPU and a digital signal processor DSP; the digital signal processor DSP includes: a receiving and decoding module, a digital filtering module, a linear interpolation module and a combined sending module;

The receiving and decoding module is used to receive, judge, and analyze sampled data at different rates and store it in the data buffer;

The digital filtering module is used to digitally filter the sampled data in the data buffer area and filter high-frequency interference data;

The linear interpolation module is used to perform linear interpolation calculation on the sampling data based on the sampling point time scale, obtain the digital sampling value that meets the transmission rate requirements, and update the sampling data according to the digital sampling value;

The combined sending module is used to obtain the sending rate parameters of the sampling data, update the sending buffer sampling data to the sending register based on the sending rate parameters, and output the sampling data at different sampling rates at the corresponding sending rate arrival time according to the sending register status.

The central processing unit CPU is connected to the background monitoring system to manage and record the operation of the entire device;

The digital signal processor DSP is used to receive multiple different types of digital sampling signals through optical fibers and process and combine the data;

The data sending plug-in sends the combined digital sample signal processed by the digital signal processor DSP;

The human-machine interface plug-in is used to output information from the multi-core processor plug-in;

The power plug-in is electrically connected to the multi-core processor plug-in, the data sending plug-in, the power plug-in, and the human-machine interface plug-in through the power supply circuit of the mainboard; and is used to supply power to the multi-core processor plug-in, the data sending plug-in, and the human-machine interface plug-in.

The central processing unit CPU is used for field programmable logic gate array FPGA; the digital signal processor DSP is used for advanced instruction processing.

The digital signal processor DSP receives multiple digital sampling signals through optical fibers and processes and merges the data. The digital signal processor DSP includes: a receiving and decoding module, a digital filtering module, a linear interpolation module and a combining and transmitting module.

Among them, the receiving and decoding module performs data classification and caching by dividing buffer areas in the buffer, including: time stamp buffer area and data buffer area;

Digitally filter the sampled data in the data buffer area of the receiving decoding module, using a second-order low-pass Butterworth filter, whose z-domain transfer function is:

H(z)＝(b ₀ +b ₁ *z ^-1 +b ₂ *z ^-2 )/(1-a ₁ *z ^-1 -a ₂ *z ^-2 )

In the formula, b ₀ , b ₁ , b ₂ , a ₁ , and a ₂ respectively represent filter coefficients; z ^-1 and z ^-2 respectively represent the complex variables of discrete sampling z-domain transformation, which are composed of the digital filter cutoff frequency f ₀ and the transmit buffer The sampling data rate of the area is determined; the linear interpolation function of the linear interpolation module is a linear polynomial, and the interpolation error on the interpolation node is zero. Its geometric meaning is to use point A (x ₀ , y ₀ ) and point B (x ₁ , y ₁ ) to approximate the original function by the straight line f(x)

Among them, y ₀ and y ₁ are the sampling data corresponding to the time of x ₀ and x ₁ respectively (x ₁ > x ₀ ), and x is the DSP interrupt time.

The flow of the linear interpolation module is shown in Figure 3. The specific implementation method is as follows: According to the DSP interrupt time x, search the interpolation sampling point time scale in the time scale buffer area, that is, x ₁ and x ₀ , satisfying x ₁ > x > x ₀ ; Further read the sampling data corresponding to the data buffer area, that is, y ₀ and y ₁ ; further substitute (x ₀ , y ₀ ) and (x ₁ , y ₁ ) into the above-mentioned linear polynomial to calculate the sampling value of x at the DSP interrupt time , that is, the digital sampling value of the sending rate; if the interpolated sampling point time stamp is not found in the time stamp buffer area, the digital sampling value will be cleared and the sampling quality will be invalid.

The combined sending module determines whether to send the data in the buffer area based on the status of the sending register.

The digital signal processor DSP is connected to the data sending plug-in through the I/O bus, and the data sending plug-in sends and processes the combined digital sampling signal.

The I/O bus includes: data bus and CAN bus, and is connected to the multi-core processor plug-in and data sending plug-in through the I/O bus for data interaction.

The human-machine interface plug-in is used to input instructions to the multi-core processor plug-in through other input devices in the external substation or output data processed by the multi-core processor plug-in through output devices, as well as monitoring information from the monitoring background.

Embodiment 2: This embodiment further explains with reference to Figures 2 to 3 that this embodiment provides a multi-rate digital acquisition method, which includes the following steps:

Receive different types of digital signals, determine the format of the sampling data frame according to the sampling rate configured when receiving the digital signal, and analyze the data frame confirmed by the CRC check code to obtain sampling data at different sampling rates and store the data cache area;

Perform digital filtering on the sampled data in the data cache area to filter out high-frequency interference data;

Read the sampling point time scale of the filtered sampling data, perform linear interpolation calculation on the sampling data based on the sampling point time scale, obtain a digital sampling value that meets the transmission rate requirements, and update the sampling data according to the digital sampling value;

Obtain the sending rate parameters of sampled data at different sampling rates. Based on the different sending rate parameters, update the sampling data in the sending buffer accordingly, and send the sampling data at different sampling rates to the sending register. According to the status of the sending register, the corresponding sending rate reaches Time output sampling data at different sampling rates.

When determining the sampling data frame format:

Determine whether the sampling data frame is received according to the sampling rate; if not received, it is considered that the frame is lost and continues to receive;

If a sampling data frame is received, the frame format of the received sampling data is judged; if the data frame format is judged to be correct, the data frame reception time stamp is parsed, and the received time stamp is stored in the time stamp buffer; if the data frame is judged to be in correct format, The frame format is incorrect, continue to receive.

The analysis of the data frame confirmed by the CRC check code includes:

Determine the CRC check code of the data frame from the received sampled data;

Determine whether the CRC check code is correct. If it is correct, it will be parsed according to the data frame definition format, and the sampled data at different sampling rates will be obtained and stored in the data buffer area; if it is incorrect, the optical fiber receiving module will be reset and the sampled data will be cleared.

In a further embodiment, the linear interpolation calculation process for the sampled data based on the sampling point time scale is as follows:

Search the interpolated sampling point time stamp in the time stamp buffer area;

Read the sampling data corresponding to the time scale in the data buffer area, and then perform linear interpolation calculation on the sampling data;

If the interpolated sampling point time stamp is not found, the digital sampling value is cleared and the sampling quality is set to invalid.

According to the status of the transmit register, the sampled data at different sampling rates are output at the corresponding transmission rate arrival time:

If the status of the sending register is normal, it is judged whether the data sending time reaches the current sending rate arrival time. If it does, the sampling data is sent. If it does not arrive, the sampling data is not sent;

If the status of the sending register is abnormal, the optical fiber sending module will be reset; no sampling data will be sent.

The present invention solves the problem of fixed rate of digital sampling signals output by the same device by receiving and decoding modules, digital filtering modules, linear interpolation modules and combined transmission modules, and then calculates and processes the sampling data received by the optical fiber module through the multi-core processor plug-in. , and then forwarded at different rates through the data sending plug-in to meet the different requirements of different interactive devices for sampling rates, and can provide digital signals with different sampling rates for different devices; through the human-machine interface plug-in, it can be connected to other output devices in the substation to make it efficient Display and output collected data in real time, or control the collection process through input device definitions.

Those skilled in the art will understand that embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment that combines software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each process and/or block in the flowchart illustrations and/or block diagrams, and combinations of processes and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing device produce a use A device for realizing the functions specified in one process or multiple processes of the flowchart and/or one block or multiple blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory that causes a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction means, the instructions The device implements the functions specified in a process or processes of the flowchart and/or a block or blocks of the block diagram.

These computer program instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operating steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby executing on the computer or other programmable device. Instructions provide steps for implementing the functions specified in a process or processes of a flowchart diagram and/or a block or blocks of a block diagram.

The above are only preferred embodiments of the present invention. It should be noted that those of ordinary skill in the art can also make several improvements and modifications without departing from the technical principles of the present invention. These improvements and modifications It should also be regarded as the protection scope of the present invention.

Claims (5)

1. A multi-rate digital acquisition method, characterized in that it includes the following steps: The receiving and decoding module receives different types of sampling data, determines the sampling data frame format according to the sampling rate configured when receiving the sampling data, and analyzes the data frame confirmed by the CRC check code to obtain sampling data at different sampling rates and Store in the data buffer area; the receiving decoding module divides the time stamp buffer area and data buffer area in the buffer; The digital filtering module performs digital filtering on the sampled data in the data buffer area to filter high-frequency interference data; among them, the specific process of digital filtering on the sampled data in the data buffer area is: Digitally filter the sampled data in the data buffer area of the receiving decoding module, using a second-order low-pass Butterworth filter, whose z-domain transfer function is: In the formula, ,/> ,/> ,/> ,/> Represent filter coefficients respectively;/> ,/> Respectively represent the complex variables of discrete sampling z-domain transformation, which are determined by the digital filter cutoff frequency f ₀ and the sampling data rate of the sending buffer area; The linear interpolation module reads the sampling point time scale of the filtered sampling data, performs linear interpolation calculation on the sampling data based on the sampling point time scale, obtains the digital sampling value that meets the transmission rate requirements, and updates the sampling data based on the digital sampling value; among them, based on The linear interpolation calculation process of the sampling data on the sampling point time scale is as follows: According to DSP interrupt time ,Search for the interpolated sampling point time scale in the time scale buffer area, that is/> and/> , satisfy/> >/> >/> ;Further read the sampling data corresponding to the sampling point time scale in the data buffer area, that is/> and/> ;Further will and/> Substitute the linear interpolation function to calculate the DSP interrupt time/> The sampling value is the digital sampling value of the sending rate; if the interpolated sampling point time stamp is not found in the time stamp buffer area, the digital sampling value will be cleared and the sampling quality will be invalid; The combined sending module obtains the sending rate parameters of the sampled data at different sampling rates. Based on the different sending rate parameters, it updates the sampling data in the sending buffer accordingly, and sends the sampling data at different sampling rates to the sending register. According to the sending register status, The corresponding sending rate reaching time outputs the sampled data at different sampling rates, wherein the specific process of outputting the sampling data at different sampling rates at the corresponding sending rate reaching time according to the sending register state is as follows: If the status of the sending register is normal, it is judged whether the data sending time reaches the current sending rate reaching time. If it does, the sampling data is sent. If it does not arrive, the sampling data is not sent; If the status of the sending register is abnormal, the sampling data will not be sent. 2. A multi-rate digital acquisition method according to claim 1, characterized in that when determining the sampling data frame format: Determine whether the sampling data frame is received according to the sampling rate; if not received, it is considered that the frame is lost and continues to receive; If a sampling data frame is received, the frame format of the received sampling data is judged; if the data frame format is judged to be correct, the data frame reception time stamp is parsed, and the received time stamp is stored in the time stamp buffer; if the data frame is judged to be in correct format, The frame format is incorrect, continue to receive. 3. A multi-rate digital acquisition method according to claim 1, characterized in that parsing the data frame confirmed by the CRC check code includes: Determine the CRC check code of the data frame from the received sampled data; Determine whether the CRC check code is correct. If it is correct, it will be parsed according to the data frame definition format, and the sampled data at different sampling rates will be obtained and stored in the data buffer; if it is incorrect, the sampled data will be cleared. 4. A multi-rate digital acquisition device, characterized in that, based on the acquisition method of claim 1, it includes: a multi-core processor plug-in, a data sending plug-in, a power plug-in and a human-machine interface plug-in; Wherein, the multi-core processor plug-in is connected to a human-machine interface plug-in, and the multi-core processor plug-in includes a central processing unit CPU and a digital signal processor DSP. The central processing unit CPU is used for field programmable logic gate array FPGA; digital signal processing The digital signal processor DSP is used for advanced instruction processing; the digital signal processor DSP includes: a receiving and decoding module, a digital filtering module, a linear interpolation module and a combined sending module; The receiving and decoding module is used to receive, judge and parse out the sampling data at different rates and store it in the data buffer area; wherein, the receiving and decoding module is used to receive different types of sampling data, determined according to the sampling rate configured when receiving the sampling data. Its sampling data frame format; The digital filtering module is used to perform digital filtering processing on the sampled data in the data buffer area and filter high-frequency interference data; The linear interpolation module is used to perform linear interpolation calculation on the sampled data according to the linear interpolation function based on the sampling point time scale, obtain a digital sample value that meets the transmission rate requirements, and update the sample data according to the digital sample value; The combined sending module is used to obtain the sending rate parameter of the sampled data, update the sending buffer sampling data based on the sending rate parameter and send it to the sending register, and output the samples at different sampling rates at the corresponding sending rate arrival time according to the sending register status. Data; wherein, the combined sending module determines whether to send the data in the sending buffer according to the sending register status; The central processing unit CPU is connected to the background monitoring system to manage and record the operation of the entire device; The human-machine interface plug-in is used for information output of the multi-core processor plug-in; The power plug-in is electrically connected to the multi-core processor plug-in, the data sending plug-in, and the human-machine interface plug-in through the motherboard power supply circuit that is electrically connected to it, and is used to provide power for the multi-core processor plug-in, the data sending plug-in, and the human-machine interface plug-in. Interface plug-in power supply; The digital signal processor DSP is connected to the data sending plug-in through the I/O bus, and the data sending plug-in sends processed and combined sampled data at different sending rates; the I/O bus includes: a data bus and a CAN bus, And connect the multi-core processor plug-in, data sending plug-in and human-machine interface plug-in through the I/O bus for data interaction. 5. A multi-rate digital acquisition device according to claim 4, characterized in that the human-machine interface plug-in inputs instructions to the multi-core processor plug-in through other input devices in the external substation or outputs the multi-core processor plug-in through an output device. The data processed by the plug-in and the monitoring information in the monitoring background.