CN114122012A - Preparation method of array substrate and array substrate - Google Patents
Preparation method of array substrate and array substrate Download PDFInfo
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Abstract
本申请公开了一种阵列基板的制备方法及阵列基板。所述阵列基板包括氧化物半导体层、栅极和形成在所述氧化物半导体层和所述栅极之间的金属氧化物绝缘层，所述金属氧化物绝缘层与所述氧化物半导体层相接触，其中，在形成所述金属氧化物绝缘层的步骤之后，所述阵列基板的制备方法包括以下步骤：对所述金属氧化物绝缘层进行激光照射处理。本申请提高了氧化物TFT的迁移率。
The present application discloses a preparation method of an array substrate and the array substrate. The array substrate includes an oxide semiconductor layer, a gate electrode, and a metal oxide insulating layer formed between the oxide semiconductor layer and the gate electrode, the metal oxide insulating layer being the same as the oxide semiconductor layer. contact, wherein, after the step of forming the metal oxide insulating layer, the preparation method of the array substrate includes the following steps: performing laser irradiation treatment on the metal oxide insulating layer. The present application improves the mobility of oxide TFTs.
Description
Technical Field
The application relates to the technical field of display, in particular to a preparation method of an array substrate and the array substrate.
Background
In the field of Active matrix flat panel displays, Active Matrix Liquid Crystal Displays (AMLCDs) and Active matrix organic Light-Emitting diodes (AMOLEDs) are mainly included, in which a thin film transistor (tft) has an irreplaceable role as a pixel switch in a Display product. As high resolution, large size and flexible display have become new directions for the development of display technology, higher requirements are also placed on the performance of thin film transistors.
Oxide Thin Film Transistors (TFTs) are particularly prominent in large-sized, high-resolution, and flexible displays because of their amorphous structure, higher mobility than a-Si, and lower cost. In order to improve the stability of the oxide TFT, a TFT having an Etch Stop Layer (ESL) structure is widely used, and the structure can effectively reduce the influence of external environmental factors and the etching damage of the source and drain electrodes on the back channel. However, the array fabrication method of the ESL structure requires more mask times and significantly increases the TFT size and parasitic capacitance. The Back Channel Etch (BCE) TFT does not need an Etch stop layer, and the Channel can be significantly reduced compared to the ESL structure, thereby having lower production cost and technical advantages compared to the ESL structure. For the TFT with the top gate type structure, the source-drain electrode and the grid electrode are overlapped less, the parasitic capacitance is small, but the number of the light covers is large, the cost is high, and the application in the AMOLED is wide. With the increasing display requirements, i.e., the popularization of high resolution and high refresh rate, higher requirements are placed on the mobility of the TFT, and the mobility of the oxide TFT, which is currently available for mass production, is low.
Disclosure of Invention
The embodiment of the application provides a preparation method of an array substrate and the array substrate, so as to improve the mobility of an oxide TFT.
The embodiment of the application provides a preparation method of an array substrate, the array substrate comprises an oxide semiconductor layer, a grid electrode and a metal oxide insulating layer formed between the oxide semiconductor layer and the grid electrode, the metal oxide insulating layer is in contact with the oxide semiconductor layer, and after the step of forming the metal oxide insulating layer, the preparation method of the array substrate comprises the following steps:
and performing laser irradiation on the metal oxide insulating layer.
Alternatively, in some embodiments of the present application, in the step of laser irradiation of the metal oxide insulating layer, the laser intensity in the laser irradiation is positively correlated with the oxygen vacancy content in the metal oxide insulating layer.
Optionally, in some embodiments of the present application, after the step of laser irradiating the metal oxide insulating layer, the content of oxygen vacancies in the metal oxide insulating layer is greater than 23%.
Optionally, in some embodiments of the present application, the material of the metal oxide insulating layer includes Ta2O5、ZrO2、HfO2、TiO2、Al2O3、SrO2And La2O3One or more of (a).
Optionally, in some embodiments of the present application, the material of the metal oxide insulating layer is Ta2O5。
Optionally, in some embodiments of the present application, the metal oxide insulating layer has a thickness of 20nm to 50 nm.
The embodiment of the application also provides an array substrate, and the array substrate is prepared by adopting the preparation method of the array substrate in any one of the embodiments.
Optionally, in some embodiments of the present application, the array substrate further includes a gate insulating layer, the gate insulating layer is disposed on a side of the metal oxide insulating layer close to the gate, and a material of the gate insulating layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.
Optionally, in some embodiments of the present application, the array substrate further includes a base, the gate is located on a side of the oxide semiconductor layer close to the base, and the array substrate further includes:
the source drain metal layer is arranged on one side, far away from the metal oxide insulating layer, of the oxide semiconductor layer and comprises a source electrode and a drain electrode;
the first passivation layer is arranged on one side, far away from the oxide semiconductor layer, of the source drain metal layer;
the organic insulating layer is arranged on one side, away from the source drain metal layer, of the first passivation layer;
the common electrode is arranged on one side, far away from the first passivation layer, of the organic insulating layer;
the second passivation layer is arranged on one side, far away from the organic insulating layer, of the common electrode; and
the pixel electrode is arranged on one side, far away from the common electrode, of the second passivation layer;
the array substrate is provided with a first passivation layer, a second passivation layer, an organic insulating layer and a pixel electrode, wherein a contact hole is formed in the array substrate, the contact hole sequentially penetrates through the second passivation layer, the organic insulating layer and the first passivation layer and exposes the drain electrode, and the pixel electrode is connected with the drain electrode in the contact hole.
Optionally, in some embodiments of the present application, the array substrate further includes a base, the gate is located on a side of the oxide semiconductor layer away from the base, and the array substrate further includes:
a light shielding layer arranged on one side of the oxide semiconductor layer close to the substrate;
a buffer layer provided between the light-shielding layer and the oxide semiconductor layer;
the interlayer dielectric layer is arranged on one side of the grid electrode, which is far away from the grid electrode insulating layer;
the source drain metal layer is arranged on one side, far away from the grid electrode, of the interlayer dielectric layer and comprises a source electrode and a drain electrode;
the passivation layer is arranged on one side, away from the interlayer dielectric layer, of the source drain metal layer, a contact hole is formed in the passivation layer, and the drain electrode is exposed out of the contact hole; and
and the pixel electrode is arranged on one side of the passivation layer, which is far away from the source drain metal layer, and is connected with the drain electrode in the contact hole.
Compared with the preparation method of the array substrate in the prior art, in the preparation method of the array substrate provided by the application, the array substrate comprises the oxide semiconductor layer, the grid electrode and the metal oxide insulating layer formed between the oxide semiconductor layer and the grid electrode, and the metal oxide insulating layer is in contact with the oxide semiconductor layer.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic flow chart of a method for manufacturing an array substrate provided in the present application.
Fig. 2 is a schematic flow chart of a method for manufacturing an array substrate according to an example of the present application
Fig. 3 is a schematic structural diagram of an array substrate prepared according to an example of the present application.
Fig. 4 is a schematic flow chart of a method for manufacturing an array substrate according to example two of the present application.
Fig. 5 is a schematic structural diagram of an array substrate prepared according to example two of the present application.
Fig. 6 is a schematic structural diagram of an array substrate according to a first embodiment of the present disclosure.
Fig. 7 is a schematic structural diagram of an array substrate according to a second embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The embodiment of the application provides a preparation method of an array substrate and the array substrate. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
Referring to fig. 1, the present application provides a method for manufacturing an array substrate, the array substrate including an oxide semiconductor layer, a gate electrode, and a metal oxide insulating layer formed between the oxide semiconductor layer and the gate electrode, the metal oxide insulating layer being in contact with the oxide semiconductor layer, wherein after the step of forming the metal oxide insulating layer, the method for manufacturing the array substrate includes the steps of:
b1: the metal oxide insulating layer is irradiated with laser light.
Therefore, after the step of forming the metal oxide insulating layer, the metal oxide insulating layer is subjected to laser irradiation, so that the content of oxygen vacancies in the metal oxide insulating layer can be regulated, and the number of oxygen vacancies at the contact interface between the metal oxide insulating layer and the oxide semiconductor layer is increased under the positive bias gate voltage, so that the mobility of the thin film transistor can be improved.
The following provides a detailed description of the method for manufacturing the array substrate according to the present application with reference to specific embodiments.
Referring to fig. 2 and 3 together, an exemplary embodiment of the present invention provides a method for manufacturing an array substrate 100 with a bottom gate structure, which includes the following steps:
b11: a substrate 10 is provided.
The substrate 10 may be a hard substrate, such as a glass substrate; alternatively, the substrate 10 may also be a flexible substrate, such as a polyimide substrate, and the material of the substrate 10 is not particularly limited in this application.
B12: a gate electrode 111, a gate insulating layer 12, and a metal oxide insulating layer 13 are sequentially formed on one side of the substrate 10.
First, a gate metal layer 11 is formed on one side of a substrate 10 using a physical vapor deposition process, and the gate metal layer 11 is patterned to form a gate electrode 111. The material of the gate 111 may include one or more of copper, aluminum, molybdenum, and titanium. It should be noted that, while the gate 111 is formed, the signal trace 112 may also be formed, and the signal trace 112 may be a scan line.
Next, a gate insulating layer 12 is formed on the side of the gate 111 away from the substrate 10 by using a chemical vapor deposition process. The material of the gate insulating layer 12 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.
Finally, a metal oxide insulating layer 13 is formed on the side of the gate insulating layer 12 away from the gate 111 by using a physical vapor deposition process. The thickness of the metal oxide insulating layer 13 is 20nm to 50nm, such as 20nm, 25nm, 30nm, 35nm, 40nm, 45nm or 50 nm. Within the above thickness range, the uniformity of the distribution of oxygen vacancies in the metal oxide insulating layer 13 after the subsequent laser irradiation can be improved.
Specifically, the material of the metal oxide insulating layer 13 may include Ta2O5、ZrO2、HfO2、TiO2、Al2O3、SrO2And La2O3One or more of (a). Since the metal oxides have high dielectric constants, the metal oxide insulating layer 13 has good dielectric properties when the above materials are used.
B13: the metal oxide insulating layer 13 is irradiated with laser light.
After the metal oxide insulating layer 13 is formed, the metal oxide insulating layer 13 is subjected to laser irradiation by the femtosecond laser technique, and the content of oxygen vacancies in the metal oxide insulating layer 13 can be controlled by controlling the laser intensity and the laser irradiation time in the laser irradiation.
In this embodiment, the metal is oxidizedThe material of the insulating layer 13 may be Ta2O5. Due to Ta2O5Can effectively reduce the driving voltage and power consumption of the device, thereby utilizing laser to drive Ta2O5The generated local heat effect and the excellent processing speed of the laser can realize the Ta2O5Precise control of performance. Particularly, Ta can be effectively regulated and controlled by selecting lasers with different wavelengths2O5The content of oxygen vacancy in the film, and further the carrier concentration is adjusted.
In the present embodiment, the laser intensity in laser irradiation is positively correlated with the oxygen vacancy content in the metal oxide insulating layer 13 at a constant laser irradiation time. Wherein, after the step of performing laser irradiation on the metal oxide insulating layer 13, the oxygen vacancy content in the metal oxide insulating layer 13 is more than 23%.
Specifically, when the material of the metal oxide insulating layer 13 is Ta2O5In this case, the metal oxide insulating layer 13 includes chemical bonds such as Ta — O and C ═ O and oxygen vacancies Vo under laser irradiation2+. Referring to Table 1, Table 1 shows the laser irradiation time, the laser irradiation time without laser irradiation, and the laser irradiation time with different laser intensities (the laser intensities are 263mJ/cm, respectively)2、309mJ/cm2And 358mJ/cm2) Ta-O content, C ═ O content, and oxygen vacancy Vo2+The content change condition is as follows:
TABLE 1
From the above table, it can be seen that:
1. the oxygen vacancy content in the metal oxide insulating layer 13 is significantly increased under laser irradiation compared to the case without laser irradiation. Specifically, the oxygen vacancy content was only 22.35% without laser irradiation, the oxygen vacancy content was significantly greater than 22.35% when laser irradiation was employed, and the laser irradiation intensity was 358mJ/cm2When the oxygen vacancy content is high, the oxygen vacancy content can reach 34.02 percent.
2. Under laser irradiation, as the laser intensity increases, the oxygen vacancy content in the metal oxide insulating layer 13 also increases.
Therefore, in the present embodiment, the metal oxide insulating layer 13 after film formation is irradiated with laser light, and the intensity of laser light irradiation is increased, so that the oxygen vacancy content in the metal oxide insulating layer 13 can be significantly increased, and the carrier concentration can be increased, thereby increasing the mobility of the oxide TFT.
It should be noted that the present embodiment merely schematically illustrates the relationship between the laser irradiation intensity and the oxygen vacancy content in the metal oxide insulating layer 13, to prove that the adjustment of the oxygen vacancy content in the metal oxide insulating layer 13 can be achieved by adjusting the laser irradiation intensity. In the actual process, the corresponding laser intensity can be set according to the actual application condition so as to realize the regulation and control of the oxygen vacancy content.
B14: an oxide semiconductor layer 14, a source-drain metal layer 15, a first passivation layer 16, an organic insulating layer 17, a common electrode 18, a second passivation layer 19, and a pixel electrode 20 are sequentially formed on the metal oxide insulating layer 13 on the side away from the gate insulating layer 12. The source-drain metal layer 15 includes a source 151 and a drain 152. The second passivation layer 19 has a contact hole 10A formed therein, and the contact hole 10A sequentially penetrates through the second passivation layer 19, the organic insulating layer 17, and the first passivation layer 16 and exposes the drain electrode 152. The pixel electrode 20 is connected to the drain electrode 152 in the contact hole 10A.
Wherein the oxide semiconductor layer 14 is formed using a physical vapor deposition process. The material of the oxide semiconductor layer 14 may include one or more of IGZO, IZO, IGZTO, IGTO, and IZTO.
Since the metal oxide insulating layer 13 has a high oxygen vacancy content, the number of oxygen vacancies at the contact interface between the oxide semiconductor layer 14 and the metal oxide insulating layer 13 increases after the formation of the oxide semiconductor layer 14, and the on-state current and mobility of the TFT can be improved after the formation of the TFT.
In this embodiment, the gate insulating layer 12 and the metal oxide insulating layer 13 are provided between the gate electrode 111 and the oxide semiconductor layer 14; in some embodiments, only the metal oxide insulating layer 13 may be disposed between the gate electrode 111 and the oxide semiconductor layer 14, in which case, the gate insulating layer 12 may be omitted, and thus, one process may be omitted, which is beneficial to saving process cost.
A source-drain metal layer 15 is formed on the oxide semiconductor layer 14 by a physical vapor deposition process, and the source-drain metal layer 15 is patterned to form a source 151 and a drain 152. Specifically, the material of the source drain metal layer 15 may include one or more of copper, aluminum, molybdenum, and titanium.
It should be noted that, in this embodiment, while the source 151 and the drain 152 are formed, a connection pad 153 may also be formed, and the connection pad 153 is used for realizing conduction between signals in different layers, for example, in this embodiment, the connection pad 153 may be used for communicating the signal trace 112 and the signal electrode 21, where the signal electrode 21 and the pixel electrode 20 are disposed in the same layer and used for transmitting a voltage to the signal trace 112.
Wherein, the first passivation layer 16 and the second passivation layer 19 can be formed by using a chemical vapor deposition process. The first passivation layer 16 and the second passivation layer 19 are the same material and may each include one or more of silicon oxide, silicon nitride, and silicon oxynitride.
The organic insulating layer 17 may be formed by coating. The material of the organic insulating layer 17 may be a resin-based transparent insulating material.
The common electrode 18 and the pixel electrode 20 may be formed using a physical vapor deposition process and patterned. The common electrode 18 and the pixel electrode 20 are made of the same material and may each include indium tin oxide.
Note that, a first via (not shown) and a second via (not shown) are also formed in the array substrate 100. The first via hole sequentially penetrates through the metal oxide insulating layer 13 and the gate insulating layer 12 and exposes the signal trace 112. The second via hole sequentially penetrates through the second passivation layer 19, the organic insulating layer 17, and the first passivation layer 16 and exposes the connection pad 153. The signal electrode 21 is connected to the signal trace 112 through a connection pad 153.
Referring to fig. 4 and 5 together, the second embodiment of the present invention provides a method for manufacturing an array substrate 100 with a top gate structure, which includes the following steps:
b21: a substrate 10 is provided.
The substrate 10 may be a hard substrate, such as a glass substrate; alternatively, the substrate 10 may also be a flexible substrate, such as a polyimide substrate, and the material of the substrate 10 is not particularly limited in this application.
B22: a light-shielding layer 22, a buffer layer 23, an oxide semiconductor layer 14, and a metal oxide insulating layer 13 are sequentially formed on one side of the substrate 10.
First, the light shielding layer 22 is formed using a physical vapor deposition process. The material of the light shielding layer 22 may include one or more of copper, aluminum, molybdenum, and titanium.
Next, a buffer layer 23 is formed on the side of the light-shielding layer 22 away from the substrate 10 by using a chemical vapor deposition process. The material of the buffer layer 23 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.
Next, the oxide semiconductor layer 14 is formed on the side of the buffer layer 23 away from the light-shielding layer 22 using a physical vapor deposition process. The material of the oxide semiconductor layer 14 may include one or more of IGZO, IZO, IGZTO, IGTO, and IZTO.
Finally, the metal oxide insulating layer 13 is formed on the side of the oxide semiconductor layer 14 away from the buffer layer 23 by using a physical vapor deposition process. The thickness of the metal oxide insulating layer 13 is 20nm to 50nm, such as 20nm, 25nm, 30nm, 35nm, 40nm, 45nm or 50 nm. Within the above thickness range, the uniformity of the distribution of oxygen vacancies in the metal oxide insulating layer 13 after the subsequent laser irradiation can be improved.
Specifically, the material of the metal oxide insulating layer 13 may include Ta2O5、ZrO2、HfO2、TiO2、Al2O3、SrO2And La2O3One or more of (a). Since the metal oxides have high dielectric constants, the metal oxide insulating layer 13 has good dielectric properties when the above materials are used.
B23: the metal oxide insulating layer 13 is irradiated with laser light.
After the metal oxide insulating layer 13 is formed, the metal oxide insulating layer 13 is subjected to laser irradiation by the femtosecond laser technique, and the content of oxygen vacancies in the metal oxide insulating layer 13 can be controlled by controlling the laser intensity and the laser irradiation time in the laser irradiation.
In the present embodiment, the material of the metal oxide insulating layer 13 may be Ta2O5. Due to Ta2O5Can effectively reduce the driving voltage and power consumption of the device, thereby utilizing laser to drive Ta2O5The generated local heat effect and the excellent processing speed of the laser can realize the Ta2O5Precise control of performance. Particularly, Ta can be effectively regulated and controlled by selecting lasers with different wavelengths2O5The content of oxygen vacancy in the film, and further the carrier concentration is adjusted.
In the present embodiment, the laser intensity in laser irradiation is positively correlated with the oxygen vacancy content in the metal oxide insulating layer 13 at a constant laser irradiation time. Wherein, after the step of performing laser irradiation on the metal oxide insulating layer 13, the oxygen vacancy content in the metal oxide insulating layer 13 is more than 23%.
Specifically, when the material of the metal oxide insulating layer 13 is Ta2O5In this case, the metal oxide insulating layer 13 includes chemical bonds such as Ta — O and C ═ O and oxygen vacancies Vo under laser irradiation2+. Referring to Table 1, Table 1 shows the laser irradiation time, the laser irradiation time without laser irradiation, and the laser irradiation time with different laser intensities (the laser intensities are 263mJ/cm, respectively)2、309mJ/cm2And 358mJ/cm2) Ta-O content, C ═ O content, and oxygen vacancy Vo2+The content change condition is as follows:
TABLE 1
From the above table, it can be seen that:
1. the oxygen vacancy content in the metal oxide insulating layer 13 is significantly increased under laser irradiation compared to the case without laser irradiation. Specifically, the oxygen vacancy content was only 22.35% without laser irradiation, the oxygen vacancy content was significantly greater than 22.35% when laser irradiation was employed, and the laser irradiation intensity was 358mJ/cm2When the oxygen vacancy content is high, the oxygen vacancy content can reach 34.02 percent.
2. Under laser irradiation, as the laser intensity increases, the oxygen vacancy content in the metal oxide insulating layer 13 also increases.
Therefore, in the present embodiment, the metal oxide insulating layer 13 after the film formation is irradiated with the laser, and the intensity of the laser irradiation is increased, whereby the oxygen vacancy content in the metal oxide insulating layer 13 can be significantly increased, and the carrier concentration can be increased.
It should be noted that the present embodiment merely schematically illustrates the relationship between the laser irradiation intensity and the oxygen vacancy content in the metal oxide insulating layer 13, to prove that the adjustment of the oxygen vacancy content in the metal oxide insulating layer 13 can be achieved by adjusting the laser irradiation intensity. In the actual process, the corresponding laser intensity can be set according to the actual application condition so as to realize the regulation and control of the oxygen vacancy content.
B24: a gate insulating layer 12, a gate electrode 111, an interlayer dielectric layer 24, a source-drain metal layer 15, a passivation layer 25, and a pixel electrode 20 are sequentially formed on the side of the metal oxide insulating layer 13 away from the oxide semiconductor layer 14. The source-drain metal layer 15 includes a source electrode 151 and a drain electrode 152, a contact hole 10A is formed in the passivation layer 25, and the pixel electrode 20 is connected to the drain electrode 152 through the contact hole 10A.
The forming method and material of the film structure can refer to the prior art, and are not described herein again.
In this embodiment, the metal oxide insulating layer 13 and the gate insulating layer 12 are provided between the oxide semiconductor layer 14 and the gate electrode 111; in some embodiments, only the metal oxide insulating layer 13 may be disposed between the oxide semiconductor layer 14 and the gate electrode 111, in which case, the gate insulating layer 12 may be omitted, and thus, one process may be omitted, which is beneficial to saving process cost.
Referring to fig. 6, a first embodiment of the present application provides an array substrate 100. The array substrate 100 provided by the first embodiment includes a substrate 10, a gate electrode 111, a gate insulating layer 12, a metal oxide insulating layer 13, an oxide semiconductor layer 14, a source-drain metal layer 15, a first passivation layer 16, an organic insulating layer 17, a common electrode 18, a second passivation layer 19, and a pixel electrode 20.
Wherein the gate electrode 111 is disposed at one side of the substrate 10. The gate insulating layer 12 is disposed on a side of the gate electrode 111 away from the substrate 10. The metal oxide insulating layer 13 is disposed on a side of the gate insulating layer 12 away from the gate electrode 111. The oxide semiconductor layer 14 is provided on a side of the metal oxide insulating layer 13 away from the gate insulating layer 12. The source-drain metal layer 15 is provided on the side of the oxide semiconductor layer 14 away from the metal oxide insulating layer 13, and the source-drain metal layer 15 includes a source electrode 151 and a drain electrode 152. The first passivation layer 16 is disposed on a side of the source-drain metal layer 15 away from the oxide semiconductor layer 14. The organic insulating layer 17 is disposed on a side of the first passivation layer 16 away from the source-drain metal layer 15. The common electrode 18 is disposed on a side of the organic insulating layer 17 away from the first passivation layer 16. A second passivation layer 19 is disposed on the common electrode 18 on a side thereof remote from the organic insulating layer 17. The pixel electrode 20 is disposed on a side of the second passivation layer 19 remote from the common electrode 18. The array substrate 100 has a contact hole 10A. The contact hole 10A sequentially penetrates the second passivation layer 19, the organic insulating layer 17, and the first passivation layer 16 and exposes the drain electrode 152. The pixel electrode 20 is connected to the drain electrode 152 in the contact hole 10A.
In addition, the array substrate 100 further includes signal traces 112, connection pads 153 and signal electrodes 21. The signal trace 112 and the gate 111 are disposed at the same layer. The pad 153 is disposed at the same level as the source 151. The signal electrode 21 is disposed in the same layer as the pixel electrode 20. The signal electrode 21 is connected to the signal trace 112 through a connection pad 153.
It should be noted that the array substrate 100 in this embodiment can be manufactured by the method for manufacturing the array substrate 100 described in the first example, and the related manufacturing method can refer to the description of the first example, and is not described herein again.
Referring to fig. 7, a second embodiment of the present application provides an array substrate 100. The array substrate 100 provided by the second embodiment includes a substrate 10, a light shielding layer 22, a buffer layer 23, an oxide semiconductor layer 14, a metal oxide insulating layer 13, a gate insulating layer 12, a gate electrode 111, an interlayer dielectric layer 24, a source-drain metal layer 15, a passivation layer 25, and a pixel electrode 20.
Wherein the light-shielding layer 22 is disposed on one side of the substrate 10. The buffer layer 23 is disposed on a side of the light-shielding layer 22 away from the substrate 10. The oxide semiconductor layer 14 is provided on a side of the buffer layer 23 away from the light-shielding layer 22. The metal oxide insulating layer 13 is provided on a side of the oxide semiconductor layer 14 away from the buffer layer 23. The gate insulating layer 12 is provided on a side of the metal oxide insulating layer 13 away from the oxide semiconductor layer 14. The gate electrode 111 is disposed on a side of the gate insulating layer 12 away from the metal oxide insulating layer 13. An interlayer dielectric layer 24 is disposed on the side of the gate 111 remote from the gate insulating layer 12. The source-drain metal layer 15 is disposed on a side of the interlayer dielectric layer 24 away from the gate 111, and the source-drain metal layer 15 includes a source 151 and a drain 152. The passivation layer 25 is arranged on one side of the source-drain metal layer 15 far away from the interlayer dielectric layer 24, a contact hole 10A is formed in the passivation layer 25, and the drain electrode 152 is exposed out of the contact hole 10A. The pixel electrode 20 is disposed on a side of the passivation layer 25 away from the source-drain metal layer 15, and the pixel electrode 20 is connected to the drain electrode 152 in the contact hole 10A.
It should be noted that the array substrate 100 in this embodiment can be manufactured by the method for manufacturing the array substrate 100 described in the foregoing example two, and the related manufacturing method can refer to the description of the example two, and is not repeated herein.
The above detailed description is provided for the preparation method of the array substrate and the array substrate provided in the embodiments of the present application, and the principle and the implementation manner of the present application are explained in this document by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
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| JP2019053172A (en) * | 2017-09-14 | 2019-04-04 | 株式会社Ｊｏｌｅｄ | Display device |
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