CN114121634B - Ultra-fast flash memory floating gate TiN film manufacturing method - Google Patents
Ultra-fast flash memory floating gate TiN film manufacturing method Download PDFInfo
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- CN114121634B CN114121634B CN202111399653.8A CN202111399653A CN114121634B CN 114121634 B CN114121634 B CN 114121634B CN 202111399653 A CN202111399653 A CN 202111399653A CN 114121634 B CN114121634 B CN 114121634B
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 title claims abstract description 87
- 238000007667 floating Methods 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000010410 layer Substances 0.000 claims abstract description 65
- 238000005530 etching Methods 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000000151 deposition Methods 0.000 claims abstract description 24
- 230000008569 process Effects 0.000 claims abstract description 10
- 239000011241 protective layer Substances 0.000 claims abstract description 7
- 238000000206 photolithography Methods 0.000 claims abstract 2
- 238000002955 isolation Methods 0.000 claims description 17
- 238000000231 atomic layer deposition Methods 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims 5
- 238000005538 encapsulation Methods 0.000 claims 3
- 239000010408 film Substances 0.000 claims 3
- 238000001312 dry etching Methods 0.000 claims 2
- 230000008021 deposition Effects 0.000 claims 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 12
- 238000010586 diagram Methods 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 5
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
本发明公开了一种超快闪存储器浮栅TiN薄膜制作方法，包括：按现有技术完成前序工序，直至完成沟槽刻蚀；沉积TiN；沉积包裹层，包裹TiN；光刻定义保护区和非保护区，形成保护层保护保护区，露出非保护区；刻蚀去除非保护区的包裹层，露出非保护区的TiN；去除保护区的保护层；刻蚀去除非保护区的TiN；沉积包裹层，包裹保护区的TiN；刻蚀去除保护区顶部和沟槽底部的包裹层，形成包裹层侧壁；刻蚀去除保护区顶部和沟槽底部的TiN以及包裹层侧壁，保留沟槽侧壁的TiN。本发明能有效保留超快闪存储器sidewall浮栅TiN薄膜，提高器件性能和均一性。
The present invention discloses a method for manufacturing a TiN film for floating gate of an ultra-fast flash memory, comprising: completing the preceding process according to the prior art until the groove etching is completed; depositing TiN; depositing a wrapping layer to wrap the TiN; photolithography to define a protection area and a non-protection area, forming a protective layer to protect the protection area, and exposing the non-protection area; etching to remove the wrapping layer of the non-protection area, exposing the TiN of the non-protection area; removing the protective layer of the protection area; etching to remove the TiN of the non-protection area; depositing a wrapping layer to wrap the TiN of the protection area; etching to remove the wrapping layer at the top of the protection area and the bottom of the groove, forming a wrapping layer sidewall; etching to remove the TiN at the top of the protection area and the bottom of the groove and the wrapping layer sidewall, and retaining the TiN of the groove sidewall. The present invention can effectively retain the ultra-fast flash memory sidewall floating gate TiN film, and improve the device performance and uniformity.
Description
Technical Field
The invention relates to the field of integrated circuit manufacturing, in particular to a manufacturing method of a floating gate TiN film of an ultra-flash memory.
Background
Compared with the Nor flash of the third generation in the current industry, 38SF (ultra-flash memory of 38nm technology node) has the advantages of higher erasure efficiency, higher erasure durability, higher write efficiency, faster write speed, lower erasure voltage, lower power consumption, no read-write interference, simple manufacturing process, short test time, greatly reduced cost and the like, and the size of a memory unit is only half of SF 1.0. High speed, low power consumption, low voltage are just bright spots of 38SF technology. The novel ultra-flash memory 2.0 is a new generation of Nor flash write operation utilizing a horizontal electric field and a tip TiN erasing operation without voltage coupling, and can greatly improve erasing efficiency and reduce operation voltage. The growth and etching of each auxiliary layer of the ALD TiN floating gate process have extremely high requirements on uniformity and stability, and the TiN film is discontinuous due to easy agglomeration of TiN caused by a plurality of heat treatments in the process, thereby seriously affecting the product performance.
Disclosure of Invention
In the summary section, a series of simplified form concepts are introduced that are all prior art simplifications in the section, which are described in further detail in the detailed description section. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The invention aims to provide a manufacturing method of an ultra-flash memory floating gate TiN film, which can effectively reserve the ultra-flash memory side floating gate TiN film and improve the device performance and uniformity.
In order to solve the technical problems, the manufacturing method of the floating gate TiN film of the ultra-flash memory provided by the invention comprises the following steps:
s2, depositing an isolation layer;
S3, depositing TiN;
S4, depositing a wrapping layer to wrap the TiN;
s5, photoetching to define a protection area and a non-protection area, forming a protection layer to protect the protection area and exposing the non-protection area;
s6, etching to remove the wrapping layer of the non-protection area and exposing TiN of the non-protection area;
s7, removing the protective layer of the protective area;
s8, etching to remove TiN in the non-protection area;
s9, depositing a wrapping layer to wrap TiN in the protection area;
s10, etching to remove the wrapping layers at the top of the protection area and the bottom of the groove to form the side wall of the wrapping layer;
s11, etching to remove the TiN at the top of the protection area and the bottom of the groove and the side wall of the wrapping layer, and reserving the TiN on the side wall of the groove.
Optionally, the manufacturing method of the floating gate TiN film of the ultra-flash memory is further improved, and the wrapping layer is an oxide layer.
Optionally, the manufacturing method of the floating gate TiN film of the ultra-flash memory is further improved, and the oxide layer is formed by adopting a low-temperature atomic layer deposition process.
Optionally, the manufacturing method of the floating gate TiN film of the ultra-flash memory is further improved, the protection area is an active area, and the non-protection area is an isolation area.
Optionally, the manufacturing method of the floating gate TiN film of the ultra-flash memory is further improved, and the protective layer is photoresist.
Optionally, the manufacturing method of the floating gate TiN film of the ultra-flash memory is further improved, and the step S5 is implemented to remove the oxide layer by adopting dry isotropic etching.
Optionally, the method for manufacturing the floating gate TiN film of the ultra-flash memory is further improved, and the step S7 is implemented to remove the TiN in the non-protection area by dry-wet etching.
Optionally, the method for manufacturing the floating gate TiN film of the ultra-flash memory is further improved, step S9 is implemented, and the oxide layers at the top of the active region and the bottom of the trench are removed by dry anisotropic etching
Optionally, the method for manufacturing the floating gate TiN film of the ultra-flash memory is further improved, step S10 is implemented, and TiN at the top of the protection area and the bottom of the trench and the side wall of the oxide layer are removed by dry-wet etching.
After finishing the groove according to the prior art, depositing a wrapping layer to wrap the TiN on the surface of the wafer to avoid the TiN on the surface of the wafer, photoetching and defining a protection area and a non-protection area to form a shielding layer protection area, exposing the non-protection area, etching and removing the wrapping layer of the non-protection area to expose the TiN of the non-protection area, removing the shielding layer of the protection area, etching and removing the TiN of the non-protection area, depositing the wrapping layer to wrap the TiN on the protection area to avoid the stain generated by the TiN on the surface of the wafer, etching and removing the wrapping layers on the top of the protection area and the bottom of the groove to form a wrapping layer side wall, etching and removing the TiN on the top of the protection area and the bottom of the groove and the wrapping layer side wall to reserve the TiN on the side wall of the groove. The method is applied to 38SF write operation by using a horizontal electric field and tip TiN erasing operation without voltage coupling, so that the erasing efficiency is greatly improved and the operating voltage is greatly reduced. The invention can increase the nested window of EG to FG and has better tip control and better Endurance performance. The cell area is only 60% of the same generation SF, the embedded additional mask number is only half of SF, and the embedded additional mask number can be reduced to <20nm. Can cover the capacity of 4 Mb-4 Gb, and has NOR and NOVRAM functions (Internet of things, AI, automobile electronics, etc.). The invention can effectively reserve the floating gate TiN film of the ultra-flash memory side, and improve the performance and uniformity of the device.
Drawings
The accompanying drawings are intended to illustrate the general features of methods, structures and/or materials used in accordance with certain exemplary embodiments of the invention, and supplement the description in this specification. The drawings of the present invention, however, are schematic illustrations that are not to scale and, thus, may not be able to accurately reflect the precise structural or performance characteristics of any given embodiment, the present invention should not be construed as limiting or restricting the scope of the numerical values or attributes encompassed by the exemplary embodiments according to the present invention. The invention is described in further detail below with reference to the attached drawings and detailed description:
fig. 1 is a schematic diagram of an intermediate structure of the present invention.
Fig. 2 is a schematic diagram of an intermediate structure of the present invention.
Fig. 3 is a schematic diagram of an intermediate structure of the present invention.
Fig. 4 is a schematic diagram of an intermediate structure of the present invention.
Fig. 5 is a schematic diagram of an intermediate structure of the present invention.
Fig. 6 is a schematic diagram of an intermediate structure of the present invention.
Detailed Description
Other advantages and technical effects of the present invention will become more fully apparent to those skilled in the art from the following disclosure, which is a detailed description of the present invention given by way of specific examples. The invention may be practiced or carried out in different embodiments, and details in this description may be applied from different points of view, without departing from the general inventive concept. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It should be appreciated that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technical solution of these exemplary embodiments to those skilled in the art.
A first embodiment;
the invention provides a manufacturing method of a floating gate TiN film of an ultra-flash memory, which comprises the following steps:
s1, completing the preamble procedure according to the prior art until the groove etching is completed;
s2, depositing an isolation layer;
S3, depositing TiN;
S4, depositing a wrapping layer to wrap the TiN;
s5, photoetching to define a protection area and a non-protection area, forming a protection layer to protect the protection area and exposing the non-protection area;
s6, etching to remove the wrapping layer of the non-protection area and exposing TiN of the non-protection area;
s7, removing the protective layer of the protective area;
s8, etching to remove TiN in the non-protection area;
s9, depositing a wrapping layer to wrap TiN in the protection area;
s10, etching to remove the wrapping layers at the top of the protection area and the bottom of the groove to form the side wall of the wrapping layer;
s11, etching to remove the TiN at the top of the protection area and the bottom of the groove and the side wall of the wrapping layer, and reserving the TiN on the side wall of the groove.
A second embodiment;
the invention provides a manufacturing method of a floating gate TiN film of an ultra-flash memory, which comprises the following steps:
s1, completing the preamble procedure according to the prior art until the groove etching is completed;
s2, depositing an isolation layer;
S3, depositing TiN;
s4, depositing an oxide layer by adopting a low-temperature atomic layer deposition process, and wrapping TiN;
S5, photoetching to define an active region and an isolation region, and shielding the active region by photoresist to expose the isolation region;
s6, etching to remove the oxide layer of the isolation region and exposing TiN of the isolation region;
S7, removing the photoresist of the active region;
s8, etching to remove TiN in the isolation region;
s9, depositing an oxide layer by adopting a low-temperature atomic layer deposition process, and wrapping TiN of the active region;
s10, etching to remove the oxide layers at the top of the active region and the bottom of the groove to form oxide layer side walls;
s11, etching to remove the TiN at the top of the protection area and the bottom of the groove and the side wall of the oxide layer, and reserving the TiN on the side wall of the groove.
Illustratively, hafnium oxide may be selected for use as the oxide layer.
Like reference numerals refer to like elements throughout the several views. Furthermore, it will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, parameters, components, regions, layers and/or sections, these elements, parameters, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, parameter, component, region, layer or section from another element, parameter, component, region, layer or section. Thus, a first element, parameter, component, region, layer or section discussed below could be termed a second element, parameter, component, region, layer or section without departing from the teachings of the example embodiments of the present invention.
A third embodiment;
the invention provides a manufacturing method of a floating gate TiN film of an ultra-flash memory, which comprises the following steps:
s1, completing the preamble procedure according to the prior art until the groove etching is completed;
s2, depositing an isolation layer;
s3, turning to an HK FOUP, and depositing TiN;
S4, depositing hafnium dioxide by adopting a low-temperature atomic layer deposition process, wrapping TiN, and transferring optional back of wafer cleaning to HL FOU and then executing the subsequent step S4;
S5, photoetching to define an active region and an isolation region, and shielding the active region by photoresist to expose the isolation region, wherein the isolation region is shown in figure 2;
s6, turning to an HK FOUP, removing hafnium dioxide in the isolation region by adopting dry isotropic etching, and exposing TiN in the isolation region;
s7, removing the photoresist of the active region, as shown in FIG. 3;
S8, etching to remove TiN in the isolation region, as shown in FIG. 4;
s9, depositing hafnium dioxide by adopting a low-temperature atomic layer deposition process, and wrapping TiN of the active region;
s10, removing hafnium dioxide at the top of the active region and at the bottom of the groove by adopting dry anisotropic etching to form a hafnium dioxide side wall, as shown in FIG. 5;
S11, removing the TiN at the top of the protection area and the bottom of the groove and the side wall of hafnium dioxide by adopting a dry-wet method, and reserving the TiN at the side wall of the groove, as shown in figure 6.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present invention has been described in detail by way of specific embodiments and examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (8)
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569182A (en) * | 2012-03-01 | 2012-07-11 | 上海宏力半导体制造有限公司 | Contact hole and manufacturing method thereof as well as semiconductor device |
| CN104900593A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Memory and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102237365B (en) * | 2010-04-28 | 2013-01-02 | 中国科学院微电子研究所 | Flash memory device and manufacturing method thereof |
| CN106206445B (en) * | 2015-04-29 | 2019-07-30 | 中芯国际集成电路制造(上海)有限公司 | The forming method of memory construction |
| CN108695332B (en) * | 2018-05-18 | 2021-05-07 | 上海华虹宏力半导体制造有限公司 | Split-gate flash memory and forming method and control method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569182A (en) * | 2012-03-01 | 2012-07-11 | 上海宏力半导体制造有限公司 | Contact hole and manufacturing method thereof as well as semiconductor device |
| CN104900593A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Memory and forming method thereof |
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