CN114121634A - Method for manufacturing floating gate TiN film of ultra-flash memory - Google Patents
Method for manufacturing floating gate TiN film of ultra-flash memory Download PDFInfo
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- CN114121634A CN114121634A CN202111399653.8A CN202111399653A CN114121634A CN 114121634 A CN114121634 A CN 114121634A CN 202111399653 A CN202111399653 A CN 202111399653A CN 114121634 A CN114121634 A CN 114121634A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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Abstract
本发明公开了一种超快闪存储器浮栅TiN薄膜制作方法，包括：按现有技术完成前序工序，直至完成沟槽刻蚀；沉积TiN；沉积包裹层，包裹TiN；光刻定义保护区和非保护区，形成保护层保护保护区，露出非保护区；刻蚀去除非保护区的包裹层，露出非保护区的TiN；去除保护区的保护层；刻蚀去除非保护区的TiN；沉积包裹层，包裹保护区的TiN；刻蚀去除保护区顶部和沟槽底部的包裹层，形成包裹层侧壁；刻蚀去除保护区顶部和沟槽底部的TiN以及包裹层侧壁，保留沟槽侧壁的TiN。本发明能有效保留超快闪存储器sidewall浮栅TiN薄膜，提高器件性能和均一性。
The invention discloses a method for manufacturing a floating gate TiN thin film of an ultra-flash memory, which includes: completing the pre-sequence procedures according to the prior art until the trench etching is completed; depositing TiN; depositing a wrapping layer to wrap the TiN; defining a protection zone by photolithography And the non-protected area, form a protective layer to protect the protected area and expose the non-protected area; etch to remove the wrapping layer of the non-protected area to expose the non-protected TiN; remove the protective layer of the protected area; etch to remove the non-protected TiN; Deposit a wrapping layer to wrap the TiN of the protected area; etch and remove the wrapping layer on the top of the protected area and the bottom of the trench to form the sidewall of the wrapping layer; etch and remove the TiN at the top of the protected area and the bottom of the trench and the sidewall of the wrapping layer, leaving the trench TiN on the sidewall of the groove. The invention can effectively retain the sidewall floating gate TiN thin film of the ultra-flash memory, and improve the performance and uniformity of the device.
Description
Technical Field
The invention relates to the field of integrated circuit manufacturing, in particular to a method for manufacturing a floating gate TiN film of a super-flash memory.
Background
Compared with the norflash in the third generation in the industry at present, 38SF (38nm technology node ultra-flash memory) has the advantages of higher erasing efficiency, higher erasing durability, higher writing efficiency, higher writing speed, lower erasing voltage, lower power consumption, no read-write interference, simple process, short test time, greatly reduced cost and the like, and the size of a memory cell is only half of that of SF 1.0. High speed, low power consumption, low voltage are just the bright spots of 38SF technology. The novel ultra-flash memory 2.0 is a new generation of Nor flash memory, and can greatly improve the erasing efficiency and reduce the operating voltage by utilizing the writing operation of a horizontal electric field and the erasing operation without voltage coupling of the TiN at the tip. The growth and etching of each attached layer of the ALD TiN floating gate process have extremely high requirements on uniformity and stability, and TiN is easy to agglomerate due to the fact that a plurality of heat treatments are used in the process, so that the discontinuity of a TiN film is caused, and the product performance is seriously influenced.
Disclosure of Invention
In this summary, a series of simplified form concepts are introduced that are simplifications of the prior art in this field, which will be described in further detail in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The invention aims to provide a method for manufacturing a floating gate TiN film of a super-flash memory, which can effectively reserve the TiN film of the super-flash memory side wall floating gate and improve the performance and the uniformity of a device.
In order to solve the technical problem, the method for manufacturing the floating gate TiN film of the ultra-flash memory provided by the invention comprises the following steps:
s2, depositing an isolating layer;
s3, depositing TiN;
s4, depositing a wrapping layer and wrapping TiN;
s5, defining a protection area and a non-protection area by photoetching, forming a protection layer protection area and exposing the non-protection area;
s6, etching to remove the wrapping layer of the non-protection area and expose TiN of the non-protection area;
s7, removing the protective layer of the protective area;
s8, etching to remove TiN in the non-protection area;
s9, depositing a wrapping layer and wrapping TiN in the protection area;
s10, etching to remove the wrapping layers at the top of the protection area and the bottom of the groove to form the side wall of the wrapping layer;
and S11, etching to remove TiN at the top of the protective region and the bottom of the groove and the side wall of the wrapping layer, and reserving TiN at the side wall of the groove.
Optionally, the fabrication method of the ultra-flash memory floating gate TiN film is further improved, and the wrapping layer is an oxide layer.
Optionally, the method for manufacturing the ultra-flash memory floating gate TiN film is further improved, and the oxide layer is formed by adopting a low-temperature atomic layer deposition process.
Optionally, the method for manufacturing the floating gate TiN film of the ultra-flash memory is further improved, the protective region is an active region, and the non-protective region is an isolation region.
Optionally, the method for manufacturing the ultra-flash memory floating gate TiN film is further improved, and the protective layer is photoresist.
Optionally, the method for manufacturing the ultra-flash memory floating gate TiN film is further improved, and step S5 is implemented to remove the oxide layer by dry isotropic etching.
Optionally, the method for manufacturing the ultra-flash memory floating gate TiN film is further improved, and step S7 is implemented to remove TiN in the non-protection region by dry and wet etching.
Optionally, the method for fabricating the floating gate TiN film of the ultra-flash memory is further improved, and step S9 is implemented, wherein dry anisotropic etching is used to remove the oxide layer on the top of the active region and the bottom of the trench
Optionally, the method for manufacturing the ultra-flash memory floating gate TiN film is further improved, and step S10 is implemented, and TiN and the sidewalls of the oxide layer at the top of the protection region and the bottom of the trench are removed by dry and wet etching.
After finishing the preorder process according to the prior art and finishing the groove, depositing a wrapping layer to wrap TiN to avoid TiN on the surface of the wafer, defining a protective area and a non-protective area by photoetching, forming a protective area protected by a shielding layer, exposing the non-protective area, etching to remove the wrapping layer of the non-protective area, and exposing the TiN of the non-protective area; removing the shielding layer of the protection area; etching to remove TiN in the non-protection area; depositing a wrapping layer to wrap TiN in the protection area, so that the TiN on the surface of the wafer is prevented from being exposed to generate dirt; etching to remove the wrapping layers at the top of the protection area and the bottom of the groove to form a side wall of the wrapping layer; and etching to remove the TiN at the top of the protective area and the bottom of the groove and the side wall of the wrapping layer, and reserving the TiN on the side wall of the groove. The method is applied to 38SF writing operation by utilizing a horizontal electric field and tip TiN erasing operation without voltage coupling, so that the erasing efficiency is greatly improved and the operating voltage is reduced. The invention can increase the nesting window of EG on FG and better control the tip, and the Endurance performance is better. The cell area is only 60% of the SF of the same generation, the embedded newly-added mask number is only half of the SF, and the cell area can be reduced to less than 20 nm. Can cover 4 Mb-4 Gb capacity, and has NOR and NOVRAM functions (Internet of things, AI, automobile electronics, etc.). The method can effectively reserve the floating gate TiN film of the ultra-flash memory sidewall, and improve the performance and the uniformity of the device.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention, are incorporated in and constitute a part of this specification. The drawings are not necessarily to scale, however, and may not be intended to accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the scope of values or properties encompassed by exemplary embodiments in accordance with the invention. The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
FIG. 1 is a first schematic diagram of the present invention.
FIG. 2 is a second schematic diagram of the present invention.
FIG. 3 is a third schematic diagram of the present invention.
FIG. 4 is a fourth schematic diagram of the intermediate structure of the present invention.
FIG. 5 is a fifth schematic diagram of the present invention.
Fig. 6 is a sixth schematic diagram of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and technical effects of the present invention will be fully apparent to those skilled in the art from the disclosure in the specification. The invention is capable of other embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the general spirit of the invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technical solutions of these exemplary embodiments to those skilled in the art.
A first embodiment;
the invention provides a method for manufacturing a floating gate TiN film of a super-flash memory, which comprises the following steps:
s1, completing the preorder procedure according to the prior art until the groove etching is completed;
s2, depositing an isolating layer;
s3, depositing TiN;
s4, depositing a wrapping layer and wrapping TiN;
s5, defining a protection area and a non-protection area by photoetching, forming a protection layer protection area and exposing the non-protection area;
s6, etching to remove the wrapping layer of the non-protection area and expose TiN of the non-protection area;
s7, removing the protective layer of the protective area;
s8, etching to remove TiN in the non-protection area;
s9, depositing a wrapping layer and wrapping TiN in the protection area;
s10, etching to remove the wrapping layers at the top of the protection area and the bottom of the groove to form the side wall of the wrapping layer;
and S11, etching to remove TiN at the top of the protective region and the bottom of the groove and the side wall of the wrapping layer, and reserving TiN at the side wall of the groove.
A second embodiment;
the invention provides a method for manufacturing a floating gate TiN film of a super-flash memory, which comprises the following steps:
s1, completing the preorder procedure according to the prior art until the groove etching is completed;
s2, depositing an isolating layer;
s3, depositing TiN;
s4, depositing an oxide layer by adopting a low-temperature atomic layer deposition process, and wrapping TiN;
s5, defining an active region and an isolation region by photoetching, and protecting the active region by photoresist shielding to expose the isolation region;
s6, etching to remove the oxide layer of the isolation region and expose TiN of the isolation region;
s7, removing the photoresist in the active region;
s8, etching to remove TiN in the isolation region;
s9, depositing an oxide layer by adopting a low-temperature atomic layer deposition process, and wrapping TiN of the active region;
s10, etching to remove the oxide layer on the top of the active area and the bottom of the groove to form the side wall of the oxide layer;
and S11, etching to remove TiN at the top of the protective region and the bottom of the trench and the side wall of the oxide layer, and reserving TiN at the side wall of the trench.
For example, hafnium oxide may be used as the oxide layer.
Like reference numerals refer to like elements throughout the drawings. Further, it will be understood that, although the terms first, second, etc. may be used herein to describe various elements, parameters, components, regions, layers and/or sections, these elements, parameters, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, parameter, component, region, layer or section from another element, parameter, component, region, layer or section. Thus, a first element, parameter, component, region, layer or section discussed below could be termed a second element, parameter, component, region, layer or section without departing from the teachings of exemplary embodiments according to the present invention.
A third embodiment;
the invention provides a method for manufacturing a floating gate TiN film of a super-flash memory, which comprises the following steps:
s1, completing the preorder procedure according to the prior art until the groove etching is completed;
s2, depositing an isolating layer;
s3, transferring to HK FOUP to deposit TiN;
s4, depositing hafnium oxide by adopting a low-temperature atomic layer deposition process, and wrapping TiN, as shown in figure 1; optional back of wafer cleaning is transferred to HL FOU and the subsequent step S4 is executed;
s5, defining an active region and an isolation region by photolithography, and exposing the isolation region by masking the active region with photoresist, as shown in fig. 2;
s6, turning to HK FOUP, and removing hafnium oxide in the isolation region by adopting dry isotropic etching to expose TiN in the isolation region;
s7, removing the photoresist in the active region, as shown in fig. 3;
s8, etching to remove TiN in the isolation region, as shown in figure 4;
s9, depositing hafnium oxide by adopting a low-temperature atomic layer deposition process, and wrapping TiN of the active region;
s10, removing hafnium oxide on the top of the active region and the bottom of the trench by adopting dry anisotropic etching to form a hafnium oxide side wall, as shown in FIG. 5;
and S11, removing TiN and hafnium oxide side walls at the top of the protection region and the bottom of the trench by adopting dry and wet etching, and reserving TiN at the side walls of the trench, as shown in figure 6.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (9)
1. A floating gate groove side wall TiN film manufacturing method is used for an ultra-flash memory and is characterized by comprising the following steps:
s1, completing the preorder procedure according to the prior art until the groove etching is completed;
s2, depositing an isolating layer;
s3, depositing TiN;
s4, depositing a wrapping layer and wrapping TiN;
s5, defining a protection area and a non-protection area by photoetching, forming a protection layer protection area and exposing the non-protection area;
s6, etching to remove the wrapping layer of the non-protection area and expose TiN of the non-protection area;
s7, removing the protective layer of the protective area;
s8, etching to remove TiN in the non-protection area;
s9, depositing a wrapping layer and wrapping TiN in the protection area;
s10, etching to remove the wrapping layers at the top of the protection area and the bottom of the groove to form the side wall of the wrapping layer;
and S11, etching to remove TiN at the top of the protective region and the bottom of the groove and the side wall of the wrapping layer, and reserving TiN at the side wall of the groove.
2. The method for fabricating floating gate TiN film of ultra-flash memory according to claim 1, wherein: the wrapping layer is an oxide layer.
3. The method for fabricating floating gate TiN film of ultra-flash memory according to claim 2, wherein: the oxide layer is formed by a low-temperature atomic layer deposition process.
4. The method for fabricating floating gate TiN film of ultra-flash memory according to claim 1, wherein: the protective region is an active region and the non-protective region is an isolation region.
5. The method for fabricating floating gate TiN film of ultra-flash memory according to claim 1, wherein: the protective layer is photoresist.
6. The method for fabricating floating gate TiN film of ultra-flash memory according to claim 1, wherein: step S6 is performed to remove the oxide layer using dry isotropic etching.
7. The method for fabricating floating gate TiN film of ultra-flash memory according to claim 1, wherein: step S8 is performed to remove TiN in the non-protection region by dry and wet etching.
8. The method for fabricating floating gate TiN film of ultra-flash memory according to claim 1, wherein: and step 10 is implemented, and dry anisotropic etching is adopted to remove the oxide layers at the top of the active region and the bottom of the trench.
9. The method for fabricating floating gate TiN film of ultra-flash memory according to claim 1, wherein: and step S11 is implemented, and the TiN and the side wall of the oxide layer at the top of the protection area and the bottom of the groove are removed by adopting dry-wet etching.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120018791A1 (en) * | 2010-04-28 | 2012-01-26 | Institute of Microelectronics, Chinese Academy of Sciences | Flash memory device and manufacturing method of the same |
| CN102569182A (en) * | 2012-03-01 | 2012-07-11 | 上海宏力半导体制造有限公司 | Contact hole and manufacturing method thereof as well as semiconductor device |
| CN104900593A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Memory and forming method thereof |
| CN106206445A (en) * | 2015-04-29 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of memory construction |
| CN108695332A (en) * | 2018-05-18 | 2018-10-23 | 上海华虹宏力半导体制造有限公司 | Gate-division type flash memory and forming method thereof, control method |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120018791A1 (en) * | 2010-04-28 | 2012-01-26 | Institute of Microelectronics, Chinese Academy of Sciences | Flash memory device and manufacturing method of the same |
| CN102569182A (en) * | 2012-03-01 | 2012-07-11 | 上海宏力半导体制造有限公司 | Contact hole and manufacturing method thereof as well as semiconductor device |
| CN104900593A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Memory and forming method thereof |
| CN106206445A (en) * | 2015-04-29 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of memory construction |
| CN108695332A (en) * | 2018-05-18 | 2018-10-23 | 上海华虹宏力半导体制造有限公司 | Gate-division type flash memory and forming method thereof, control method |
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