CN114121612B - A kind of FDSOI silicon epitaxial growth process optimization method - Google Patents

Abstract

The invention discloses an FDSOI silicon epitaxial growth process optimization method, which can ensure that the top layer silicon above the active region can be grown completely. The transistor includes a substrate on which an active region, a trench isolation region and a gate region are distributed. The substrate is divided into several substrate regions, a trench isolation region is arranged between two adjacent substrate regions, and epitaxial layers are grown respectively on the top silicon of different substrate regions. A first layer of top layer silicon is deposited over the active region of the bottom region, a thin film is deposited on the upper surface of the first layer of top layer silicon, the gate region, and the trench isolation region, a mask is arranged over the thin film, and the top of the corresponding substrate region is etched etch the film above the corresponding substrate area, further clean with pre-cleaning technology, dry the first layer of top silicon, and deposit a second layer of top silicon on the surface of the first layer of top silicon to form a combined top silicon , so that the combined top layer silicon grows out of the epitaxial layer.

Description

A kind of FDSOI silicon epitaxial growth process optimization method

technical field

The invention relates to the technical field of transistor processing, in particular to an FDSOI silicon epitaxial growth process optimization method.

Background technique

Field effect transistor is a voltage-controlled semiconductor device, mainly including planar field effect transistor (MOSFET), fin field effect transistor (FinFET, released in 1999) and SOI-based ultra-thin silicon-on-insulator transistor (FDSOI, 2000 Published), when the gate length approaches 20 nanometers, the current control capability drops sharply, and the leakage rate increases accordingly, which is no longer applicable in the traditional planar MOSFET structure. The FinFET structure and the FDSOI structure can meet the gate length reduction, while ensuring the gate voltage to the source and drain current control capability requirements.

At present, the gate length of FDSOI planar transistors can be reduced to less than 14 nanometers. A large number of early electrical simulation results show that in this structure, in order to reduce the degree of transistor leakage induced barrier lowering (DIBL), it is necessary to reduce the FDSOI at the same time. The buried dielectric layer thickness of the substrate (i.e. the BOX thickness) and the top layer silicon thickness. However, a reduction in the thickness of the top layer silicon will have a greater impact on the silicon epitaxial growth. In the FDSOI fabrication process, the initial surface silicon of the FDSOI wafer is only about 10nm to 6nm, and several processes before the epitaxial layer epitaxy, including oxidation, etching, cleaning, etc., will cause a certain amount of silicon loss. Silicon loss leads to active The silicon above the area (ie AA) may not be able to meet the epitaxial growth, resulting in the inability or incomplete growth of the epitaxial layer. This defect will be detrimental to the connection between the subsequent silicide and the contact layer. If the silicon loss is serious, it may even lead to the contact layer. Erosion through and other problems, which will directly affect the improvement of FDSOI device performance.

SUMMARY OF THE INVENTION

In view of the problems in the prior art that the top silicon of the FDSOI transistor is blocked or oxidized, cleaned and other processes are prone to excessive loss of the top silicon, resulting in the inability of epitaxial growth or poor epitaxial growth effect of the top silicon above the active region, the present invention provides An FDSOI silicon epitaxial growth process optimization method is proposed, which can improve the epitaxial growth effect, reduce the excessive loss of the top silicon above the active region and the trench isolation region, and can make the top silicon have sufficient thickness to ensure the active region. The top layer of silicon can grow intact.

To achieve the above object, the present invention adopts the following technical solutions:

An FDSOI silicon epitaxial growth process optimization method, the FDSOI transistor includes a substrate, and an active region, a trench isolation region, and a gate region are distributed on the substrate, and the active region includes a source and drain region. The doping substances and concentrations are different, and the substrate is divided into several substrate regions; it is characterized in that,

An epitaxial layer is grown on the top silicon of different substrate regions respectively, and the process optimization steps before the growth of the epitaxial layer include: K1, sequentially depositing a first layer of top silicon over the active regions of the different substrate regions, and in depositing a thin film on the upper surface of each of the substrate regions;

K2, arranging a mask over the thin film, the mask comprising an anti-reflection layer and a photoresist layer deposited in sequence;

K3, etching the mask above the corresponding substrate region;

K4. Etch the thin film above the corresponding substrate region. The thin film etching method is as follows: using hydrofluoric acid solution (DHF), phosphoric acid solution (H ₃ PO ₄ ), and ammonium hydroxide solution (SC ₁ ), hydrogen chloride solution (SC ₂ ) for cleaning;

K5. Use pre-cleaning technology for further cleaning;

K6, drying the first layer of top silicon;

K7, depositing a second layer of top silicon and a third layer of top silicon on the surface of the first layer of top silicon in sequence, the first layer of top silicon, the second layer of top silicon and the third layer of top silicon are combined to form Combined top layer silicon;

K8, using an epitaxial growth method to grow an epitaxial layer from the combined top layer silicon.

It is further characterized in that,

Further, in step K1, the HCD silicon nitride deposition process is used to realize the thin film deposition, the thin film includes silicon nitride, and the thickness of the silicon nitride is 135A;

Further, the step of removing the mask includes: first, placing the substrate processed in step K2 in an etching machine to perform a degumming process, and removing the photoresist layer above the corresponding substrate area. (photoresist layer) removal;

The anti-reflection layer corresponding to the substrate region is removed by wet cleaning.

Further, the cleaning solution of described wet cleaning comprises SPM solution, and described SPM solution comprises: the sulfuric acid that concentration is 98% and the hydrogen peroxide that concentration is 30%, the ratio of sulfuric acid and hydrogen peroxide is 5:1, adopts wet cleaning to carry out The cleaning temperature during cleaning was 125°C.

Further, in step K4, the thin film etching step includes: K41, using the hydrofluoric acid solution (DHF) to remove the mask polymer; K42, using a phosphoric acid solution (H ₃ PO ₄ ) to clean the thin film , K43, was further cleaned with ammonium hydroxide solution (SC ₁ ) to remove the residual thin film polymer, and the cleaning temperature was 50 °C; K44, was cleaned again with hydrogen chloride solution (SC ₂ ), and the residual thin film polymer was completely removed, The cleaning temperature is 35℃;

Wherein, the ammonium hydroxide solution (SC ₁ ) is a mixed solution of ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ) and pure water (H ₂ O), and the ammonium hydroxide ( The mixing ratio of NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ) and pure water (H ₂ O) is 1:1.5:50; the hydrogen chloride solution (SC ₂ ) is a mixture of hydrogen chloride (HCL), hydrogen peroxide and pure water, The mixing ratio of hydrogen chloride, hydrogen peroxide and pure water in the hydrogen chloride solution is 1:1.5:50.

Further, in step K6, the deposition thickness of the top layer silicon of the second layer ranges from 3 nm to 5 nm.

Further, in step K7, the drying temperature is 650°C.

Further, in step K8, the epitaxial layer is silicon phosphorus and/or silicon germanium.

Further, the substrate region includes a first substrate, a second substrate... an Nth substrate, where N is an integer, the thin film includes a first thin film, and the mask includes a first mask , the epitaxial layer includes a first epitaxial layer grown on the first substrate, and the first epitaxial layer is grown on the first substrate by using the process optimization steps K1 to K8.

Further, the process optimization method for the growth of the first epitaxial layer includes: S1, covering the first top layer silicon on the upper surface of the active region of the first substrate region, and covering the upper surface of each of the substrate regions on the upper surface of each of the substrate regions uniformly depositing the first film;

S2, arranging a first mask over the first thin film in each of the substrate regions, where the first mask includes an anti-reflection layer and a photoresist layer deposited in sequence;

S3, etching the first mask above the first substrate;

S4. Etch the first thin film above the first substrate. The first thin film etching method is as follows: using hydrofluoric acid solution (ie DHF), phosphoric acid solution (ie H ₃ PO ₄ ), hydrogen Ammonium oxide solution (ie SC ₁ ), hydrogen chloride solution (ie SC ₂ ) for cleaning;

S5. Use pre-cleaning technology (ie SiCoNi technology) for further cleaning;

S6, drying the first layer top layer silicon after cleaning;

S7. Deposit a second layer of top silicon (about 2 nanometers) and a third layer of top silicon (about 2 The second layer of top silicon is combined with the third layer of top silicon to form a first combined top silicon;

S8, growing a first epitaxial layer from the first combined top layer silicon.

Further, the thin film includes a second thin film, the mask includes a second mask, and the process optimization method further includes: S9, growing a second epitaxy on the top silicon surface above the second substrate layer, step S9 includes: first removing the first mask, then depositing a second thin film on the top of the first epitaxial layer and on the remaining first thin film; and then performing the steps K2~ K8.

Further, the specific step of growing the second epitaxial layer from the top silicon above the second substrate includes: S91, depositing a second epitaxial layer over the first epitaxial layer and over the remaining first thin film. film;

S92, arranging a second mask on the surface of the second thin film, where the second mask includes an anti-reflection layer and a photoresist layer deposited in sequence;

S93, etching the second mask above the second substrate;

S94 , etching the second thin film above the second substrate, and the etching method of the second thin film is as follows: using hydrofluoric acid solution (DHF), phosphoric acid solution (H ₃ PO ₄ ), hydrogen The second thin film is cleaned with an ammonium oxide solution (SC ₁ ) and a hydrogen chloride solution (SC ₂ ), and the second thin film above the second substrate is removed;

S95, further cleaning the substrate by using a pre-cleaning technology;

S96, sequentially depositing a second layer of top layer silicon and a third layer of top layer silicon on the surface of the first layer of top layer silicon above the second substrate, and the first layer of top layer silicon and the second layer of silicon above the second substrate the top layer silicon is combined with the third layer top layer silicon to form a second combined top layer silicon;

S97, using an epitaxial growth process to grow a second epitaxial layer from the second combined top layer silicon.

The above-mentioned structure of the present invention can achieve the following beneficial effects: In the method for optimizing the silicon epitaxial growth process of the present application, the substrate is divided into several substrate regions, and epitaxial layers are grown on the different substrate regions in sequence, and before the epitaxial layer is grown, sequentially The process before the growth of the epitaxial layer is carried out by arranging the mask, removing the mask above the corresponding substrate area, removing the film above the corresponding substrate area, pre-cleaning, deposition of the second layer of top silicon and the third layer of top silicon, etc. In order to optimize, in this optimization process, the film etching method is as follows: use hydrofluoric acid solution (DHF), phosphoric acid solution (H ₃ PO ₄ ), ammonium hydroxide solution (SC ₁ ), and hydrogen chloride solution (SC ₂ ) for cleaning in sequence , effectively remove the mask polymer, film, and film polymer in turn, avoiding the problem that the mask polymer, the film and the film polymer are blocked on the surface of the top layer silicon and affect the silicon epitaxial growth.

After the thin film and thin film polymer on the surface of the top silicon layer of the first layer are removed, the surface of the top silicon layer of the first layer is further cleaned by pre-cleaning technology, which further reduces the influence of the residual thin film or thin film polymer on the epitaxial growth of the top layer silicon; After pre-cleaning, a second layer of top silicon and a third layer of top silicon are deposited on the surface of the first layer of top silicon. The deposition of the second layer of top silicon and/or the third layer of top silicon not only compensates for the The loss of a layer of top silicon, and the increase in the thickness of the top silicon, ensures that there is a sufficient thickness of top silicon above the active region to meet the complete growth requirements of the epitaxial layer.

Description of drawings

Fig. 1 is the front view structure schematic diagram of the cross-section before epitaxial growth of the field effect transistor of the present invention;

Fig. 2 is the silicon epitaxial growth process flow chart above the P-type silicon substrate of the present invention;

3a is a schematic structural diagram of the first thin film deposited on the first substrate by adopting step S1 of the process optimization method of the present invention;

3b is a schematic structural diagram of implementing a mask etching above the first substrate in step S3 of the process optimization method of the present invention;

3c is a schematic structural diagram of implementing the etching of the first thin film above the first substrate in step S4 of the process optimization method of the present invention;

FIG. 3d is a schematic structural diagram of realizing the deposition of the first combined top layer silicon over the first substrate by adopting step S7 of the process optimization method of the present invention;

3e is a schematic structural diagram of growing a SiGe epitaxial layer above the first substrate by adopting step S8 of the process optimization method of the present invention;

4a is a schematic structural diagram of realizing the deposition of the second thin film above the second substrate by adopting step S91 of the process optimization method of the present invention;

4b is a schematic structural diagram of implementing the etching of the second thin film above the second substrate in step S94 of the process optimization method of the present invention;

FIG. 4c is a schematic structural diagram of realizing the growth of the silicon epitaxial layer above the second substrate by adopting step S97 of the process optimization method of the present invention.

Detailed ways

In order to make those skilled in the art better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only Embodiments are part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It should be noted that the terms "comprising" and "having" in the description and claims of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusion, for example, including a series of steps or units The processes, methods, apparatus, products or devices are not necessarily limited to those steps or units expressly listed, but may include other steps or units not expressly listed or inherent to such processes, methods, products or devices.

An FDSOI silicon epitaxial growth process optimization method, the FDSOI transistor includes a substrate 1, an active region 2, a trench isolation region 3, and a gate region 4 are distributed on the substrate 1, and the active region 2 includes a source and drain region. The doping concentrations of the transistors are different, and the substrate 1 is divided into several substrate regions. An epitaxial layer is grown on top of the top silicon in each substrate region, and the process optimization steps before the epitaxial layer growth include: K1, depositing a first layer of top silicon 5 over the active region of each substrate region, and in each substrate region deposit a thin film on the upper surface;

K2. Arrange a mask on the upper surface of the film, and the mask includes an anti-reflection layer and a photoresist layer deposited in sequence;

K3, etching the mask above the corresponding substrate region;

K4, etching the film above the corresponding substrate region;

K5. Use pre-cleaning technology for further cleaning;

K6, drying the top layer silicon 5 of the first layer;

K7, sequentially depositing the second layer of top silicon and the third layer of top silicon on the surface of the first layer of top silicon 5, the first layer of top silicon, the second layer of top silicon and the third layer of top silicon are combined to form a combined top silicon;

K8, using an epitaxial growth method to grow an epitaxial layer from the combined top layer silicon.

The following is a specific embodiment of a method for optimizing a FDSOI silicon epitaxial growth process. In this embodiment, the substrate region includes a first substrate 11, a second substrate 12, ... an Nth substrate, where N is an integer, and the present In the embodiment, the first substrate is an N-type silicon substrate, the second substrate is a P-type silicon substrate, and both the first substrate and the second substrate include an SOI region (ie, a silicon substrate region) and a Hybrid region (ie, a doped substrate region), wherein the SOI region of the first substrate is the N-type silicon substrate Ncore, the SOI region of the second substrate is the P-type silicon substrate Pcore, the mask includes a first mask 71, an epitaxial The layer includes a first epitaxial layer 81 grown over the SOI region of the first substrate. Based on the process optimization steps K1 to K8, a first epitaxial layer 81 is grown over the first substrate 11. Before the first epitaxial layer 81 is grown, the first epitaxial layer 81 is grown. Process optimization steps include:

S1. Cover the upper surface of the active region 2 with a first layer of top layer silicon 5, and deposit a first film 61 on the upper surface of each substrate region (see FIG. 3a), and the first film 61 is deposited by the HCD silicon nitride deposition process It is realized that the deposited first film includes silicon nitride, and the thickness of the silicon nitride is 135A;

S2. A first mask 71 is arranged above the first thin film 61, and the first mask 71 includes an anti-reflection layer and a photoresist layer (ie, a photoresist layer) deposited in sequence.

S3 , etching the first mask 71 above the first substrate 11 (see FIG. 3 b ). The first mask removal step includes: first, placing the substrate in an etching machine for degumming, the photoresist layer above the first substrate is removed;

The anti-reflection layer above the first substrate is removed by wet cleaning. The cleaning solution for wet cleaning includes SPM solution. The SPM solution includes: sulfuric acid with a concentration of 98% and hydrogen peroxide with a concentration of 30%, and the ratio of sulfuric acid to hydrogen peroxide It is 5:1, and the cleaning temperature when cleaning is performed by wet cleaning is 125° C. The SPM solution has strong acidity, and the first mask is removed under the corrosion effect of the SPM solution.

S4, etching the first thin film 61 above the first substrate 11, as shown in FIG. 3c, the etching method of the first thin film 61 is as follows: hydrofluoric acid solution (ie DHF), phosphoric acid solution (H ₃ PO ₄ ), hydrogen Ammonium oxide solution (SC ₁ ) and hydrogen chloride solution (SC ₂ ) are used for cleaning. The specific steps of cleaning include: K41, using hydrofluoric acid solution (DHF) to remove the mask polymer, and the hydrofluoric acid solution is an aqueous solution of hydrogen fluoride gas, It has weak acidity and strong corrosiveness, and can effectively remove the mask polymer; after the anti-reflection layer is cleaned by the wet cleaning (ie RCA cleaning) process in the above step S3, problems such as incomplete cleaning and introduction of new impurities are prone to occur. Therefore, hydrofluoric acid solution is used for further cleaning to remove mask polymer and new impurities, preventing mask polymer from remaining on the surface of the first film and reducing the removal effect of the first film; K42, through phosphoric acid solution (H ₃ PO ₄ ) Wash off the first film, the phosphoric acid solution is an aqueous solution of phosphoric acid, the material of the first film mainly includes silicon nitride, and the phosphoric acid solution with moderately strong acidity is used, which can corrode the silicon nitride and effectively remove the first film; K43 , using ammonium hydroxide solution (SC ₁ ) for further cleaning to remove the residual film polymer, the cleaning temperature is 50 ℃, ammonium hydroxide solution (SC ₁ ) generally refers to ammonia monohydrate, which is a kind of ammonium hydroxide (NH _{4 ).} OH) and hydrogen peroxide (H ₂ O ₂ ), pure water (H ₂ O) inorganic compound solution, wherein ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), pure water (H ₂ O) mixed The ratio is 1:1.5:50, which is weakly alkaline and corrosive, and its acidity is less than that of phosphoric acid solution, so the use of this solution can not only remove film residues, but also prevent the first layer of top silicon under the first film from being overetched Etching; K44, use hydrogen chloride solution (SC ₂ ) to clean again to completely remove the residual film polymer, and the cleaning temperature is 35 ℃. Hydrogen chloride solution (SC ₂ ) is a mixture of hydrogen chloride (HCL), hydrogen peroxide and pure water. The mixing ratio of hydrogen chloride, hydrogen peroxide and pure water is 1:1.5:50. Among them, the aqueous solution of hydrogen chloride is commonly known as hydrochloric acid, and its melting point and boiling point are relatively high. Low, thermal stability and corrosiveness, which can further remove the residual thin film polymer, and at the same time, due to the lower cleaning temperature, the reaction is slower, therefore, the first layer of the top layer of silicon can be further prevented from being overetched while cleaning.

S5, further cleaning the first top layer silicon 5 above the first substrate 11 by using a pre-cleaning technology (SiCoNi technology); pre-cleaning (ie, Siconi technology) is a dry plasma chemical pre-cleaning technology, the advantage of which is the cleaning speed High and selective, it is more effective for removing organic pollutants, and can further remove mask polymer, thin film polymer and newly introduced impurities, etc., so as to facilitate the subsequent deposition and growth of top layer silicon.

S6. Dry the first layer of top silicon after cleaning. The drying temperature is controlled at about 650 degrees Celsius, which prevents the layers on the substrate from being separated, deformed or damaged due to excessive temperature. In order to affect the growth effect of subsequent silicon epitaxial growth due to the residual cleaning solution.

S7. On the surface of the first layer of top layer silicon above the first substrate, deposit a second layer of top layer silicon and a third layer of top layer silicon in sequence (the thicknesses of the second layer of top layer silicon and the third layer of top layer silicon are 2 nanometers respectively), and the first layer The top layer silicon is combined with the second layer top layer silicon and the third layer top layer silicon 51 to form the first combined top layer silicon, as shown in FIG. 3d. The thicknesses of the second layer top layer silicon and the third layer top layer silicon are respectively 2 nm to 4 nm. 2 nm is preferred.

S8. A first epitaxial layer 81 is grown on the surface of the first combined top layer silicon, and the first epitaxial layer is SiGe. Specifically, the substrate on which the second layer top layer silicon has been deposited is placed in an epitaxial growth device for epitaxial growth, so that the first epitaxial layer is grown. A SiGe epitaxial layer is grown from the first combined top silicon layer over a substrate, see Figure 3e.

The thin film includes a second thin film, the mask includes a second mask, and the method for optimizing the silicon epitaxial growth process of the field effect transistor further includes: S9, growing a second epitaxial layer on the top silicon surface of the SOI region of the second substrate, and the process The steps include: first removing the remaining first mask by dry cleaning and wet cleaning, and then depositing a second film on the top of the first epitaxial layer 81 of the first substrate 11 and on the top of the remaining first thin film 61 62; and then execute steps S91 to S97 in sequence.

The specific steps of growing the second epitaxial layer on the second combined top layer silicon surface above the second substrate include: S91 , depositing a second epitaxial layer over the first epitaxial layer 81 of the first substrate 11 and over the remaining first film For the thin film 62, the deposition of the second thin film 62 is realized in the same manner as the deposition of the first thin film in step S1, as shown in FIG. 4a;

S92, arranging a second mask 72 on the surface of the second thin film 62, and the second mask 72 includes an anti-reflection layer and a photoresist layer deposited in sequence;

S93 , etching the second mask 72 above the second substrate 12 , and the etching method of the second mask 72 is the same as that of the first mask 71 in step S3 .

S94, the second film 62 above the second substrate 12 is etched, the figure after the second film is etched is shown in Figure 4b, and the etching method of the second film 62 is the same as the etching method of the first film in step S4 : Use hydrofluoric acid solution (DHF), phosphoric acid solution (H ₃ PO ₄ ), ammonium hydroxide solution (SC ₁ ), and hydrogen chloride solution (SC ₂ ) to clean the second film in sequence, and clean the second film above the second substrate. 2. Film removal;

S95, further cleaning the substrate by using a pre-cleaning technique, and the pre-cleaning technique is the same as that in step S5;

S96, sequentially depositing a second layer of top layer silicon, a third layer of top layer silicon 51 on the surface of the first layer of top layer silicon above the second substrate 12, a first layer of top layer silicon, a second layer of top layer silicon, The three-layer top layer silicon is combined to form the second combined top layer silicon, and the thickness of the second layer top layer silicon is 2nm~4nm, preferably 2nm in this embodiment;

S97 , growing a second epitaxial layer from the top silicon of the second combination. The growth mode of the second epitaxial layer is the same as that of the first epitaxial layer, and the second epitaxial layer is SiP, as shown in FIG. 4 c .

Before applying the processing optimization method of the present application to the epitaxial growth of the epitaxial layer of the field effect transistor (the field effect transistor is FDSOI, but not limited to FDSOI), taking the SiGe epitaxial layer growth as an example, the SiGe epitaxial layer can only be selectively grown on the exposed surface. A complete SiGe epitaxial layer is grown on the surface of the silicon, for example, above the active region and above the trench isolation region, and consists of three layers: a SiGe seed layer with a germanium content of about 20%, a SiGe bulk layer with a germanium content of about 35%, As well as the uppermost silicon cap layer, in order to ensure the performance and yield of FDSOI, it is necessary to ensure that the seed layer, bulk layer and silicon cap layer in the SiGe epitaxial growth process of the SiGe epitaxial layer can grow completely.

The method of the present application adopts multiple cleaning methods and top layer silicon secondary deposition methods to optimize the epitaxial growth process to ensure that the three-layer SiGe epitaxial layer or SiP can be grown completely. First, in the actual process, the first thin film (or The cleaning effect of the second film) is easily affected by temperature. When the temperature is low, the reaction rate of the cleaning solution and the film will decrease, and the etching effect will be reduced, resulting in that the thin film polymer of the first film (or the second film) cannot be effectively removed. The problem occurs, the application uses hydrofluoric acid solution (DHF), phosphoric acid solution (H ₃ PO ₄ ), ammonium hydroxide solution (SC ₁ ), hydrogen chloride solution (SC ₂ ) for cleaning in sequence, and controls ammonium hydroxide solution, The cleaning temperature of the hydrogen chloride solution solves the problem that the first film (or the second film) and the film polymer cannot be effectively removed. Subsequently, the Siconi pre-cleaning method was used to further clean and remove the polymer and newly introduced impurities in the process, preventing the film polymer and/or film residue, mask polymer and/or mask residue from blocking. The growth of the epitaxial layer is hindered on the surface, which ensures the complete growth of the subsequent epitaxial layer.

Secondly, the processing process optimization method of the present application also includes deposition of the second top layer silicon and/or the third top layer silicon (the number and thickness of the top layer silicon deposited in the present application can be flexibly set according to actual process requirements). After drying, A second layer of top layer silicon and/or a third layer of top layer silicon is deposited on the surface of the first layer of top layer silicon above the first substrate or the second substrate, and the total thickness of the second layer of top layer silicon and the third layer of top layer silicon is about 4nm , which not only compensates for the possible loss of the first layer of top silicon, but also increases the thickness of the top silicon, so that the top silicon has enough thickness to ensure the complete growth of the epitaxial layer above the active region.

The above are only preferred embodiments of the present application, and the present invention is not limited to the above embodiments. It can be understood that other improvements and changes directly derived or thought of by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.

Claims (10)

1. An FDSOI (fully-diffused silicon on insulator) silicon epitaxial growth process optimization method is characterized in that an FDSOI transistor comprises a substrate, wherein an active region, a groove isolation region and a gate region are distributed on the substrate, the active region comprises a source drain region, and the substrate is divided into a plurality of substrate regions according to different doping concentrations of field effect transistors; it is characterized in that the preparation method is characterized in that,

growing epitaxial layers on top silicon of different substrate areas, wherein the process optimization step before the epitaxial layer growth comprises the following steps: k1, respectively depositing a first layer of top layer silicon above active areas of different substrate areas, and depositing a film on the upper surface of each substrate area, wherein the film comprises silicon nitride;

k2, arranging a mask above the film, wherein the mask comprises an anti-reflection layer and a light resistance layer which are deposited in sequence;

k3, etching the mask above the corresponding substrate area;

k4, etching the film above the corresponding substrate area, wherein the etching mode of the film is as follows: cleaning with hydrofluoric acid solution, phosphoric acid solution, ammonium hydroxide solution and hydrogen chloride solution in sequence, wherein in the step K4, the etching step of the film comprises: k41, removing the mask polymer by using the hydrofluoric acid solution; k42, washing off the membrane by phosphoric acid solution; k43, further cleaning by adopting an ammonium hydroxide solution, and removing the film polymer, wherein the cleaning temperature is 50 ℃; k44, adopting a hydrogen chloride solution to clean again, and thoroughly removing the film polymer, wherein the cleaning temperature is 35 ℃; wherein the ammonium hydroxide solution is a mixed solution of ammonium hydroxide, hydrogen peroxide and pure water;

k5, further cleaning by adopting a pre-cleaning technology;

k6, drying the first layer of top silicon;

k7, sequentially depositing a second layer of top layer silicon and a third layer of top layer silicon on the surface of the first layer of top layer silicon, and combining the first layer of top layer silicon, the second layer of top layer silicon and the third layer of top layer silicon to form combined top layer silicon;

k8, growing an epitaxial layer on the combined top layer silicon by adopting an epitaxial growth method.

2. The FDSOI silicon epitaxial growth process optimization method of claim 1, wherein the substrate region comprises a first substrate, a second substrate to an Nth substrate, wherein N is an integer, the thin film comprises a first thin film, the mask comprises a first mask, the epitaxial layer comprises a first epitaxial layer grown on the first substrate, and the process optimization steps K1 to K8 are adopted to grow the first epitaxial layer on the first substrate.

3. The FDSOI silicon epitaxial growth process optimization method of claim 2, wherein the film comprises a second film and the reticle comprises a second reticle, the process optimization method further comprising: s9, growing a second epitaxial layer on the surface of the top silicon layer above the second substrate, wherein the method comprises the following specific steps: removing the rest of the first mask plate, and depositing a second film above the first epitaxial layer of the first substrate and above the rest of the first film; and then sequentially executing the steps K2-K8.

4. The method as claimed in claim 1 or 3, wherein in step K1, HCD deposition of silicon nitride is used to deposit the film, and the thickness of the silicon nitride is 135A.

5. The FDSOI silicon epitaxial growth process optimization method of claim 4, wherein the step of removing the mask comprises: firstly, placing the substrate covered with the mask plate in an etching machine for photoresist removal treatment, and removing the photoresist layer above the corresponding substrate area;

and removing the anti-reflection layer of the corresponding substrate area by adopting a wet cleaning mode.

6. The method for optimizing the FDSOI silicon epitaxial growth process according to claim 5, wherein the cleaning solution for wet cleaning comprises an SPM solution, the SPM solution comprises 98% sulfuric acid and 30% hydrogen peroxide, the ratio of sulfuric acid to hydrogen peroxide is 5:1, and the cleaning temperature is 125 ℃ when cleaning is carried out by wet cleaning.

7. The FDSOI silicon epitaxial growth process optimization method according to claim 1, wherein the mixing ratio of ammonium hydroxide, hydrogen peroxide and pure water in the ammonium hydroxide solution is 1:1.5: 50; the hydrogen chloride solution is a mixed solution of hydrogen chloride, hydrogen peroxide and pure water, and the mixing ratio of the hydrogen chloride, the hydrogen peroxide and the pure water in the hydrogen chloride solution is 1:1.5: 50.

8. The FDSOI silicon epitaxial growth process optimization method of claim 1, 6 or 7, wherein in the step K6, the deposition thickness of the second layer of top silicon and the deposition thickness of the third layer of top silicon are respectively in the range of 3nm to 5 nm.

9. The method as claimed in claim 8, wherein the drying temperature in step K7 is 650 ℃.

10. The method as claimed in claim 9, wherein in step K8, the epitaxial layer is phosphorus silicon and/or germanium silicon.

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