CN114071856B - Three-dimensional circuit board and preparation method thereof - Google Patents
Three-dimensional circuit board and preparation method thereof Download PDFInfo
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- CN114071856B CN114071856B CN202010760072.1A CN202010760072A CN114071856B CN 114071856 B CN114071856 B CN 114071856B CN 202010760072 A CN202010760072 A CN 202010760072A CN 114071856 B CN114071856 B CN 114071856B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000003475 lamination Methods 0.000 claims description 10
- 238000003825 pressing Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 261
- 238000000034 method Methods 0.000 description 15
- 239000000463 material Substances 0.000 description 11
- 229910000679 solder Inorganic materials 0.000 description 10
- 239000004642 Polyimide Substances 0.000 description 8
- 229920001721 polyimide Polymers 0.000 description 8
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 6
- 239000011112 polyethylene naphthalate Substances 0.000 description 6
- -1 polyethylene terephthalate Polymers 0.000 description 6
- 229920000139 polyethylene terephthalate Polymers 0.000 description 6
- 239000005020 polyethylene terephthalate Substances 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 239000003365 glass fiber Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910000861 Mg alloy Inorganic materials 0.000 description 1
- 229910001297 Zn alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The invention provides a three-dimensional circuit board which comprises a second circuit board, a second insulating layer, a first circuit board, a first insulating layer and a conductive layer. The second insulating layer, the first circuit board and the first insulating layer are sequentially stacked on one side of the second circuit board. The first circuit board is provided with a first through hole, and the first insulating layer is filled in the first through hole and is connected with the second insulating layer. The first insulating layer is provided with a groove corresponding to the first through hole, and the groove extends to the second insulating layer. The conductive layer includes a first line pattern embedded in at least one of the first insulating layer and the second insulating layer and exposed from the groove. The invention also provides a preparation method of the three-dimensional circuit board.
Description
Technical Field
The invention relates to the field of circuit boards, in particular to a three-dimensional circuit board and a preparation method thereof.
Background
In recent years, electronic products are widely used in daily work and life, and demands for miniaturization, multifunctionality, and high performance are increasing. The circuit board is used as a main component of the electronic product, occupies a large space of the electronic product, and therefore the volume of the circuit board influences the volume of the electronic product to a great extent. The mounting surface of the existing circuit board is usually positioned on the front surface or the back surface of the existing circuit board, so that the circuit board is difficult to miniaturize; and some products require electronic components to be mounted on the sides of the circuit board or even buried therein, however, such circuit boards do not meet the requirements.
Disclosure of Invention
In view of the foregoing, there is a need for a three-dimensional circuit board and a method of manufacturing the same that can solve the above-described problems.
An embodiment of the invention provides a three-dimensional circuit board, which comprises a second circuit board, a second insulating layer, a first circuit board, a first insulating layer and a conductive layer. The second insulating layer, the first circuit board and the first insulating layer are sequentially stacked on one side of the second circuit board. The first circuit board is provided with a first through hole, and the first insulating layer is filled in the first through hole and is connected with the second insulating layer. The first insulating layer is provided with a groove corresponding to the first through hole, and the groove extends to the second insulating layer. The conductive layer includes a first line pattern embedded in at least one of the first insulating layer and the second insulating layer and exposed from the groove.
Further, the groove includes a bottom wall and a side wall disposed around the bottom wall, and the first line pattern is located on the bottom wall and the side wall.
Further, the conductive layer further comprises a second circuit pattern embedded in the first insulating layer and exposed from one side of the first insulating layer away from the first circuit board.
Further, the three-dimensional circuit board further includes an electronic component disposed on the conductive layer and embedded in at least one of the first insulating layer and the second insulating layer.
Further, the three-dimensional circuit board further comprises a shielding layer, and the shielding layer is arranged on at least one side wall of the groove.
An embodiment of the present invention provides a method for manufacturing a three-dimensional circuit board, including: providing a mold, wherein the mold comprises a plate body and a protruding part protruding and formed on one side of the plate body; forming a conductive layer on the mold, the conductive layer including a first line pattern on the protrusion and a second line pattern on the board body; providing a first circuit board, a second circuit board, a first insulating layer and a second insulating layer, wherein a first through hole corresponding to the protruding part is formed in the first circuit board, and a second through hole corresponding to the protruding part is formed in the first insulating layer; the second insulating layer, the first circuit board, the first insulating layer and the die are sequentially stacked on one side of the second circuit board and pressed, when stacking is performed, the protruding portion sequentially penetrates through the second through hole and the first through hole and is abutted to the second insulating layer, after pressing, the first insulating layer and the second insulating layer are connected and jointly cover one side of the die, the first circuit pattern is embedded in at least one of the first insulating layer and the second insulating layer, and the second circuit pattern is embedded in the first insulating layer; and removing the die, exposing the first circuit pattern from the groove formed after the protruding part is removed, and exposing the second circuit pattern from one side of the first insulating layer, which is away from the first circuit board, so as to manufacture the three-dimensional circuit board.
Further, before forming the conductive layer on the mold, the method further comprises the following steps: and forming a metal layer on the die, wherein the conductive layer is formed on the metal layer.
Further, before forming the metal layer on the mold, the method further comprises the following steps: and forming a release layer on the die, wherein the metal layer covers one side of the release layer, which is away from the die.
Further, the groove includes a bottom wall and a side wall disposed around the bottom wall, and the first line pattern is located on the bottom wall and the side wall.
Further, after forming the conductive layer on the mold, the method further comprises the steps of: and mounting an electronic element on the conductive layer, and embedding the electronic element into at least one of the first insulating layer and the second insulating layer after lamination.
Further, forming a conductive layer on the mold includes the steps of: and forming a shielding layer on at least one side surface of the protruding part, wherein the shielding layer is positioned on at least one side wall of the groove after lamination.
In the three-dimensional circuit board and the preparation method thereof provided by the embodiment of the invention, the conductive layer is formed on the die, and after being pressed, the formed conductive layer is directly pressed on the first insulating layer and the second insulating layer to prepare the three-dimensional circuit board, so that the preparation process is simplified. In addition, the first circuit pattern is formed on the side wall and the bottom wall of the groove, so that the first circuit pattern is buried in the three-dimensional circuit board, and the size miniaturization is facilitated; and the electronic element can be directly arranged on the side wall and the bottom wall of the groove, thereby meeting the three-dimensional installation requirement of the electronic element.
Drawings
Fig. 1 is a schematic structural diagram of a mold according to an embodiment of the present invention.
Fig. 2 is a schematic view of the structure after forming a conductive layer on the mold shown in fig. 1.
Fig. 3 is a schematic structural diagram of a first circuit board, a second circuit board, a first insulating layer and a second insulating layer according to an embodiment of the present invention.
Fig. 4 is a schematic view of the structure shown in fig. 2 and the structure shown in fig. 3 after being pressed together.
Fig. 5 is a schematic view of the structure of fig. 4 with the mold removed.
Fig. 6 is a schematic view of the structure shown in fig. 5 after a solder mask layer is formed thereon.
Fig. 7 is a mold provided with a shielding layer and an electronic component according to another embodiment of the present invention.
Fig. 8 is a schematic structural diagram of a three-dimensional circuit board according to another embodiment of the present invention.
Description of the main reference signs
Mold 10
Plate body 11
Protruding part 13
First surface 111
Second surface 113
Side 131
Top surface 133
Release layer 12
Metal layer 14
Conductive layers 20, 34, 42
First line pattern 22
Second circuit pattern 24
First circuit board 30
Second circuit board 40
First insulating layer 50
Second insulating layer 60
First through hole 31
Second through hole 52
Insulating layers 36, 44
Groove 53
Bottom wall 533
Side wall 531
Three-dimensional circuit board 100
Solder mask layer 70
Electronic component 90
Shielding layer 80
The invention will be further described in the following detailed description in conjunction with the above-described figures.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without any inventive effort, are within the scope of the present invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
An embodiment of the present invention provides a method for manufacturing a three-dimensional circuit board, including the steps of:
s1, providing a mold, wherein the mold comprises a plate body and a protruding part protruding to form at one side of the plate body;
s2, forming a conductive layer on the die, wherein the conductive layer comprises a first circuit pattern positioned on the protruding part and a second circuit pattern positioned on the plate body part;
S3, providing a first circuit board, a second circuit board, a first insulating layer and a second insulating layer, wherein a first through hole corresponding to the protruding part is formed in the first circuit board, and a second through hole corresponding to the protruding part is formed in the first insulating layer;
S4, stacking the second insulating layer, the first circuit board, the first insulating layer and the die on one side of the second circuit board in sequence and laminating, wherein when stacking, the protruding part sequentially penetrates through the second through hole and the first through hole and is abutted against the second insulating layer, after lamination, the first insulating layer is connected with the second insulating layer and jointly covers one side of the die, the first circuit pattern is embedded in at least one of the first insulating layer and the second insulating layer, and the second circuit pattern is embedded in the first insulating layer;
And S5, removing the die, exposing the first circuit pattern from the groove formed after the protruding part is removed, and exposing the second circuit pattern from one side of the first insulating layer, which is away from the first circuit board, so as to manufacture the three-dimensional circuit board.
Referring to fig. 1, in step S1, a mold 10 is provided, the mold 10 includes a plate 11 and a protrusion 13 protruding from one side of the plate 11.
The plate body 11 includes a first surface 111 and a second surface 113 disposed opposite to each other, and the protruding portion 13 protrudes from the second surface 113. The projection 13 includes a side 131 connected to the second surface 113 and a top 133 disposed away from the second surface 113.
The material of the die 10 is an alloy, and the alloy is one or more selected from stainless steel, aluminum alloy, copper alloy, zinc alloy and magnesium alloy.
Further, after step S1, the method further comprises the following steps: a release layer 12 and a metal layer 14 are sequentially formed on the mold 10. The release layer 12 has elasticity, and can protect the circuit board when the subsequent die 10 and the circuit board are pressed together; and which facilitates subsequent removal of the mold 10. The metal layer 14 may be used for subsequent conductive layer formation. The release layer 12 and the metal layer 14 may be formed on the mold 10 by attaching or coating. The release layer 12 completely covers the second surface 113 of the plate body 11 and the top surface 133 and the side surfaces 131 of the protruding portion 13. The metal layer 14 completely covers the side of the release layer 12 facing away from the mold 10.
Referring to fig. 2, in step S2, a conductive layer 20 is formed on the mold 10, wherein the conductive layer 20 includes a first circuit pattern 22 on the protruding portion 13 and a second circuit pattern 24 on the plate body 11.
In this embodiment, a plurality of second circuit patterns 24 are formed on the plate body 11, and the plurality of second circuit patterns 24 are distributed on the second surface 113 at intervals; the protruding portion 13 has a plurality of first circuit patterns 22 formed thereon, and the plurality of first circuit patterns 22 are spaced apart from each other on the side surface 131 and the top surface 133.
The conductive layer 20 is made of copper, and can be manufactured by exposing, developing, copper plating, stripping and other processes in conventional technology.
In this embodiment, the conductive layer 20 is formed on the metal layer 14.
Referring to fig. 3, in step S3, a first circuit board 30, a second circuit board 40, a first insulating layer 50 and a second insulating layer 60 are provided, the first circuit board 30 is provided with a first through hole 31 corresponding to the protruding portion 13, and the first insulating layer 50 is provided with a second through hole 52 corresponding to the protruding portion 13.
The first circuit board 30 may be a single-layer board structure or a multi-layer board structure, and may be a flexible board, a rigid board or a flexible-rigid board. In this embodiment, the first circuit board 30 is a hard board, and includes two conductive layers 34 and an insulating layer 36 sandwiched between the two conductive layers 34. The insulating layer 36 is made of a prepreg (Prepreg, PP) containing glass fibers and epoxy resin. Optionally, the number of layers of the conductive layer 34 and the insulating layer 36 in the first circuit board 30 may be set according to actual requirements.
The first via 31 penetrates the insulating layer 36 and the two conductive layers 34. The first through hole 31 corresponds to the protruding portion 13, which allows the protruding portion 13 to pass therethrough. The first through hole 31 may be formed by a stamping method. In this embodiment, the size of the first through hole 31 is larger than the size of the protruding portion 13.
The first circuit board 30 further comprises a conductive structure 35 for electrically connecting the two conductive layers 34. Specifically, the conductive structure 35 penetrates through the two conductive layers 34 and the insulating layer 36, and electrically connects the two conductive layers 34.
The second circuit board 40 may be a single-layer board structure or a multi-layer board structure, and may be a flexible board, a rigid board or a flexible-rigid board. In this embodiment, the second circuit board 40 is a flexible board, and includes two conductive layers 42 and an insulating layer 44 interposed between the two conductive layers 42. The insulating layer 44 is made of Polyimide (PI). Optionally, the number of layers of the conductive layer 42 and the insulating layer 44 in the second circuit board 40 may be set according to actual requirements.
The second through hole 52 may be formed by a stamping method, and its size is matched with that of the protruding portion 13. In this embodiment, the second through hole 52 has the same size as the protruding portion 13.
The material of the first insulating layer 50 and the second insulating layer 60 may be one of a prepreg (Prepreg, PP) including glass fiber and epoxy resin, polyimide (PI), polyethylene terephthalate (PolyethyleneTerephthalate, PET) and polyethylene naphthalate (PolyethyleneNaphthalate, PEN). The material of the first insulating layer 50 and the material of the second insulating layer 60 may be the same or different. In this embodiment, the material of the first insulating layer 50 and the material of the second insulating layer 60 are PP.
Referring to fig. 4, in step S4, the second insulating layer 60, the first circuit board 30, the first insulating layer 50 and the mold 10 are sequentially stacked on one side of the second circuit board 40 and pressed, when stacked, the protruding portion 13 sequentially passes through the second through hole 52 and the first through hole 31 and abuts against the second insulating layer 60, after being pressed, the first insulating layer 50 and the second insulating layer 60 are connected and jointly cover one side of the mold 10, the first circuit pattern 22 is embedded in at least one of the first insulating layer 50 and the second insulating layer 60, and the second circuit pattern 24 is embedded in the first insulating layer 50.
Specifically, when stacking, the second insulating layer 60 covers a side of one conductive layer 42 of the second circuit board 40 facing away from the insulating layer 44, the one conductive layer 34 of the first circuit board 30 covers a side of the second insulating layer 60 facing away from the second circuit board 40, the first insulating layer 50 covers a side of the other conductive layer 34 of the first circuit board 30 facing away from the insulating layer 36, and the mold 10 covers a side of the first insulating layer 50 facing away from the first circuit board 30. Wherein the protruding portion 13 is accommodated in the second through hole 52 and the first through hole 31, the first line pattern 22 disposed on the side surface 131 is located between the side walls of the first through hole 31 and the second through hole 52 and the side surface 131, and the first line pattern 22 disposed on the top surface 133 is located between the second insulating layer 60 and the top surface 133; the second line pattern 24 is located between the board body 11 and the first insulating layer 50.
In this embodiment, the pressing is performed by a hot pressing method. When the first insulating layer 50 and the second insulating layer 60 are fused, the second circuit pattern 24 on the plate body 11 is directly embedded in the fused first insulating layer 50, and the first circuit pattern 22 on the top surface 133 of the protruding portion 13 is directly embedded in the fused second insulating layer 60; and a melted portion of the first insulation layer 50 is filled into the first via hole 31, connected to the second insulation layer 60, and fills a gap between a sidewall of the first via hole 31 and the protrusion 13, so that the first line pattern 22 on the side 131 of the protrusion 13 is embedded in the first insulation layer 50.
After lamination, the first insulating layer 50 and the second insulating layer 60 are connected and jointly cover the side of the mold 10 provided with the protruding portion 13. The first insulating layer 50 includes a first portion (not shown) on the first wiring board 30 and a second portion (not shown) filled in the second through hole 52 and connected to the second insulating layer 60. The second circuit pattern 24 is embedded in the first portion, the first circuit pattern 22 on the side surface 131 is embedded in the second portion, and the first circuit pattern 22 on the top surface 133 is embedded in the second insulating layer 60.
Referring to fig. 4 and 5, in step S5, the mold 10 is removed, the first circuit pattern 22 is exposed from the recess 53 formed by removing the protrusion 13, and the second circuit pattern 24 is exposed from the side of the first insulating layer 50 facing away from the first circuit board 30, so as to obtain the three-dimensional circuit board 100.
After removing the protruding portion 13 of the mold 10, a groove 53 surrounded by the first insulating layer 50 and the second insulating layer 60 is formed. The groove 53 is disposed corresponding to the first through hole 31. The recess 53 includes a bottom wall 533 and a side wall 531 disposed around the bottom wall 533. The side walls 531 correspond to the side surfaces 131 of the protruding parts 13 such that the first circuit patterns 22 on the side surfaces 131 of the protruding parts 13 are press-fit formed on the side walls 531 of the grooves 53. The bottom wall 533 corresponds to the top surface 133 of the protruding portion 13, so that the first circuit pattern 22 on the top surface 133 of the protruding portion 13 is press-fit formed on the bottom wall 533 of the recess 53. In the present embodiment, the bottom wall 533 of the groove 53 is formed by the second insulating layer 60, and the side wall 531 of the groove 53 is formed by the second insulating layer 60 and the first insulating layer 50 together.
After removing the plate body 11 of the mold 10, the second circuit pattern 24 is exposed from the side of the first insulating layer 50 facing away from the first circuit board 30. The side of the first insulating layer 50 facing away from the first circuit board 30 serves as the front or rear side of the three-dimensional circuit board 100.
The first and second circuit patterns 22 and 24 may each be used to mount electronic components such as resistors, capacitors, inductors, and the like.
When the electronic component is mounted on the first circuit pattern 22, the electronic component is accommodated in the groove 53, that is, the electronic component is embedded in the three-dimensional circuit board 100, so that the three-dimensional circuit board 100 can be miniaturized. In addition, since the first circuit pattern 22 may be disposed on the sidewall 531 of the groove 53, it may satisfy the requirement of mounting electronic components on the side of the circuit board.
When the electronic component is mounted on the second circuit pattern 24, the electronic component is located on the front or back of the three-dimensional circuit board 100, that is, the second circuit pattern 24 can meet the requirement of mounting the electronic component on the front or back of the circuit board.
The step S5 specifically comprises the following steps: the mold 10 is removed by tearing the release layer 12, the metal layer 14 is removed to expose the first circuit pattern 22 from the groove 53, and the second circuit pattern 24 is exposed from the side of the first insulation layer 50 facing away from the first circuit board 30, thereby manufacturing the three-dimensional circuit board 100. The metal layer 14 may be removed using an etching process.
Referring to fig. 6, after removing the mold 10, the preparation method further includes the steps of: a solder resist layer 70 is formed on the first insulating layer 50. The solder mask layer 70 covers a side of the first insulating layer 50 away from the first circuit board 30, and the second circuit pattern 24 is exposed outside the solder mask layer 70 (or alternatively covers the first circuit pattern 22 on the side 131 of the protruding portion 13 by spraying). The solder mask layer 70 may be made of insulating ink, and may be formed by printing or spraying.
Referring to fig. 7, in some embodiments, a shielding layer 80 may be further formed on the mold 10 when the conductive layer 20 is formed in step S2. The shielding layer 80 is made of metal for shielding external interference electromagnetic signals. In this embodiment, the shielding layer 80 is located on at least one side 131 of the protruding portion 13, and the plurality of first circuit patterns 22 are located on the other side 131 and the top 133 of the protruding portion 13. It will be appreciated that the shield 80 may completely or partially cover the sides 131 of the protrusion 13. In this embodiment, the shielding layer 80 completely covers the side surface 131 of the protruding portion 13.
Referring to fig. 7, after step S2, the method further includes the following steps: an electronic component 90 is mounted on the conductive layer 20. The electronic component 90 may be mounted on the conductive layer 20 by surface assembly techniques. The electronic component 90 may be a capacitor, a resistor, an inductor, or the like. In the present embodiment, a part of the electronic components 90 are mounted on the first circuit pattern 22, and a part of the electronic components 90 are mounted on the second circuit pattern 24.
Referring to fig. 8, after the lamination, the shielding layer 80 is laminated on at least one side wall 531 of the groove 53, and the first circuit pattern 22 on the other side surface 131 of the protrusion 13 is laminated on the other side wall 531 of the groove 53. In this embodiment, the shielding layer 80 completely covers at least one sidewall 531 of the recess 53.
Referring to fig. 8, after lamination, the electronic component 90 is embedded in at least one of the first insulating layer 50 and the second insulating layer 60. In this embodiment, after the lamination, the electronic component 90 mounted on the second circuit pattern 24 is completely embedded in the first insulating layer 50, and the electronic component mounted on the first circuit pattern 22 is completely embedded in the second insulating layer 60.
According to the method for manufacturing the three-dimensional circuit board 100 provided by the embodiment of the invention, the conductive layer 20 is formed on the die 10, and after lamination, the formed conductive layer 20 is directly laminated on the first insulating layer 50 and the second insulating layer 60 to manufacture the three-dimensional circuit board 100, so that the manufacturing process is simplified. In addition, the first line pattern 22 is formed on the side wall 531 and the bottom wall 533 of the recess 53 such that the first line pattern 22 is buried in the three-dimensional circuit board 100, which is advantageous in downsizing; and the electronic components can be directly mounted on the side wall 531 and the bottom wall 533 of the groove 53, so as to meet the three-dimensional mounting requirement of the electronic components.
Referring to fig. 6, an embodiment of the present invention provides a three-dimensional circuit board 100, which includes a second circuit board 40, a second insulating layer 60, a first circuit board 30, a first insulating layer 50 and a conductive layer 20, wherein the second insulating layer 60, the first circuit board 30 and the first insulating layer 50 are sequentially stacked on one side of the second circuit board 40, the first circuit board 30 is provided with a first through hole 31, the first insulating layer 50 is filled in the first through hole 31 and is connected with the second insulating layer 60, a groove 53 is formed at a position of the first insulating layer 50 corresponding to the first through hole 31, the groove 53 extends to the second insulating layer 60, the conductive layer 20 includes a first circuit pattern 22, and the first circuit pattern 22 is embedded in at least one of the first insulating layer 50 and the second insulating layer 60 and is exposed from the groove 53.
The recess 53 includes a bottom wall 533 and a side wall 531 surrounding the bottom wall 533, and in this embodiment, the bottom wall 533 of the recess 53 is formed by the second insulating layer 60, and the side wall 531 of the recess 53 is formed by the second insulating layer 60 and the first insulating layer 50. The first line pattern 22 is located on at least one of the bottom wall 533 and the side wall 531. In this embodiment, the number of the first line patterns 22 is plural, and the first line patterns 22 are distributed on the bottom wall 533 and the side wall 531 of the recess 53 at intervals.
When electronic components (such as resistors, capacitors, inductors, etc.) are mounted on the first circuit pattern 22, the electronic components are accommodated in the grooves 53, i.e., the electronic components are embedded in the three-dimensional circuit board 100, so that the three-dimensional circuit board 100 can be miniaturized. In addition, since the first circuit pattern 22 may be disposed on the sidewall 531 of the groove 53, it may satisfy the requirement of mounting electronic components on the side of the circuit board.
The conductive layer 20 further includes a second circuit pattern 24. The second circuit pattern 24 is embedded in the first insulating layer 50 and is exposed from a side of the first insulating layer 50 facing away from the first circuit board 30. In this embodiment, the number of the second circuit patterns 24 is plural, and the plurality of second circuit patterns 24 are distributed at intervals on the side of the first insulating layer 50 facing away from the first circuit board 30. The side of the first insulating layer 50 facing away from the first circuit board 30 serves as the front or back surface of the three-dimensional circuit board 100, and the second circuit pattern 24 may satisfy the requirement of mounting electronic components on the front or back surface of the circuit board.
The first circuit board 30 may be a single-layer board structure or a multi-layer board structure, and may be a flexible board, a rigid board or a flexible-rigid board. In this embodiment, the first circuit board 30 is a hard board, and includes two conductive layers 34 and an insulating layer 36 sandwiched between the two conductive layers 34. The insulating layer 36 is made of a prepreg (Prepreg, PP) containing glass fibers and epoxy resin. Optionally, the number of layers of the conductive layer 34 and the insulating layer 36 in the first circuit board 30 may be set according to actual requirements. The first via 31 penetrates the insulating layer 36 and the two conductive layers 34.
The first circuit board 30 further comprises a conductive structure 35 for electrically connecting the two conductive layers 34. Specifically, the conductive structure 35 penetrates through the two conductive layers 34 and the insulating layer 36, and electrically connects the two conductive layers 34.
The second circuit board 40 may be a single-layer board structure or a multi-layer board structure, and may be a flexible board, a rigid board or a flexible-rigid board. In this embodiment, the second circuit board 40 is a flexible board, and includes two conductive layers 42 and an insulating layer 44 interposed between the two conductive layers 42. The insulating layer 44 is made of Polyimide (PI). Optionally, the number of layers of the conductive layer 42 and the insulating layer 44 in the second circuit board 40 may be set according to actual requirements.
The first insulating layer 50 is sandwiched between the conductive layer 20 and one of the conductive layers 34 of the first wiring board 30. The second insulating layer 60 is sandwiched between the other conductive layer 34 of the first circuit board 30 and one conductive layer 42 of the second circuit board 40.
The material of the first insulating layer 50 and the second insulating layer 60 may be one of a prepreg (Prepreg, PP) including glass fiber and epoxy resin, polyimide (PI), polyethylene terephthalate (Polyethylene Terephthalate, PET), and polyethylene naphthalate (Polyethylene Naphthalate, PEN). The material of the first insulating layer 50 and the material of the second insulating layer 60 may be the same or different. In this embodiment, the material of the first insulating layer 50 and the material of the second insulating layer 60 are PP.
The three-dimensional circuit board 100 further includes a solder mask layer 70. The solder mask layer 70 covers a side of the first insulating layer 50 away from the first circuit board 30, and the second circuit pattern 24 is exposed from the solder mask layer 70. The solder mask layer 70 may be formed by printing, optionally with an insulating ink.
Referring to fig. 8, in some embodiments, the three-dimensional circuit board 100 further includes a shielding layer 80 and an electronic component 90. The shielding layer 80 is disposed on at least one sidewall 531 of the recess 53. In this embodiment, the shielding layer 80 completely covers at least one sidewall 531 of the recess 53. The shielding layer 80 is made of metal for shielding external interference electromagnetic signals.
The electronic component 90 is disposed on the conductive layer 20 and is fully embedded in at least one of the first insulating layer 50 and the second insulating layer 60. The electronic component 90 may be mounted on the conductive layer 20 by surface assembly techniques. The electronic component 90 may be a capacitor, a resistor, an inductor, or the like. In this embodiment, a part of the electronic components 90 are mounted on the second circuit pattern 24 and embedded in the first insulating layer 50; a portion of the electronic component 90 is mounted on the first circuit pattern 22 and embedded in the second insulating layer 60.
The foregoing disclosure is merely illustrative of the present invention and is not intended to limit the invention thereto, therefore, equivalent variations of the invention may be made and fall within the scope of the invention.
Claims (9)
1. The utility model provides a three-dimensional circuit board, its characterized in that includes second circuit board, second insulating layer, first circuit board, first insulating layer and conducting layer, the second insulating layer first circuit board with first insulating layer stacks gradually and sets up one side of second circuit board, first through-hole has been seted up to first circuit board, first insulating layer fill in the first through-hole and with the second insulating layer is connected, first insulating layer corresponds first through-hole department has seted up flutedly, the recess extends to the second insulating layer, the conducting layer includes first circuit pattern, first circuit pattern inlay in the second insulating layer or inlay in the first insulating layer with in the second insulating layer, first circuit pattern is followed the recess exposes, the recess includes the diapire with encircle the lateral wall that the diapire set up, first circuit pattern is located the diapire with on the lateral wall.
2. The three-dimensional circuit board of claim 1, wherein the conductive layer further comprises a second circuit pattern embedded in the first insulating layer and exposed from a side of the first insulating layer facing away from the first circuit board.
3. The three-dimensional circuit board of claim 1, further comprising an electronic component disposed on the conductive layer and embedded in at least one of the first insulating layer and the second insulating layer.
4. The three-dimensional circuit board of claim 1, further comprising a shielding layer disposed on at least one sidewall of the recess.
5. A preparation method of a three-dimensional circuit board comprises the following steps:
Providing a mold, wherein the mold comprises a plate body and a protruding part protruding and formed on one side of the plate body;
forming a conductive layer on the mold, the conductive layer including a first line pattern on the protrusion and a second line pattern on the board body;
Providing a first circuit board, a second circuit board, a first insulating layer and a second insulating layer, wherein a first through hole corresponding to the protruding part is formed in the first circuit board, and a second through hole corresponding to the protruding part is formed in the first insulating layer;
The second insulating layer, the first circuit board, the first insulating layer and the die are sequentially stacked on one side of the second circuit board and pressed, when stacking is performed, the protruding part sequentially penetrates through the second through hole and the first through hole and is abutted against the second insulating layer, after pressing, the first insulating layer is connected with the second insulating layer and jointly covers one side of the die, the first circuit pattern is embedded in the second insulating layer or embedded in the first insulating layer and the second insulating layer, and the second circuit pattern is embedded in the first insulating layer;
And removing the die, exposing the first circuit pattern from the groove formed after the protruding part is removed, and exposing the second circuit pattern from one side of the first insulating layer, which is away from the first circuit board, so as to manufacture the three-dimensional circuit board.
6. The method of manufacturing a three-dimensional circuit board according to claim 5, further comprising the steps of, before forming the conductive layer on the mold: and forming a metal layer on the die, wherein the conductive layer is formed on the metal layer.
7. The method of manufacturing a three-dimensional circuit board according to claim 6, further comprising the steps of, before forming the metal layer on the mold: and forming a release layer on the die, wherein the metal layer covers one side of the release layer, which is away from the die.
8. The method of manufacturing a three-dimensional circuit board according to claim 6, further comprising the steps of, after forming a conductive layer on the mold: and mounting an electronic element on the conductive layer, and embedding the electronic element into at least one of the first insulating layer and the second insulating layer after lamination.
9. The method of manufacturing a three-dimensional circuit board according to claim 6, wherein forming a conductive layer on the mold comprises the steps of: and forming a shielding layer on at least one side surface of the protruding part, wherein the shielding layer is positioned on at least one side wall of the groove after lamination.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW201032302A (en) * | 2009-02-16 | 2010-09-01 | Unimicron Technology Corp | Package substrate structure with cavity and method for making the same |
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| JP5554868B1 (en) * | 2013-07-03 | 2014-07-23 | 太陽誘電株式会社 | Manufacturing method of substrate with cavity |
| KR20150009826A (en) * | 2013-07-17 | 2015-01-27 | 삼성전자주식회사 | Device embedded package substrate and Semiconductor package including the same |
| US10321560B2 (en) * | 2015-11-12 | 2019-06-11 | Multek Technologies Limited | Dummy core plus plating resist restrict resin process and structure |
| KR20170067481A (en) * | 2015-12-08 | 2017-06-16 | 삼성전기주식회사 | Printed circuit board, eletronic device package the same and method for manufacturing for printed circuit board |
| KR102647325B1 (en) * | 2018-08-06 | 2024-03-14 | 엘지이노텍 주식회사 | Circuit board and semiconductor package comprising same |
| KR102683289B1 (en) * | 2018-12-17 | 2024-07-10 | 삼성전기주식회사 | Printed circuit board |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW201032302A (en) * | 2009-02-16 | 2010-09-01 | Unimicron Technology Corp | Package substrate structure with cavity and method for making the same |
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