CN114050159B

CN114050159B - Storage device and method for manufacturing the same

Info

Publication number: CN114050159B
Application number: CN202111342580.9A
Authority: CN
Inventors: 涂志康
Original assignee: Wuhan Xinxin Integrated Circuit Co ltd
Current assignee: Wuhan Xinxin Integrated Circuit Co ltd
Priority date: 2021-11-12
Filing date: 2021-11-12
Publication date: 2024-11-19
Anticipated expiration: 2041-11-12
Also published as: CN114050159A

Abstract

The present invention provides a storage device and a method for manufacturing the same. A heat treatment process is used to convert the material of a semi-floating gate material layer of a portion of thickness located above a contact window from polycrystalline silicon to single crystal silicon; the converted area is defined as a convex body. The present invention takes a different approach and uses a heat treatment method to form a convex body, thereby avoiding the failure of the semi-floating gate transistor caused by the difficulty in controlling the etching process accuracy due to the small etching selectivity ratio between the polycrystalline silicon layer and the substrate in the conventional etching process. The semi-floating gate material layer and the drain region of the present invention are connected only through the convex body, and the area of the leakage path is only the physical width of the convex body that can be precisely controlled; the built-in potential barrier in the convex body can prevent the diffusion of carriers between the semi-floating gate material layer and the drain region in a non-working state. As a result, the leakage of stored charge in the semi-floating gate is greatly reduced, and the stability of the stored information is improved.

Description

Memory device and method of manufacturing the same

Technical Field

The invention relates to the technical field of semiconductors, in particular to a memory device and a manufacturing method thereof.

Background

Semiconductor memories are used in various electronic fields. Wherein the nonvolatile memory can store data for a long period of time in the event of power failure. Semi-floating gate transistors are a mainstream nonvolatile memory. The semi-floating gate transistor replaces the traditional silicon oxide erasing window by utilizing the quantum Tunneling effect of a Tunneling Field-Effect Transistor (TFET) and a pn junction diode, so that the charge and discharge of the floating gate are realized, the working voltage of the transistor can be greatly reduced, the working speed of the transistor is improved, the faster data writing and erasing under low voltage are realized, and the requirement of low power consumption of a chip is conveniently met.

Fig. 1a and 1b are schematic cross-sectional structures of a conventional semi-floating gate transistor. Referring to fig. 1a, a doped region N is formed in an upper portion of a substrate 11, a U-shaped trench is formed in the substrate 11, and the doped regions N on both sides of the U-shaped trench are respectively configured as a source region 12 and a drain region 13. An insulating layer 14 is formed on the surface of the U-shaped groove, a polysilicon layer 15 fills the U-shaped groove and covers the upper surface of the substrate 11, and a patterned photoresist 16 is formed on the upper surface of the polysilicon layer 15. Referring to fig. 1b, in the semi-floating gate forming process, the contact window between the polysilicon layer 15 and the substrate 11 is mostly etched, and the polysilicon layer 15 and a part of the thickness of the substrate 11 are etched together to form a bump T. Specifically, the patterned photoresist 16 is used as a mask to etch the polysilicon layer 15 and a portion of the thickness of the substrate 11, and the remaining polysilicon layer is used as a semi-floating gate 15', where the semi-floating gate 15' contacts a portion of the substrate 11 that is not etched on a side near the drain region 13 and forms a pn junction contact with the drain region 13. The portion of the substrate 11 above the etch stop surface that is not etched is referred to as a convex body T (dashed box portion).

The semi-floating gate transistor with the convex body T is a preferable structure; however, in the process of etching the polysilicon layer 15 and the substrate 11 with partial thickness together to form the convex body T, since the etching selection ratio of the polysilicon layer 15 to the substrate 11 is small, it is difficult to control the process precision in practical application, and if the etching is insufficient, the polysilicon layer 15 remains on the substrate 11 on both sides uncovered by the patterned photoresist 16; an over-etch may result in an etch stop surface (the remaining upper surface of the substrate) below the lower surface of the doped region N, and both under-and over-etch may cause the semi-floating gate transistor to fail.

Disclosure of Invention

The invention provides a memory device and a manufacturing method thereof, wherein a heat treatment method is adopted to form a quasi-convex body, so that the problem that a semi-floating gate transistor is invalid due to the fact that the etching selection ratio of a polycrystalline silicon layer to a substrate is very small and the etching process precision is difficult to control in the conventional process of forming the convex body by etching is avoided.

The invention provides a manufacturing method of a memory device, which comprises the following steps:

Providing a substrate, wherein the substrate comprises a storage unit area, and a common source area, a first drain area and a second drain area which are positioned at two sides of the common source area are preset at one side of the upper surface of the substrate of the storage unit area;

forming a gate insulating layer on the substrate of the memory cell region, wherein a first contact window and a second contact window exposing the substrate are formed in the gate insulating layer, the first contact window is positioned between the common source region and the first drain region, and the second contact window is positioned between the common source region and the second drain region;

Forming a semi-floating gate material layer, wherein the semi-floating gate material layer covers the substrate exposed by the first contact window and the second contact window and also covers the gate insulation layer positioned between the first contact window and the second contact window; the semi-floating gate material layer is made of polysilicon;

Performing a heat treatment process to convert the material of the semi-floating gate material layer with partial thickness above the first contact window and the second contact window from polysilicon to monocrystalline silicon; the transformed regions are defined as asperities.

Further, the temperature of the heat treatment is in the range of 1000 ℃ to 1200 ℃.

Further, the substrate also comprises a peripheral area, and the peripheral area is distributed with an active area; the heat treatment process comprises a thermal oxidation process, and a gate oxide layer is grown on the surface of the substrate of the active region of the peripheral region.

Further, after the thermal oxidation process is performed, the method further comprises:

doping nitrogen into the gate oxide layer by adopting a plasma nitriding process; and

And stabilizing the nitrogen doping and repairing the plasma damage in the gate oxide layer by adopting a high-temperature annealing process.

Further, providing the substrate comprises: doping ions of a second doping type in the substrate to form a well region; doping ions of a first doping type in the well region to form a doped region, wherein the doped region extends from the interior of the well region to the upper surface of the substrate, and the common source region, the first drain region and the second drain region are formed on the top of the doped region;

forming the layer of semi-floating gate material includes doping ions of the second doping type in the layer of semi-floating gate material.

Further, before forming the gate insulating layer, forming a first trench in the substrate between the common source region and the first drain region, and forming a second trench in the substrate between the common source region and the second drain region; the first contact window is located between the first drain region and the first trench, and the second contact window is located between the second drain region and the second trench.

Further, after the gate insulating layer and the floating gate material layer are formed, the gate insulating layer also covers inner surfaces of the first trench and the second trench, and the floating gate material layer covers the gate insulating layer and fills the first trench and the second trench.

Further, after the semi-floating gate material layer is formed, before the heat treatment process is performed, the method further comprises:

and forming an inter-gate dielectric layer, wherein the inter-gate dielectric layer at least covers the upper surface and the side surface of the floating gate material layer.

Further, after performing the heat treatment process, the method further includes:

Forming a control gate material layer, wherein the control gate material layer covers the inter-gate dielectric layer;

Etching the control gate material layer, the inter-gate dielectric layer and the floating gate material layer of the common source region, and etching the control gate material layer of the first drain region and the second drain region; the rest of the control gate material layer, the inter-gate dielectric layer and the floating gate material layer form a first gate stack at the part between the first drain region and the common source region, and form a second gate stack at the part between the second drain region and the common source region; and

And forming side walls on the side walls of the first grid electrode lamination and the second grid electrode lamination, performing ion implantation, forming a common source electrode in the substrate corresponding to the common source region, forming a first drain electrode in the substrate corresponding to the first drain region, and forming a second drain electrode in the substrate corresponding to the second drain region.

The invention also provides a manufacturing method of the memory device, which is characterized by comprising the following steps:

Providing a substrate, wherein the substrate comprises a storage unit area, and a source area and a drain area are preset on one side of the upper surface of the substrate in the storage unit area;

forming a gate insulating layer on the substrate of the memory cell region, wherein a contact window exposing the substrate is formed in the gate insulating layer, and the contact window is close to one side of the drain region;

Forming a semi-floating gate material layer, wherein the semi-floating gate material layer covers the substrate exposed by the contact window and also covers the gate insulation layer positioned between the contact window and the source region; the semi-floating gate material layer is made of polysilicon;

performing a heat treatment process to convert the material of the semi-floating gate material layer with partial thickness above the contact window from polysilicon to monocrystalline silicon; the transformed regions are defined as asperities.

Further, after forming the semi-floating gate material layer, before performing the heat treatment process, the method further includes:

Forming a control gate material layer, wherein the control gate material layer covers the inter-gate dielectric layer and the gate insulating layers positioned on two sides of the inter-gate dielectric layer;

Etching the control gate material layer of the source region and the drain region; the rest of the control gate material layer, the inter-gate dielectric layer and the floating gate material layer form a gate stack; and

And forming a side wall on the side wall of the grid electrode lamination, performing ion implantation, forming a source electrode in the substrate corresponding to the source region, and forming a drain electrode in the substrate corresponding to the drain region.

The present invention provides a memory device characterized by comprising:

A substrate, which comprises a memory cell area, wherein a source area and a drain area are preset on one side of the upper surface of the substrate in the memory cell area;

A gate insulating layer is formed on the substrate of the memory cell region, a contact window exposing the substrate is formed in the gate insulating layer, and the contact window is close to one side of the drain region;

A semi-floating gate material layer covering the substrate exposed by the contact window and also covering the gate insulation layer between the contact window and the source region; the semi-floating gate material layer is made of polysilicon;

And the quasi-convex body is positioned in the semi-floating gate material layer with partial thickness above the contact window, and the quasi-convex body is made of monocrystalline silicon converted from the polycrystalline silicon.

Further, the memory device includes a semi-floating gate transistor; the semi-floating gate transistor includes: the source region, the drain region, the quasi-convex body positioned above the contact window, the semi-floating gate, the inter-gate dielectric layer and the control gate.

Further, two adjacent semi-floating gate transistors share a source region.

Further, the substrate also comprises a peripheral region, wherein an active region is distributed in the peripheral region, and a gate oxide layer grows on the surface of the substrate in the active region.

Compared with the prior art, the invention has the following beneficial effects:

1. According to the memory device and the manufacturing method thereof, a heat treatment process is adopted, so that the material of the semi-floating gate material layer with partial thickness above the contact window is converted into monocrystalline silicon from polycrystalline silicon; the transformed regions are defined as asperities. In the existing memory device, the asperities are part of the substrate, and the semi-floating gate (polysilicon layer) and the asperities are stacked together in different units. The invention adopts a heat treatment method to form the quasi-convex body on the body of the semi-floating gate material layer, the quasi-convex body is used as a part of the body of the semi-floating gate material layer, namely, the semi-floating gate material layer and the quasi-convex body are of an integrated structure, and the structure is different from the structure that the semi-floating gate and the convex body of the traditional storage device are stacked together for different individuals. The etching step of etching the polysilicon layer and a part of the thickness of the substrate together in the process of fig. 1a and 1b to form the convex body is omitted, and the failure of the semi-floating gate transistor caused by the fact that the etching selection ratio of the polysilicon layer to the substrate is very small and the etching process precision is difficult to control is avoided.

The invention develops a new way, a heat treatment method is adopted to form a quasi-convex body, the semi-floating gate material layer is connected with the drain region through the quasi-convex body, and the area of the leakage path is only the physical width of the quasi-convex body which can be accurately controlled; the built-in barrier in the quasi-convex body can prevent the diffusion of carriers between the semi-floating gate material layer and the drain region in a non-working state. Therefore, leakage of stored charges in the semi-floating gate is greatly reduced, and the stability of stored information is improved. The semi-floating gate transistor failure caused by the fact that the etching selection ratio of the polycrystalline silicon layer to the substrate is small and the etching process precision is difficult to control is avoided.

2. The quasi-convex body above the first contact window is used as a channel of the vertical tunneling field effect transistor to be connected with the semi-floating gate material layer and the drain region, occupies small area of a semiconductor substrate, and is beneficial to improving the integration density of chips; in the process of manufacturing, the width of the quasi-convex body can be further reduced, the requirement of the device on the area of the semiconductor substrate is reduced, and an optimization space is provided for improving the integration density of the device chip.

Drawings

Fig. 1a is a schematic cross-sectional view of a prior art semi-floating gate transistor.

Fig. 1b is a schematic cross-sectional view of a prior art semi-floating gate transistor after forming a protrusion.

Fig. 2 is a flowchart of a method for manufacturing a memory device according to the present embodiment.

Fig. 3a is a schematic cross-sectional view of the memory device of the present embodiment after forming the first trench and the second trench.

Fig. 3b is a top view of the memory device of the present embodiment after forming the first trench and the second trench.

Fig. 4 is a cross-sectional view of the memory device of the present embodiment after forming a second insulating layer.

Fig. 5 is a cross-sectional view of the memory device of the present embodiment after forming a bottom anti-reflective layer and a patterned photoresist.

Fig. 6 is a cross-sectional view of the memory device of the present embodiment after forming a first contact window and a second contact window.

Fig. 7 is a cross-sectional view of the memory device of the present embodiment after forming an original layer of floating gate material.

Fig. 8 is a cross-sectional view of the memory device of the present embodiment after forming a semi-floating gate material layer.

Fig. 9 is a cross-sectional view of the memory device of the present embodiment after forming an inter-gate dielectric layer.

Fig. 10 is a cross-sectional view of the memory device of the present embodiment after forming a bump-like body.

Fig. 11 is a cross-sectional view showing a method of manufacturing a memory device of the present embodiment in which a gate oxide layer is not formed in a peripheral region.

Fig. 12 is a cross-sectional view of the memory device of the present embodiment after forming a gate oxide layer in the peripheral region.

Fig. 13 is a cross-sectional view of the memory device of the present embodiment after forming a control gate material layer.

Fig. 14 is a cross-sectional view of the memory device of this embodiment after forming independently separated semi-floating gate transistors.

Fig. 15 is a cross-sectional view of a memory device of this embodiment in which a U-channel device is formed.

Fig. 16 is a cross-sectional view of a memory device of this embodiment in which a planar channel device is formed.

Fig. 17 is a schematic diagram of another method for manufacturing a memory device according to the present embodiment after forming an original layer of floating gate material;

Fig. 18 is a schematic diagram of a method for manufacturing a memory device according to another embodiment after forming a floating gate material layer;

Fig. 19 is a schematic view of another method for manufacturing a memory device according to the present embodiment after forming a bump-like body;

Fig. 20 is a cross-sectional view of a U-channel device formed by another method of fabricating a memory device according to this embodiment.

Fig. 21 is a cross-sectional view of another method of fabricating a memory device of this embodiment to form a planar channel device.

Reference numerals illustrate:

A 20-semi-floating gate transistor; 200-substrate; 200 a-a first contact window; 200 b-a second contact window; 201-a common source; 203-a first drain; 204-a second drain; 205-doped region; 211 a-a first insulating layer; 211 b-a second insulating layer; 211-a gate insulating layer; 213-a bottom antireflective layer; 215-photoresistance;

220-first semi-floating gate; 221 a-a floating gate material original layer; 221 b-a layer of floating gate material; 230-an inter-gate dielectric layer; 231-silicon oxide layer; 232-a silicon nitride layer; 235-gate oxide; 240-a first control gate; 241-a layer of control gate material; 30-a first trench; 40-a second trench; 300-a first gate stack; 400-a second gate stack; SP-side wall; i-a common source region; II-a first drain region; III-a second drain region;

A V-source region; IV-drain region; 200 c-contact window; 271-an original layer of floating gate material; 260-an inter-gate dielectric layer; 261-a silicon oxide layer; 262-a silicon nitride layer; 263-source; 264-drain; 270-a layer of floating gate material; 281-a control gate material layer; 280-control gate.

Detailed Description

The method of fabricating the memory device of the present invention is described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be understood that the drawings in the specification are in a very simplified form and are all to a non-precise scale, simply to facilitate a clear and thorough description of the embodiments of the invention.

It should be noted that the terms "first," "second," and the like, are used hereinafter to distinguish between similar elements and are not necessarily used to describe a particular order or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if a method described herein comprises a series of steps, and the order of the steps presented herein is not necessarily the only order in which the steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the structure in the figures is inverted or otherwise oriented (e.g., rotated), the exemplary term "on … …" may also include "under … …" and other orientations.

The manufacturing method of the memory device of the present embodiment, as shown in fig. 2, includes the following steps:

S1, providing a substrate, wherein the substrate comprises a storage unit area, and a common source area, a first drain area and a second drain area which are positioned at two sides of the common source area are preset at one side of the upper surface of the substrate of the storage unit area;

s2, forming a gate insulating layer on the substrate of the memory cell region, wherein a first contact window and a second contact window exposing the substrate are formed in the gate insulating layer, the first contact window is positioned between the common source region and the first drain region, and the second contact window is positioned between the common source region and the second drain region;

s3, forming a semi-floating gate material layer, wherein the semi-floating gate material layer covers the substrate exposed by the first contact window and the second contact window and also covers the gate insulation layer positioned between the first contact window and the second contact window; the semi-floating gate material layer is made of polysilicon;

S4, performing a heat treatment process to convert the material of the semi-floating gate material layer with partial thickness above the first contact window and the second contact window from polycrystalline silicon to monocrystalline silicon; the transformed regions are defined as asperities.

The memory device and the method for manufacturing the same according to the present embodiment are described in detail below with reference to fig. 3a to 16.

Fig. 15 is a schematic cross-sectional structure of a memory device of a U-shaped channel manufactured by the manufacturing method of the present embodiment. Fig. 16 is a schematic cross-sectional structure of a memory device with a planar channel manufactured by the manufacturing method of the present embodiment. Referring to fig. 15 and 16, the memory device may include at least one semi-floating gate transistor, and may further include other types of memory elements, logic elements, and the like. In one embodiment, the memory device includes two adjacent semi-floating gate transistors having different drain regions and sharing the same source region, which is beneficial to reducing the area occupied by all the semi-floating gate transistors on the substrate and improving the integration density of the memory device. In this embodiment, the structures of two adjacent semi-floating gate transistors are symmetrical.

The present embodiment specifically describes the fabrication of a memory device including two half-floating gate transistors sharing a source region. The two half floating gate transistors sharing the source region are respectively referred to as a first half floating gate transistor and a second half floating gate transistor, which are formed by the same process.

As shown in fig. 3a and 3b, a substrate 200 is provided, which is provided with a common source region i in advance on a side near an upper surface thereof, and a first drain region ii and a second drain region iii on both sides of the common source region. The location of the common source region used to form the first and second half-floating gate transistors is referred to as the common source region i, the first drain region ii is used to form the drain region of the first half-floating gate transistor, the second drain region iii is used to form the drain region of the second half-floating gate transistor, the half-floating gate in the subsequently formed first half-floating gate transistor is referred to as the first half-floating gate, and the half-floating gate in the subsequently formed second half-floating gate transistor is referred to as the second half-floating gate. The substrate 200 is, for example, monocrystalline silicon, polycrystalline silicon, or silicon-on-insulator. The substrate 200 may be entirely of the second doping type or formed with a well region of the second doping type. Optionally, a well region (e.g., P-well) of the second doping type is formed in the substrate 200, and a doped region 205 of the first doping type is formed in the well region and extends from the inside to the upper surface of the substrate 200, and the source and drain regions of the semi-floating gate transistor are formed on top of the doped region 205. The first insulating layer 211a is formed on the upper surface of the substrate 200.

The memory device of this embodiment may have both a trench corresponding to a U-channel memory device and a non-trench corresponding to a planar channel memory device. Figure 3a shows a grooved situation. A first trench 30 is formed in the substrate between the common source region i and the first drain region ii, and a second trench 40 is formed in the substrate between the common source region i and the second drain region iii. The first trench 30 and the second trench 40 may be formed by depositing a hard mask on the surface of the substrate 200 and by photolithography and etching processes. The first trench 30 and the second trench 40 are formed by etching the insulating layer 211a and the substrate 200 having a partial thickness. The first trench 30 and the second trench 40 have a depth of aboutIn this embodiment, the depth of the first trench 30 and the depth of the second trench 40 are both greater than the depth of the doped region 205, that is, based on the upper surface f1 of the substrate 200, the bottom surface of the first trench 30 and the bottom surface of the second trench 40 are further away from the upper surface f1 of the substrate than the bottom of the doped region 205.

With continued reference to fig. 3a and 3b, a first direction (e.g., X-direction) and a second direction (e.g., Y-direction) perpendicular to each other are defined in a plane parallel to the substrate 200, and a direction perpendicular to the plane of the substrate 200 is defined as a Z-direction (device thickness direction). The substrate 200 may have isolation structures (e.g., shallow trench isolation, STI) and active areas AA formed thereon. The shallow trench isolation STI and the active area AA may be alternately arranged along the first direction (e.g., X direction). The first drain region ii, the first trench 30, the common source region i, the second trench 40, and the second drain region iii are sequentially distributed along the second direction (e.g., Y direction). In addition, it is believed that the well implant, other ion implant, and anneal steps are completed in the substrate 200, with the well region of the second doping type (e.g., a P-well in this embodiment) already formed in the substrate 200 and the doped region 205 extending from within the well region to the upper surface of the substrate 200.

As shown in fig. 4 and 5, a second insulating layer 211b is formed to cover at least the first trench 30 and the second trench 40. The first insulating layer 211a may be removed before the second insulating layer 211b is deposited. The second insulating layer 211b may also cover the first insulating layer 211a located on the upper surface of the substrate, for example. The first insulating layer 211a and/or the second insulating layer 211b located on the upper surface of the substrate serves as a gate insulating layer 211. The gate insulating layer 211 is used to isolate the substrate 200 from a floating gate material layer 221 formed later, and the gate insulating layer 211 covering the upper surface of the substrate can also act as an etching stop when patterning the floating gate material layer 221. The material of the gate insulating layer 211 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may be formed by thermal oxidation, chemical Vapor Deposition (CVD), atomic layer deposition, or the like.

And etching the gate insulating layer to form a first contact window and a second contact window. As shown in fig. 5, a bottom antireflective layer (BARC) 213 and a patterned photoresist 215 are formed. A bottom anti-reflective layer (BARC) 213 fills the first trench 30 and the second trench 40 and forms a thickness over the substrate covering the gate insulation layer 211. A patterned photoresist 215 is located on the top surface of the bottom antireflective layer (BARC) 213. The patterned photoresist 215 has openings corresponding to the first contact window and the second contact window.

As shown in fig. 5 and 6, the bottom anti-reflection layer 213 and the lower gate insulating layer 211 are sequentially dry etched using the patterned photoresist 215 as a mask, exposing the substrate 200, forming a first contact window 200a and a second contact window 200b. The dry etching process is controllable, and the first contact window 200a and the second contact window 200b can be precisely formed. Specifically, the first contact window 200a is located between the first drain region ii and the first trench 30, and the second contact window 200b is located between the second drain region iii and the second trench 40. The patterned photoresist 215, bottom anti-reflective coating (BARC) 213 are finally removed. The lithography and etching process can prevent the mask material composed of the bottom anti-reflective layer (BARC) 213 and the photoresist 215 from collapsing while ensuring protection of the pattern to be preserved.

As shown in fig. 7, a floating gate material original layer 221a (original state) is formed on the substrate 200, the floating gate material original layer 221a covering the gate insulating layer 211 and the upper surface of the substrate 200 exposed by the first contact window 200a and the second contact window 200 b. The floating gate material original layer 221a of the present embodiment fills the first trench 30 and the second trench 40 described above, for example. In some embodiments, the first trench and the second trench are not formed on the substrate, and the original layer 221a of floating gate material is located over the substrate. The floating gate material original layer 221a is used to form the half floating gates of the first half floating gate transistor and the second half floating gate transistor. The floating gate material original layer 221a has a second doping type. In this embodiment, the floating gate material of the floating gate material primitive layer 221a is, for example, p-type doped polysilicon, wherein p-type dopant can be introduced by doping gas during the deposition process or by ion implantation after the deposition of polysilicon. Illustratively, the polysilicon may be deposited to a thickness by a CVD process, then p-type ion implantation and annealing followed by Chemical Mechanical Polishing (CMP) to planarize the upper surface of the polysilicon to a desired thickness, e.g., to a thickness of about the original layer 221a of floating gate material above the upper surface of the substrate 200

As shown in fig. 8, the floating gate material original layer 221a is etched to remove a region of the floating gate material original layer 221a between the first contact window 200a and the first drain region ii and a region between the second contact window 200b and the second drain region iii. The remaining original layer of gate material, referred to as a semi-floating gate material layer 221b (intermediate state), the semi-floating gate material layer 221b covers the substrate 200 exposed by the first contact window 200a and the second contact window 200b and also covers the gate insulation layer 211 located between the first contact window 200a and the second contact window 200 b; the semi-floating gate material layer 221b is made of polysilicon. The boundary of the semi-floating gate material layer 221b near the first drain region ii falls within the range of the first contact window 200a, and the boundary of the semi-floating gate material layer 221 near the second drain region iii falls within the range of the second contact window 200 b. Preferably, the sides of the semi-floating gate material layer 221b and the second contact window 200b adjacent to the second drain region iii are close to or aligned, and the sides of the semi-floating gate material layer 221 and the first contact window 200a adjacent to the first drain region ii are close to or aligned. The floating gate material original layer 221a may be etched using a dry or wet etch to form the semi-floating gate material layer 221b.

It should be appreciated that if the gate insulating layer 211 between the contact window and the drain region is not left when the contact window is formed, there is no etching stop layer when the floating gate material original layer 221a is etched, and the etching selectivity between the floating gate material original layer 221a (for example, polysilicon material) and the substrate 200 (for example, silicon material) is low, so that serious substrate damage is caused, which further affects the performance of the semi-floating gate transistor. In this embodiment, when the floating gate material original layer 221a is etched, the gate insulating layer 211 located between the first drain region ii and the first contact window 200a and between the second drain region iii and the second contact window 200b may be used as an etching barrier layer, so as to avoid damaging the surface of the substrate 200 during the etching process. Preferably, the floating gate material original layer 221a may be etched using a dry etching mode of "End PT) +over Etch (Over Etch)" to ensure that the semi-floating gate material within the removal range is removed cleanly.

As shown in fig. 9, an inter-gate dielectric layer 230 is formed, and the inter-gate dielectric layer 230 covers at least the upper surface and the side surfaces of the semi-floating gate material layer 221 b. Optionally, the upper surface of the gate insulating layer 211 between the first contact window 200a and the first drain region ii may be further covered, and the upper surface of the gate insulating layer 211 between the second contact window 200b and the second drain region iii may be further covered. The material of the inter-gate dielectric layer 230 may be silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials, and the inter-gate dielectric layer 230 may have a single-layer structure or a multi-layer structure with more than two layers (for example, an ONO structure). Illustratively, the inter-gate dielectric layer 230 includes a stacked silicon oxide layer 231 and silicon nitride layer 232 (i.e., an ON structure).

As shown in fig. 9 and 10, a heat treatment process is performed to convert the material of the semi-floating gate material layer 221b of a partial thickness located above the first contact window 200a and the second contact window 200b from the polycrystalline silicon to single crystal silicon; the transformed region is defined as the asperity T2. Ions of a first doping type (e.g., N-type) of the doped region 205 in the substrate 200 diffuse into the polysilicon of the semi-floating gate material layer 221b under the effect of the high temperature of the heat treatment, ions of a second doping type (e.g., P-type) in the polysilicon of the semi-floating gate material layer 221b, and the diffusion forms a PN junction. The temperature range of the heat treatment is 1000-1200 ℃.

The thermal treatment process may include a thermal oxidation process, for example, a thermal oxidation process during formation of a gate oxide layer that doubles as a peripheral region. The heat treatment process is not limited to only the thermal oxidation process, or may include a high temperature anneal or other high temperature treatment process. The thermal oxidation process in the formation of the gate oxide layer, which also serves as a peripheral region, converts the material of the semi-floating gate material layer 221b, which is located at a portion of the thickness above the first contact window 200a and the second contact window 200b, from the polycrystalline silicon to single crystal silicon.

Referring to fig. 3b, fig. 10 and 11, the memory device of the present embodiment includes a memory cell region C (cell) and a peripheral region P (peripheral). The memory cell regions C (cells) are alternately distributed with shallow trench isolation STI and active regions AA along a first direction (e.g., X direction). The peripheral regions P are also alternately arranged with shallow trench isolation STI and active regions AA along the first direction (e.g., X direction). The peripheral region P includes, for example, various circuits that provide a voltage source, a current source, and a read-write operation.

In the process of forming the inter-gate dielectric layer 230 in the memory cell region C, the inter-gate dielectric layer 230 also covers the peripheral region P. In the memory cell region C, the inter-gate dielectric layer 230 covers at least the upper surface and the side surface of the semi-floating gate material layer 221b, and the inter-gate dielectric layer 230 includes a stacked silicon oxide layer 231 and a silicon nitride layer 232 (i.e., an ON structure). As shown in fig. 11, the shallow trench isolation STI top of the peripheral region P is also consumed with a small thickness during the etching process to remove the inter-gate dielectric layer (not shown) of the peripheral region P. Within the peripheral region P, the substrate surface of the active region AA between adjacent shallow trench isolation STI is exposed.

As shown in fig. 12, the gate oxide layer 235 is formed on the substrate surface of the active area AA of the peripheral area P by thermal oxidation, and in particular, the gate oxide layer 235 may be formed on the substrate surface of the active area AA of the Low Voltage (LV) area and/or the High Voltage (HV) area of the peripheral area P.

Specifically, the gate oxide layer 235 is formed using a thermal oxidation process, which may employ an In-situ steam oxidation (In-Situ Steam Generation, ISSG) method or a Rapid Thermal Oxidation (RTO) method. An In-situ steam oxidation process (In-Situ Steam Generation, ISSG) may be used to grow a gate oxide, such as silicon oxide, on the substrate surface of the active region AA. The in-situ steam oxidation (ISSG) step comprises an N ₂ O in-situ steam oxidation step, wherein the reaction gases are N ₂ O and H ₂, or an O ₂ in-situ steam oxidation step, and the reaction gases are O ₂ and H ₂; the temperature range of the in-situ steam oxidation method is 1000-1200 ℃. The Rapid Thermal Oxidation (RTO) is performed at a reaction temperature ranging from 1000 ℃ to 1200 ℃ for example, and oxygen and hydrogen are introduced to form the gate oxide layer 235. Rapid Thermal Oxidation (RTO) growth of the gate oxide 235 reduces the growth time and reduces the required thermal budget.

Preferably, after the thermal oxidation process is performed, nitrogen may be doped into the gate oxide layer by a plasma nitridation process, so that part of oxygen atoms in the gate oxide layer are replaced by nitrogen atoms to form si—n bonds, so that the gate oxide layer is adjusted to have a certain nitrogen concentration, for example, silicon oxynitride, so that the dielectric constant of the gate oxide layer can be improved.

The plasma nitridation process includes any of decoupled plasma nitridation (Decoupled Plasma Nitridation, DPN), remote Plasma Nitridation (RPN), or nitridation of N ₂ of a vertical diffusion device. N ₂ dissociates into N ions at high temperatures, thereby nitriding the oxide layer. The process conditions of the decoupled plasma nitrogen treatment process are, for example: the plasma treatment power is 300W-600W; the plasma treatment pressure is 10 mTorr-30 mTorr, the plasma treatment gas is N ₂ and He, wherein the flow rate of N ₂ is 50 sccm-120 sccm, and the flow rate of He is 80 sccm-150 sccm.

The plasma damage in the N-doped and repair medium is stabilized by a high temperature anneal process (Post Nitridation Anneal, PNA) to form the gate oxide layer 235 that has improved gate oxide interface states. The Si-H bond and the S-O-H bond generated in the process of growing the gate oxide layer by the ISSG thermal oxidation method are repaired mainly by a PNA high-temperature annealing process, and fracture bonds occur near the Si-SiO interface. The high temperature annealing process is carried out at a temperature ranging from 1000 ℃ to 1100 ℃ for a reaction time ranging from 5sec to 120sec.

In the process of forming the gate oxide layer 235 in this embodiment, a real-time high-temperature nitridation process is introduced after the SiO gate oxide layer is formed by thermal oxidation, so as to reduce the number of Si-H bonds and S-O-H bonds generated at the Si-SiO interface, promote stress release of the internal structure of the oxide film, reduce the possibility of breaking bonds near the interface, and simultaneously introduce a proper amount of oxidizing gas to eliminate the damage defect caused by pure nitridation treatment on the gate dielectric layer, effectively reduce the total interface state charge of the gate oxide film by one order of magnitude or more, and effectively eliminate the gate oxide damage defect.

The memory cell region C is also transferred from the contact window, where the polycrystalline silicon is in contact with the single crystal silicon, under the thermal oxidation high temperature in the gate oxide layer formation process of the peripheral region P, and the polycrystalline is recrystallized along the crystal direction of the single crystal at the high temperature, which is represented by the transformation of the polycrystalline into the single crystal, and the recrystallization is extended upward by a certain thickness under the continuous thermal oxidation high temperature, so that the polycrystalline silicon of the semi-floating gate material layer 221b of a partial thickness located above the first contact window 200a and the second contact window 200b is melted into a molten state, and in the molten state, the polycrystalline silicon is transformed into a small crystal grain state, and the small crystal grains (crystal nuclei) are recrystallized to form the single crystal silicon with the same crystal face orientation.

In this embodiment, the region where the polycrystal is converted into the single crystal is not particularly required, as long as the contact window is ensured to be single crystal silicon, and the topography of the convex body T1 formed by etching the substrate is not necessarily required. The converted region is defined as a quasi-bulge T2, namely the material of the quasi-bulge T2 region is converted from polycrystalline silicon to monocrystalline silicon, and a PN junction is formed in the quasi-bulge T2 region.

The thermal oxidation process in this embodiment includes growing a gate oxide layer on the surface of the substrate in the active region of the peripheral region, and converting the material of the semi-floating gate material layer with a partial thickness above the contact window from the polysilicon to monocrystalline silicon by utilizing the thermal oxidation of the grown gate oxide layer in the peripheral region; no extra thermal oxidation step is added, two purposes are achieved, and the process cost is saved.

As shown in fig. 13, a control gate material layer 241 is formed, the control gate material layer 241 covering the inter-gate dielectric layer 230. The control gate material layer 241 is used to form the control gates of the first and second semi-floating gate transistors. A certain thickness of polysilicon may be deposited by CVD or the like and planarized to a desired thickness to provide the control gate material layer 241. The control gate material layer 241 may be polysilicon of the first doping type, and in this embodiment, the control gate material layer 241 is doped n-type, for example.

As shown in fig. 13 and 14, the control gate material layer 241, the inter-gate dielectric layer 230, and the semi-floating gate material layer 221b are etched to form independently separated semi-floating gate transistors.

Specifically, the control gate material layer 241, the inter-gate dielectric layer 230 and the semi-floating gate material layer 221b of the common source region i are etched, and the control gate material layers 241 of the first drain region ii and the second drain region iii are etched; the remaining portions of the control gate material layer 241, the inter-gate dielectric layer 230, and the semi-floating gate material layer 221b between the first drain region ii and the common source region i constitute a first gate stack 300, and the portion between the second drain region iii and the common source region i constitutes a second gate stack 400.

The first gate stack 300 is located between the first drain region ii and the common source region i for forming a first semi-floating gate transistor. The first gate stack 300 includes a first half floating gate 220 resulting from etching the half floating gate material layer 221b, a first control gate 240 resulting from etching the control gate material layer 241, and a first inter-gate dielectric layer resulting from etching the inter-gate dielectric layer 230. The second gate stack 400 is located between the second drain region iii and the common source region i, and is used for forming a second semi-floating gate transistor, where the second gate stack 400 includes a second semi-floating gate obtained by etching the semi-floating gate material layer 221b, a second control gate obtained by etching the control gate material layer 241, and a second inter-gate dielectric layer obtained by etching the inter-gate dielectric layer 230. The first gate stack 300 and the second gate stack 400 described above may be formed using photolithography and an anisotropic dry etching process. In the dry etching process, in order to avoid damage to the substrate 200 of the first and second drain regions ii and iii, the gate insulating layer 211 of the region may be incompletely removed by adjusting etching conditions. The gate insulating layer 211 of the common source region i is exposed.

As shown in fig. 15, forming a side wall SP of the semi-floating gate; specifically, a sidewall SP is formed on the sidewalls of the first gate stack 300 and the second gate stack 400, and ion implantation and annealing are performed to form a common source 201 in the substrate 200 corresponding to the common source region i, a first drain 203 in the substrate 200 corresponding to the first drain ii, and a second drain 204 in the substrate 200 corresponding to the second drain iii.

Specifically, a dielectric material may be conformally deposited, and then anisotropically dry etched to remove the dielectric material covering the upper surfaces of the first control gate and the second control gate and the upper surface of the semiconductor, and the dielectric material covering the sides of the first gate stack 300 and the second gate stack 400 may be left as a sidewall. The sidewall covered on the drain region side of the first gate stack 300 covers the side of the first control gate, the sidewall covered on the common source region side of the first gate stack 300 covers the side of the first control gate, the first inter-gate dielectric layer and the first half floating gate, that is, in the first half floating gate transistor, the side surface of the first half floating gate facing the source region is covered by the sidewall to be isolated from the outside on the side facing the source region, and the second half floating gate in the second half floating gate transistor is identical. In this embodiment, when ion implantation and annealing are performed to form the common source, the first drain and the second drain, the ion implantation is, for example, n-type implantation.

Through the above steps, the first half floating gate transistor and the second half floating gate transistor are formed on the substrate 200.

Fig. 16 is a schematic cross-sectional view showing a trench-free memory device manufactured by the manufacturing method of the present embodiment. Fig. 16 is different from fig. 15 in that the first half floating gate 220 is formed only on the upper surface of the substrate 220, not in the trench; the corresponding gate insulating layer 211 is formed only on the upper surface of the substrate 220, and does not cover the surface of the trench.

The steps of another method for manufacturing a memory device are described in detail below with reference to fig. 17 through 21. The present embodiment specifically describes the fabrication of a memory device of a single semi-floating gate transistor.

A method of fabricating a memory device, comprising:

Specifically, as shown in fig. 17, a substrate 200 is provided, the upper surface side of which is provided with a source region V and a drain region IV in advance. The memory device of this embodiment may have both a trench corresponding to a U-channel memory device and a non-trench corresponding to a planar channel memory device. Fig. 17 illustrates a grooved U-channel memory device. A gate insulating layer 211 is formed on the substrate 200, and a contact window 200c exposing the substrate 200 is formed in the gate insulating layer 211, the contact window 200c being close to the drain region IV side.

A floating gate material original layer 271 covering the substrate 200 and the gate insulating layer 211 is formed between the source region V and the drain region IV.

As shown in fig. 18, the floating gate material original layer 271 is etched to remove a partial region of the floating gate material original layer 271 located at one side of the source region V and a region located between the contact window 200c and the drain region IV; the original layer of floating gate material remaining after etching serves as the semi-floating gate material layer 270 of the semi-floating gate transistor, also being the final semi-floating gate. A layer 270 of semi-floating gate material covers the substrate 200 exposed by the contact window 200c and also covers the gate insulation layer 211 between the contact window 200c and the source region V; the semi-floating gate material layer 270 is made of polysilicon.

As shown in fig. 19, a heat treatment process is performed to convert the material of the semi-floating gate material layer 270 with a partial thickness above the contact window from the polycrystalline silicon to monocrystalline silicon; the transformed region is defined as the asperity T3. The heat treatment forming process of the quasi-convex body T3 is the same as that of the quasi-convex body T2, and the morphology is the same, and the description is omitted.

An inter-gate dielectric layer 260 and a control gate material layer 281 are formed, the inter-gate dielectric layer 260 covers the upper surface of the semi-floating gate material layer 270 and the side surface facing the drain region, and the control gate material layer 281 covers the inter-gate dielectric layer 260. The control gate material layer 281 is used for the control gate of the semi-floating gate transistor. The inter-gate dielectric layer 260 may have a single layer structure or a multi-layer structure (e.g., ONO structure) with two or more layers. Illustratively, the inter-gate dielectric layer 260 includes a stacked silicon oxide layer 261 and silicon nitride layer 262 (i.e., an ON structure).

As shown in fig. 19 and 20, the control gate material layer 281 and the inter-gate dielectric layer 260 are etched. Etching the control gate material layer 281 of the source region V and the drain region IV, and further etching to remove the inter-gate dielectric layer 260 on the sidewall of the semi-floating gate material layer 270 near the source region V; the remaining control gate material layer 281 serves as the control gate 280 of the semi-floating gate transistor. In the dry etching process, in order to avoid damage to the substrate 200 of the source region V and the drain region IV, the gate insulating layer 211 of the region may be incompletely removed by adjusting etching conditions, that is, after etching is completed, the gate insulating layer 211 may remain on the substrate 200 of the source region V and the drain region IV to a certain thickness.

Forming a semi-floating gate side wall SP; specifically, the semi-floating gate, the inter-gate dielectric layer 260 and the control gate 280 form a gate stack, a sidewall SP is formed on a sidewall of the gate stack, and ion implantation and annealing are performed to form a source 263 in the substrate 200 corresponding to the source region V, and a drain 264 in the substrate 200 corresponding to the drain region IV.

Fig. 21 is a schematic cross-sectional view showing a trench-free memory device manufactured by the manufacturing method of the present embodiment. Unlike fig. 20, the semi-floating gate 270 is formed only on the upper surface of the substrate 220, not in the trench; the corresponding gate insulating layer 211 is formed only on the upper surface of the substrate 220, and does not cover the surface of the trench.

The invention also provides a memory device manufactured by the manufacturing method, as shown in fig. 15-16 and 20-21, the memory device comprises:

Specifically, the memory device includes a semi-floating gate transistor; the semi-floating gate transistor includes: the drain region, the source region, the quasi-convex body positioned above the contact window, the semi-floating gate, the inter-gate dielectric layer and the control gate.

The substrate comprises:

The well region is doped with ions of a second doping type; and

A doped region extending from inside the well region to an upper surface of the substrate, the doped region being doped with ions of a first doping type; the source region and the drain region are both formed on top of the doped region.

The substrate also comprises a peripheral region, wherein an active region is distributed in the peripheral region, and a gate oxide layer grows on the surface of the substrate in the active region.

A memory of this embodiment (as shown in fig. 15 and 16) includes two adjacent semi-floating gate transistors having different drain regions and sharing the same source region; the two adjacent semi-floating gate transistors which share the source region are used as first repeating units, and the wafer for manufacturing the memory comprises a plurality of first repeating units which are arranged in a copying mode. The arrangement is beneficial to reducing the occupied area of all the semi-floating gate transistors on the substrate and improving the integration density of the memory device. In this embodiment, the structures of two adjacent semi-floating gate transistors are symmetrical.

Another memory of this embodiment (as shown in fig. 20 and 21) is manufactured by using a single semi-floating gate transistor as a second repeating unit, and the wafer of the memory includes a plurality of second repeating units arranged in a duplication manner.

A memory of the present embodiment is described in detail below with reference to fig. 10 to 16.

As shown in fig. 10 and 11, a memory of the present embodiment includes:

a substrate 200, which comprises a memory cell area C, wherein a common source area I, a first drain area II and a second drain area III which are positioned at two sides of the common source area I are pre-arranged at one side of the upper surface of the substrate of the memory cell area C;

A gate insulating layer 211 is formed on the substrate of the memory cell region C, a first contact window exposing the substrate 200 and a second contact window are formed in the gate insulating layer 211, the first contact window is located between the common source region i and the first drain region ii, and the second contact window is located between the common source region i and the second drain region iii;

A layer of semi-floating gate material 211b, said layer of semi-floating gate material 211b covering said substrate 200 exposed by said first contact window and said second contact window and also covering said gate insulation layer 211 between said first contact window and said second contact window; the semi-floating gate material layer 211b is made of polysilicon;

And a quasi-convex body T2, wherein the quasi-convex body T2 is positioned in the semi-floating gate material layer 221b with partial thickness above the first contact window and the second contact window, and the quasi-convex body T2 is made of monocrystalline silicon converted from polycrystalline silicon.

Specifically, the substrate includes: the well region is doped with ions of a second doping type; and a doped region 205, the doped region 205 extending from inside the well region to the upper surface of the substrate 200, the doped region 205 being doped with ions of a first doping type; the common source region I and the first drain region II and the second drain region III are formed on top of the doped region 205.

The memory device further comprises a first trench 30 and a second trench 40, the first trench 30 being located in the substrate between the common source region I and the first drain region II; the second trench 40 is located in the substrate between the common source region I and the second drain region III; the first contact window is located between the first drain region II and the first trench 30, and the second contact window is located between the second drain region III and the second trench 40. The gate insulating layer 211 also covers inner surfaces of the first trench 30 and the second trench 40, and the floating gate material layer 211b covers the gate insulating layer 211 and fills the first trench 30 and the second trench 40.

As shown in fig. 12, the substrate further includes a peripheral region P, where an active region AA is distributed in the peripheral region P, and a gate oxide layer 235 is grown on the surface of the substrate in the active region AA.

As shown in fig. 14 and 15, the memory device includes adjacent first and second semi-floating gate transistors; the first half floating gate transistor includes: the first drain region II, the protrusion-like body T2 located above the first contact window, the first half floating gate 220, the first inter-gate dielectric layer 230, and the first control gate 240. The second semi-floating gate transistor is symmetrical to the first semi-floating gate transistor. The second semi-floating gate transistor includes: the second drain region, the quasi-convex body positioned above the second contact window, the second semi-floating gate, the second inter-gate dielectric layer and the second control gate. As shown in fig. 13, the semi-floating gate material layer 221b removes a portion located above the common source region I, and the remaining portions located at two sides of the common source region I are the first semi-floating gate 220 and the second semi-floating gate, respectively.

In the semi-floating gate transistor 20 according to the embodiment of the present invention, the first semi-floating gate 220 is used as a charge storage layer, and the ions of the first doping type of the doped region 205 in the quasi-protrusion T2 region diffuse from the first contact window into the first semi-floating gate 220 and form a PN junction. In the first half floating gate transistor, the first half floating gate 220, the protrusion-like body T2 located above the first contact window, the first drain region II, the first inter-gate dielectric layer 230 and the first control gate 240 form a vertical tunneling field effect transistor using the control gate as a gate, the protrusion-like body T2 located above the first contact window is used as a channel of the vertical tunneling field effect transistor to connect the first half floating gate 220 and the first drain region II, and the first control gate 240 regulates and controls on and off of current in the vertical tunneling field effect transistor through an electric field. The second semi-floating gate transistor operates in the same manner as the first semi-floating gate transistor.

Referring to fig. 15, the memory device includes a semi-floating gate transistor 20, the semi-floating gate transistor 20 includes a substrate 200, a common source 201 and a first drain 203 of a first doping type are formed on top of the substrate 200, and a surface of the substrate 200 between the common source 201 and the first drain 203 is provided with a first contact window of the semi-floating gate. The semi-floating gate transistor 20 further includes a dummy body T2, a first semi-floating gate 220, an inter-gate dielectric layer 230, and a control gate 240 formed on the substrate 200 between the common source 201 and the first drain 203. The first half floating gate 220 has a second doping type opposite to the first doping type; the quasi-protrusion T2 is located in the first half floating gate 220 with a partial thickness above the first contact window, and the inter-gate dielectric layer 230 covers the upper surface of the first half floating gate 220 and the side surface of the floating gate 220 near the side of the first drain 203. Control gate 240 is located on inter-gate dielectric layer 230.

The semi-floating gate transistor may be an n-type device or a p-type device depending on the type of charge transferred. The semi-floating gate transistor of this embodiment is, for example, an n-type device, and the first doping type is n-type, and the second doping type is p-type. It will be appreciated that the p-type device may be obtained by n-type and p-type interchange of doped conductivity types of the device. The n-type dopant is, for example, phosphorus or arsenic, and the p-type dopant is, for example, boron or indium.

The semi-floating gate transistor (SFGT) of the embodiment of the invention adopts TFET as a channel for charge injection or release of the first semi-floating gate and the drain region in the semi-floating gate device. The SFGT controls the on-off state of the TFET through a control gate 240 that is overlaid outside the sidewall of the asperity T2 (the sidewall that faces the drain region). Taking N-type SFGT as an example, the source region and the drain region of SFGT are both N-type doped, the polysilicon of the semi-floating gate is p-type doped, and a quasi-convex body T2 between the source region and the drain region is used as a channel of the TFET. When a negative bias is applied to the control gate and a positive bias is applied to the drain region, the surfaces of the quasi-convex body T2 and the gate dielectric layer enter an accumulation state, a large number of holes are accumulated on the surfaces, and a PN junction which is in tunneling between the quasi-convex body T2 and the high-concentration electrons of the drain region is formed, so that the vertical TFET is started, electrons tunnel from the quasi-convex body T2 to the drain region, and the number of positive charges in the semi-floating gate is increased, namely logic '1' is written; when the control gate is forward biased and the drain region is reverse biased, the diode formed by the quasi-convex body T2 and the drain region enters a forward biased state, carriers in the semi-floating gate are released through the quasi-convex body T2, and the quantity of stored charges is reduced, namely logic '0' is written.

The floating gate is charged or discharged through the vertical tunneling field effect transistor, and the vertical tunneling field effect transistor has the advantages of higher chip integration density, stronger data holding capacity and faster data reading speed.

Another memory of the present embodiment is described in detail below with reference to fig. 20 and 21.

As shown in fig. 20 and 21, another memory includes:

a substrate 200, which comprises a memory cell region, wherein a source region V and a drain region IV are preset on one side of the upper surface of the substrate in the memory cell region;

A gate insulating layer 211 is formed on the substrate of the memory cell region, a contact window 200c exposing the substrate is formed in the gate insulating layer 211, and the contact window 200c is close to one side of the drain region IV;

a layer of semi-floating gate material 270, said layer of semi-floating gate material 270 covering said substrate 200 exposed by said contact window 200c and also covering said gate insulation layer 211 between said contact window 200c and said source region V; the semi-floating gate material layer 270 is made of polysilicon;

A quasi-convex body T3, wherein the quasi-convex body T3 is positioned right above the contact window 200c

In the semi-floating gate material layer 270 with a partial thickness above, the material of the quasi-protrusion T3 is monocrystalline silicon converted from the polycrystalline silicon.

The memory device includes a semi-floating gate transistor; the semi-floating gate transistor includes: the drain region, the asperities T3 above the contact window, the semi-floating gate, the inter-gate dielectric layer 260 and the control gate 280.

The memory device of fig. 15 obtained by dicing (bisecting) the common source electrode 201 is identical to the memory device of fig. 20, and therefore the structure and operation principle of the device of fig. 20 are described above with reference to the device of fig. 15, and are not repeated here.

In the prior art memory device (fig. 1a and 1 b), the asperities T1 are part of the substrate 11, and the semi-floating gate (polysilicon layer 15) and the asperities T1 are stacked together in different units. The memory of the embodiment forms a quasi-convex body on the body of the semi-floating gate material layer, wherein the quasi-convex body is used as a part of the body of the semi-floating gate material layer, namely, the semi-floating gate material layer and the quasi-convex body are of an integrated structure; the structure of the semi-floating gate and the convex body stacked together for different individuals is different from that of the conventional memory device. The etching step of etching the polysilicon layer and a portion of the thickness of the substrate together to form the asperities in (fig. 1a and 1 b) is omitted. The semi-floating gate transistor failure caused by the fact that the etching selection ratio of the polycrystalline silicon layer to the substrate is small and the etching process precision is difficult to control is avoided.

In summary, the present invention provides a memory device and a method for manufacturing the same, in which a heat treatment process is used to convert a material of a semi-floating gate material layer with a partial thickness above a contact window from polysilicon to monocrystalline silicon; the transformed regions are defined as asperities. The invention develops a new way, adopts a heat treatment method to form the quasi-convex body, and avoids the failure of the semi-floating gate transistor caused by the fact that the etching selection ratio of the polysilicon layer to the substrate is very small and the etching process precision is difficult to control in the conventional process of forming the convex body by etching. The semi-floating gate material layer and the drain region are connected through the quasi-convex body, and the area of a leakage path is only the physical width of the quasi-convex body which can be accurately controlled; the built-in barrier in the quasi-convex body can prevent the diffusion of carriers between the semi-floating gate material layer and the drain region in a non-working state. Therefore, leakage of stored charges in the semi-floating gate is greatly reduced, and the stability of stored information is improved.

In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since the device corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.

The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.

Claims

1. A method of fabricating a memory device, comprising:

Forming a gate insulating layer on the substrate of the memory cell region, wherein a first contact window and a second contact window exposing the upper surface of the substrate are formed in the gate insulating layer, the first contact window is positioned between the common source region and the first drain region, and the second contact window is positioned between the common source region and the second drain region;

Performing a heat treatment process to convert the material of the semi-floating gate material layer with partial thickness above the first contact window and the second contact window from polysilicon to monocrystalline silicon; the transformed regions are defined as asperities, which are in contact with the substrate.

2. The method of manufacturing a memory device according to claim 1, wherein the temperature of the heat treatment is in a range of 1000 ℃ to 1200 ℃.

3. The method of fabricating a memory device of claim 1, wherein the substrate further comprises a peripheral region, the peripheral region having an active region distributed therein; the heat treatment process comprises a thermal oxidation process, and a gate oxide layer is grown on the surface of the substrate of the active region of the peripheral region.

4. The method of fabricating a memory device of claim 3, further comprising, after performing the thermal oxidation process:

5. The method of manufacturing a memory device according to claim 1, wherein,

Providing the substrate comprises: doping ions of a second doping type in the substrate to form a well region; doping ions of a first doping type in the well region to form a doped region, wherein the doped region extends from the interior of the well region to the upper surface of the substrate, and the common source region, the first drain region and the second drain region are formed on the top of the doped region;

6. The method of manufacturing a memory device according to claim 1, further comprising forming a first trench in the substrate between the common source region and the first drain region and forming a second trench in the substrate between the common source region and the second drain region before forming the gate insulating layer; the first contact window is located between the first drain region and the first trench, and the second contact window is located between the second drain region and the second trench.

7. The method of manufacturing a memory device of claim 6, wherein after forming the gate insulating layer and the floating gate material layer, the gate insulating layer further covers inner surfaces of the first trench and the second trench, and the floating gate material layer covers the gate insulating layer and fills the first trench and the second trench.

8. The method of manufacturing a memory device according to any one of claims 1 to 7, wherein after forming the semi-floating gate material layer, before performing a heat treatment process, further comprising:

9. The method of manufacturing a memory device of claim 8, further comprising, after performing the heat treatment process:

10. A method of fabricating a memory device, comprising:

Forming a gate insulating layer on the substrate of the memory cell region, wherein a contact window exposing the upper surface of the substrate is formed in the gate insulating layer, and the contact window is close to one side of the drain region;

performing a heat treatment process to convert the material of the semi-floating gate material layer with partial thickness above the contact window from polysilicon to monocrystalline silicon; the transformed regions are defined as asperities, which are in contact with the substrate.

11. The method of fabricating a memory device of claim 10, wherein the substrate further comprises a peripheral region, the peripheral region having an active region distributed therein; the heat treatment process comprises a thermal oxidation process, and a gate oxide layer is grown on the surface of the substrate of the active region of the peripheral region.

12. The method of manufacturing a memory device according to any one of claims 10 to 11, further comprising, after forming the layer of semi-floating gate material, before performing the heat treatment process:

13. The method of manufacturing a memory device of claim 12, further comprising, after performing the heat treatment process:

14. A memory device, comprising:

a gate insulating layer is formed on the substrate of the memory cell region, a contact window exposing the upper surface of the substrate is formed in the gate insulating layer, and the contact window is close to one side of the drain region;

The quasi-convex body is positioned in the semi-floating gate material layer with partial thickness above the contact window, the quasi-convex body is in contact with the substrate, and the quasi-convex body is made of monocrystalline silicon converted from polycrystalline silicon through a heat treatment process.

15. The memory device of claim 14, wherein the memory device comprises a semi-floating gate transistor; the semi-floating gate transistor includes: the source region, the drain region, the quasi-convex body positioned above the contact window, the semi-floating gate, the inter-gate dielectric layer and the control gate.

16. The memory device of claim 15 wherein adjacent two of said semi-floating gate transistors share a source region.

17. The memory device of claim 14, wherein the substrate further comprises a peripheral region, the peripheral region having an active region distributed therein, the substrate surface of the active region having a gate oxide layer grown thereon.