CN114047682B - A Time-to-Digital Converter Based on Fully Differential Ring Oscillator with PVT Robustness - Google Patents

Abstract

The invention discloses a time-to-digital converter with PVT robustness based on a fully differential ring oscillator, and relates to a time-to-digital converter. The uncertainty of the process and the change of PVT robustness seriously restrict the performance of TDC. Contradictions in actual production and application propose this scheme, which is to electrically connect the front-end module, the global control module, the delay unit and the decoding module in sequence; a delay calibration module is also set to connect the delay unit and the decoding module respectively, for delaying the delay unit. For calibration, the delay unit is a fully differential ring oscillator module. The advantage is that high accuracy and dynamic range can be achieved at the same time, and the PVT robustness tolerance and linearity of the TDC can be improved through a simple calibration method.

Description

A Time-to-Digital Converter Based on Fully Differential Ring Oscillator with PVT Robustness

technical field

The invention relates to a time-to-digital converter, in particular to a time-to-digital converter based on a fully differential ring oscillator with PVT robustness.

Background technique

In recent years, with the rapid development of all-digital phase-locked loop technology, time digital converter (TDC) has received high attention as one of the key modules. TDC-based digital phase-locked loops have the characteristics of high integration, easy calibration and programmability. With the evolution of process nodes, all-digital phase-locked loops also show advantages in area and performance. The traditional charge pump phase-locked loop structure includes modules such as frequency discriminator, charge pump, loop filter, voltage controlled oscillator and frequency divider. The charge pump and loop filter contain passive components such as capacitors and resistors. , in addition to consuming area, it also degrades the phase-noise performance of the phase-locked loop. In the new all-digital phase-locked loop, TDC is used to replace the frequency detector and the charge pump, and the phase information is directly processed in the time domain, which is further processed by an on-chip digital filter. Due to the programmability of the digital filter, the loop dynamics of the digital phase-locked loop can be changed in real time, so it can lock quickly while maintaining low phase noise. Also, the area of the digital phase-locked loop will be greatly reduced due to the removal of the large capacitors used in the analog filters. However, TDC has the same problem of limited accuracy as ordinary digital-to-analog converters, and the introduced quantization noise determines the in-band noise of the all-digital phase-locked loop. In addition to the accuracy requirements, the measurement range of the TDC also needs to cover a complete input reference clock cycle to avoid the problem of the digital phase-locked loop losing lock. In addition, the uncertainty of the process and the change of PVT robustness seriously restrict the actual production application of TDC. The main reason is that the measurement accuracy of ordinary TDC is determined by the delay time of the delay unit, and the delay time varies with process angle, voltage, temperature changes with the change.

The inverter chain TDC is simple to implement and has a large measurement range, but the accuracy is limited by the process node. The cursor chain type TDC has high accuracy, but often sacrifices indicators such as area and power consumption in order to increase the measurement range. Two-step TDC is a combination of inverter chain TDC and vernier TDC, which has higher accuracy and larger measurement range, but does not have the robustness of PVT (Pyramid Vision Transformer). Vernier ring TDC can theoretically provide infinite accuracy and measurement range. The measurement result consists of the absolute delay and relative delay of the two ring oscillators, so performance such as linearity and accuracy are affected by these two aspects. In addition, because the ring oscillator is often composed of odd-numbered inverters, the layout design is difficult, resulting in a large difference in imitation performance before and after.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a time-to-digital converter based on a fully differential ring oscillator with PVT robustness, so as to solve the above-mentioned problems in the prior art.

The time-to-digital converter based on a fully differential ring oscillator with PVT robustness according to the present invention includes a front-end module, a global control module, a delay unit and a decoding module that are electrically connected in sequence; a delay calibration module is also arranged to be connected respectively The delay unit and the decoding module are used for delay calibration of the delay unit;

The delay unit is a fully differential ring oscillator module.

The fully differential ring oscillator module includes,

Four fully differential inverters connected end to end to form a slow loop;

four additional fully differential inverters connected end to end to form a fast loop; and,

Four edge SR flip-flops used to collect and compare the lead or lag of the node signal in the slow loop and the fast loop.

The four fully differential inverters that form the slow loop are the first fully differential inverter, the second fully differential inverter, the third fully differential inverter and the fourth fully differential inverter: the first fully differential inverter The non-inverting output terminal of the fully differential inverter is connected to the inverting input terminal of the second fully differential inverter, and the inverting output terminal of the first fully differential inverter is connected to the non-inverting input terminal of the second fully differential inverter; The non-inverting output terminal of the second fully differential inverter is connected to the inverting input terminal of the third fully differential inverter, and the inverting output terminal of the second fully differential inverter is connected to the non-inverting output terminal of the third fully differential inverter. Input terminal; the non-inverting output terminal of the third fully differential inverter is connected to the inverting input terminal of the fourth fully differential inverter, and the inverting output terminal of the third fully differential inverter is connected to the fourth fully differential inverter. The non-inverting input terminal of the inverter; the non-inverting output terminal of the fourth fully differential inverter is connected to the non-inverting input terminal of the first fully differential inverter, and the inverting output terminal of the fourth fully differential inverter is connected to the first fully differential inverter. The inverting input of a fully differential inverter;

The four fully differential inverters that make up the fast loop are the fifth fully differential inverter, the sixth fully differential inverter, the seventh fully differential inverter and the eighth fully differential inverter: the fifth fully differential inverter The non-inverting output terminal of the fully differential inverter is connected to the inverting input terminal of the sixth fully differential inverter, and the inverting output terminal of the fifth fully differential inverter is connected to the non-inverting input terminal of the sixth fully differential inverter; The non-inverting output terminal of the sixth fully differential inverter is connected to the inverting input terminal of the seventh fully differential inverter, and the inverting output terminal of the sixth fully differential inverter is connected to the non-inverting input terminal of the seventh fully differential inverter. Input terminal; the non-inverting output terminal of the seventh fully differential inverter is connected to the inverting input terminal of the eighth fully differential inverter, and the inverting output terminal of the seventh fully differential inverter is connected to the eighth fully differential inverter The non-inverting input terminal of the inverter; the non-inverting output terminal of the eighth fully differential inverter is connected to the non-inverting input terminal of the fifth fully differential inverter, and the inverting output terminal of the eighth fully differential inverter is connected to the fifth fully differential inverter. The inverting input of a fully differential inverter;

The four edge SR flip-flops are the first edge SR flip-flop, the second edge SR flip-flop, the third edge SR flip-flop and the fourth edge SR flip-flop: the first edge SR flip-flop is connected to the slow loop input The inverting output terminal of the first fully differential inverter, the fast loop input terminal of the first edge SR flip-flop is connected to the inverting output terminal of the fifth fully differential inverter, and the first edge SR flip-flop is reset The terminal RST_E is connected to the inverting output terminal of the third fully differential inverter; the slow loop input terminal of the second edge SR flip-flop is connected to the non-inverting output terminal of the first fully differential inverter, and the second edge SR triggering The input terminal of the fast loop of the inverter is connected to the non-inverting output terminal of the fifth fully differential inverter, and the reset terminal RST_E of the second edge SR flip-flop is connected to the non-inverting output terminal of the third fully differential inverter; the third edge SR The trigger slow loop input terminal is connected to the inverting output terminal of the third full differential inverter, the fast loop input terminal of the third edge SR flip-flop is connected to the inverting output terminal of the seventh full differential inverter, and the The reset terminal RST_E of the third edge SR flip-flop is connected to the non-inverting output terminal of the first fully differential inverter; the slow loop input terminal of the fourth edge SR flip-flop is connected to the non-inverting output terminal of the third fully differential inverter. The fourth edge SR flip-flop fast loop input terminal is connected to the non-inverting output terminal of the seventh fully differential inverter, and the fourth edge SR flip-flop reset terminal RST_E is connected to the inverting output terminal of the first fully differential inverter; The reset terminals RST_I of the first edge SR flip-flop, the second edge SR flip-flop, the third edge SR flip-flop and the fourth edge SR flip-flop are all connected to the external global reset signal RST, and the respective output terminals are connected to the the decoding module.

The four edge SR flip-flops have the same structure, and each edge SR flip-flop is mainly composed of three buffer modules, three rising edge detection modules, four PMOS transistors and six NMOS transistors;

The source of the fifth PMOS transistor and the source of the sixth PMOS transistor are connected to VDD in common;

The gate of the fifth PMOS transistor is preceded by the first rising edge detection module and used as the fast loop input terminal, and the gate of the sixth PMOS transistor is preceded by the second rising edge detection module and used as the fast and slow loop input terminals;

The drain of the fifth PMOS transistor is connected to the source of the seventh PMOS transistor, and the drain of the sixth PMOS transistor is connected to the source of the eighth PMOS transistor;

The drain of the seventh PMOS transistor, the gate of the eighth PMOS transistor, the drain of the ninth NMOS transistor, the drain of the eleventh NMOS transistor, the gate of the eighth NMOS transistor, the drain of the seventh NMOS transistor, and the drain of the The input of a buffer module has a common point, and the output terminal QB of the first buffer module is suspended;

The drain of the eighth PMOS transistor, the gate of the seventh PMOS transistor, the drain of the twelfth NMOS transistor, the drain of the tenth NMOS transistor, the gate of the seventh NMOS transistor, the drain of the eighth NMOS transistor, and the drain of the The input ends of the two buffer modules share the same point, and the output end Q of the second buffer module is connected to the decoding module;

The gates of the ninth NMOS transistor and the tenth NMOS transistor are connected to the input terminal of the third buffer module in common, and the output terminal of the third buffer module is connected to the reset terminal RST_I, which is connected to the global reset terminal RST; the eleventh NMOS transistor and After the gates of the twelfth NMOS transistors share the same point, the front third rising edge detection module is used as the reset terminal RST_E;

The sources of the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor and the twelfth NMOS transistor are connected to VSS in common.

The four fully differential inverters that make up the slow loop have the same structure as the other four fully differential inverters that make up the fast loop. Each fully differential inverter mainly consists of two inverters, four PMOS transistors, and six NMOS transistors. It consists of a transistor and two capacitor arrays;

The source of the third PMOS transistor is connected to VDD, the gate is connected to the output end of the first inverter, and the drain is connected to the sources of the first PMOS transistor and the second PMOS transistor, respectively;

The first inverter input terminal is used as the enabling terminal of the fully differential inverter;

The gate of the first PMOS transistor and the gate of the first NMOS transistor share a common point as a non-inverting input terminal, and the gate of the second PMOS transistor and the second NMOS transistor share a common point as an inverting input terminal;

The drain of the first PMOS transistor, the drain of the sixth NMOS transistor, the drain of the first NMOS transistor, the drain of the third NMOS transistor, the gate of the fourth NMOS transistor and the upper plate of the first capacitor array are in common as an inverting output terminal;

The drain of the second PMOS transistor, the drain of the fourth PMOS transistor, the drain of the second NMOS transistor, the drain of the fourth NMOS transistor, the gate of the third NMOS transistor and the upper plate of the second capacitor array share a common point as a non-inverting output terminal;

The source of the sixth NMOS transistor is connected to VSS, and the gate is connected to the output terminal of the first inverter; the source of the fourth PMOS transistor is connected to VDD, and the gate is connected to the output terminal of the second inverter; The lower plates of the two capacitor arrays are respectively connected to VSS;

The source of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor are connected to the drain of the fifth NMOS transistor after a common point;

The source of the fifth NMOS transistor is connected to VSS, and the gate is connected to the output end of the second inverter;

The input terminal of the second inverter is connected to the output terminal of the first inverter.

The invention has the advantages of a time-to-digital converter based on a fully differential ring oscillator with PVT robustness, which has the advantages of simultaneously achieving high precision and dynamic range, and improving the PVT robustness of TDC through a simple calibration method. Rod tolerance and linearity.

Description of drawings

Fig. 1 is the structural representation of the time-to-digital converter of the present invention;

Fig. 2 is the circuit schematic diagram of the fully differential ring oscillator according to the present invention;

3 is a circuit schematic diagram of the edge SR flip-flop according to the present invention;

FIG. 4 is a circuit schematic diagram of the fully differential inverter according to the present invention.

Reference number:

FDINV1 to FDINV8: the first fully differential inverter to the eighth fully differential inverter;

ARB1 to ARB4: the first edge SR flip-flop to the fourth edge SR flip-flop;

RUD1 to RUD3: the first rising edge detection module to the third rising edge detection module;

BUF1 to BUF3: the first buffer module to the third buffer module;

INV1-first inverter, INV2-second inverter;

MP1 to MP8: first to eighth PMOS transistors;

MN1 to MN12: first to twelfth NMOS transistors;

CDAC1-the first capacitor array, CDAC2-the second capacitor array;

Von-inverting output, Vop-non-inverting output.

Detailed ways

As shown in FIG. 1 , a time-to-digital converter based on a fully differential ring oscillator with PVT robustness according to the present invention includes a front-end module, a global control module, a delay unit and a decoding module that are electrically connected in sequence; A delay calibration module is respectively connected to the delay unit and the decoding module, and the type of the delay unit is a fully differential ring oscillator module.

The two inputs of the front-end module are connected to the clock REF and the frequency divider output clock DIV, the phases of the two clock signals are judged successively, and two corresponding outputs are generated, which are respectively the fast signal LEAD_PUS and the slow signal LAG_PUS, and simultaneously output the TDC. The most significant MSB and the global reset signal RST. The front-end module judges the arrival speed of the two clocks. If the clock REF arrives first, the clock REF is sent to the fast signal LEAD_PUS output, and the clock LAG is sent to the slow signal LAG_PUS output, and the MSB of the highest bit becomes 1; if the clock DIV arrives first, Then the clock REF is sent to the slow signal LAG_PUS output, the clock DIV is sent to the fast signal LEAD_PUS output, and the MSB of the highest bit becomes 0.

The global control module has two working modes. When the signal CAL_EN is 0, it works in the first mode, and when the signal CAL_EN is 1, it works in the second mode. The first mode is used to receive the fast signal LEAD_PUS and the slow signal LAG_PUS, and convert it into the fast signal LEAD_PUS and the slow signal LAG_PUS with a certain pulse width according to the signal STOP, which is used to control the operation and shutdown of the fully differential ring oscillator module; The second mode is used to receive the calibration signal CAL_EN, and convert the cycle of the clock into two correspondingly spaced fast signals LEAD_PUS and slow signals LAG_PUS, and further cooperate with the delay calibration module to complete the full differential ring oscillator module. delay calibration. When the global reset signal RST is received as 1, the global control module is reset and waits for the arrival of the next pair of LEAD_PUS and LAG_PUS. When the received signal STOP is 1, the fast signal LEAD_PUS and the slow signal LAG_PUS not only change from 1 to 0 at the same time, but also generate a falling edge, which is used to turn off the fully differential ring oscillator module of the next stage, so as not to continue to generate power consumption .

The fully differential ring oscillator module sends the fast signal LEAD_PUS received first to the slow ring, and the slow ring starts to oscillate; it sends the slow signal LAG_PUS received later to the fast ring, and the fast ring also starts to oscillate and starts to catch up with the slow ring. The number of turns of the two loops and the specific position of the catch-up will be output to the next-level decoding module through the SLAP terminal, the FLAP terminal and the Q terminal.

The decoding module includes two 3bit counters, a thermometer code parser and a digital logic unit. Among them, the two counters are used to record the number of turns of the fast loop and the slow loop respectively, the thermometer code parser is used to generate the least significant bit of TDC, and the digital logic unit is used to synthesize and convert the output of the counter and the thermometer code parser into TDC Output signal D, and generate signal STOP.

The delay calibration module is a digital circuit, the input is connected to the output signal D of the time-to-digital converter, and the two outputs are respectively connected to the CFGS terminal and the CFGF terminal of the fully differential ring oscillator module for adjusting the slow loop and fast loop. The delay time of the medium delay unit. In the calibration stage, the corresponding digital output signal D is directly read, and compared with the preset value, the CFGF terminal and the CFGS terminal are set according to the SAR logic successive approximation, and the accuracy of the time-to-digital converter is further adjusted.

As shown in Fig. 2, the fully differential ring oscillator module includes: four peripheral fully differential inverters and another four inner peripheral fully differential inverters, as well as a method for collecting and comparing the slow ring and the fast ring. The node signal leads or lags the four edge SR flip-flops between the slow loop and the fast loop. The four peripheral fully differential inverters are connected end to end to form a slow ring (slowly round, SR), and the four inner peripheral fully differential inverters are connected end to end to form a fast round (FR).

The four fully differential inverters that form the slow loop are the first fully differential inverter FDINV1, the second fully differential inverter FDINV2, the third fully differential inverter FDINV3, and the fourth fully differential inverter FDINV4: The non-inverting output terminal of the first fully differential inverter FDINV1 is connected to the inverting input terminal of the second fully differential inverter FDINV2, and the inverting output terminal of the first fully differential inverter FDINV1 is connected to the second fully differential inverter. The non-inverting input terminal of the inverter FDINV2; the non-inverting output terminal of the second fully differential inverter FDINV2 is connected to the inverting input terminal of the third fully differential inverter FDINV3, and the inverting output terminal of the second fully differential inverter FDINV2 The terminal is connected to the non-inverting input terminal of the third fully differential inverter FDINV3; the non-inverting output terminal of the third fully differential inverter FDINV3 is connected to the inverting input terminal of the fourth fully differential inverter FDINV4, and the third fully differential inverter FDINV3 non-phase output terminal is connected. The inverting output terminal of the differential inverter FDINV3 is connected to the non-inverting input terminal of the fourth fully differential inverter FDINV4; the non-inverting output terminal of the fourth fully differential inverter FDINV4 is connected to the non-inverting input terminal of the first fully differential inverter FDINV1 , the inverting output terminal of the fourth fully differential inverter FDINV4 is connected to the inverting input terminal of the first fully differential inverter FDINV1.

The four fully differential inverters that make up the fast loop are the fifth fully differential inverter FDINV5, the sixth fully differential inverter FDINV6, the seventh fully differential inverter FDINV7 and the eighth fully differential inverter FDINV8: The non-inverting output terminal of the fifth fully differential inverter FDINV5 is connected to the inverting input terminal of the sixth fully differential inverter FDINV6, and the inverting output terminal of the fifth fully differential inverter FDINV5 is connected to the sixth fully differential inverter. The non-inverting input terminal of the inverter FDINV6; the non-inverting output terminal of the sixth fully differential inverter FDINV6 is connected to the inverting input terminal of the seventh fully differential inverter FDINV7, and the sixth fully differential inverter FDINV6 inverting output The terminal is connected to the non-inverting input terminal of the seventh fully differential inverter FDINV7; the non-inverting output terminal of the seventh fully differential inverter FDINV7 is connected to the inverting input terminal of the eighth fully differential inverter FDINV8. The inverting output terminal of the differential inverter FDINV7 is connected to the non-inverting input terminal of the eighth fully differential inverter FDINV8; the non-inverting output terminal of the eighth fully differential inverter FDINV8 is connected to the non-inverting input terminal of the fifth fully differential inverter FDINV5 , the inverting output terminal of the eighth fully differential inverter FDINV8 is connected to the inverting input terminal of the fifth fully differential inverter FDINV5.

The four edge SR flip-flops are the first edge SR flip-flop ARB1, the second edge SR flip-flop ARB2, the third edge SR flip-flop ARB3 and the fourth edge SR flip-flop ARB4: the first edge SR flip-flop ARB1 The slow loop input terminal is connected to the inverting output terminal of the first full differential inverter FDINV1, the fast loop input terminal of the first edge SR flip-flop ARB1 is connected to the inverting output terminal of the fifth full differential inverter FDINV5, and the The reset terminal RST_E of the first edge SR flip-flop ARB1 is connected to the inverting output terminal of the third fully differential inverter FDINV3; the slow loop input terminal of the second edge SR flip-flop ARB2 is connected to the first fully differential inverter FDINV1. Non-inverting output terminal, the fast loop input terminal of the second edge SR flip-flop ARB2 is connected to the non-inverting output terminal of the fifth fully differential inverter FDINV5, and the reset terminal RST_E of the second edge SR flip-flop ARB2 is connected to the third fully differential inverter. The non-inverting output end of the inverter FDINV3; the slow loop input end of the third edge SR flip-flop ARB3 is connected to the inverting output end of the third full differential inverter FDINV3, and the third edge SR flip-flop ARB3 fast loop The input terminal is connected to the inverting output terminal of the seventh fully differential inverter FDINV7, and the reset terminal RST_E of the third edge SR flip-flop ARB3 is connected to the non-inverting output terminal of the first fully differential inverter FDINV1; the fourth edge The slow loop input end of the SR flip-flop ARB4 is connected to the non-inverting output end of the third full differential inverter FDINV3, and the fast loop input end of the fourth edge SR flip-flop ARB4 is connected to the non-inverting output end of the seventh full differential inverter FDINV7, The reset terminal RST_E of the fourth edge SR flip-flop ARB4 is connected to the inverting output terminal of the first fully differential inverter FDINV1; the first edge SR flip-flop ARB1, the second edge SR flip-flop ARB2, the third edge The reset terminals RST_I of the SR flip-flop ARB3 and the fourth-edge SR flip-flop ARB4 are both connected to the external global reset signal RST, and the respective output terminals are respectively connected to the decoding module.

In the initial stage, the first-stage inverters of the two loops all work in the preset state of enabling invalidation, while the other three stages work in the enabling and valid state. When the fast signal LEAD_PUS arrives, the slow loop starts to oscillate, and the fast signal LEAD_PUS is transmitted along the slow loop; when the slow signal LAG_PUS arrives, the fast loop also starts to oscillate, and the slow signal LAG_PUS transmits along the fast loop and starts to chase the slow loop. Fast signal LEAD_PUS. At the same time, the four edge SR flip-flops are used to determine the order in which the fast signal LEAD_PUS and the slow signal LAG_PUS arrive at the same node. If the slow signal LAG_PUS at the FN<0> end arrives earlier than the fast signal LEAD_PUS at the SN<0> end, the edge SR flip-flop The output is 1, otherwise it is 0.

Compared with the traditional sampling method with D flip-flop, this edge SR flip-flop has the following advantages: D flip-flop compares the speed of the two signals through the clock terminal CLK and the data terminal D, but the clock terminal CLK and the data terminal D compare the speed of the two signals. The structure is asymmetric, so there is an offset affected by PVT, while the structure of the edge SR flip-flop is strictly symmetrical, and the offset is smaller; in addition, the D flip-flop sampling needs to be processed in case 010 and case 10, resulting in more complicated and redundant digital processing circuits. However, using edge SR flip-flops to sample two loops only occurs in case 10, thus reducing the subsequent design work and difficulty. Since the slow loop is used as a reference to determine the arrival speed of the fast signal LEAD_PUS and the slow signal LAG_PUS, the reset of the edge SR flip-flop is given by the output node of the slow loop, and the reset of the next-level edge SR flip-flop is given by the slow loop of the previous stage. Node gives.

As shown in FIG. 3 , the four edge SR flip-flops have the same structure, and each edge SR flip-flop is mainly composed of three rising edge detection modules, four PMOS transistors and six NMOS transistors. On the basis of the fully differential ring oscillator, the time-to-digital converter only uses four edge SR flip-flops to realize the capture of the position on the signal transmission path, thereby reducing the overall design complexity.

The source of the fifth PMOS transistor MP5 and the source of the sixth PMOS transistor MP6 are connected to VDD in common; the gate of the fifth PMOS transistor MP5 is preceded by the first rising edge detection module RUD1 as a slow loop input terminal, and the sixth PMOS transistor The gate of MP6 is preceded by the second rising edge detection module RUD2 and then used as the input terminal of the fast loop.

The drain of the fifth PMOS transistor MP5 is connected to the source of the seventh PMOS transistor MP7, and the drain of the sixth PMOS transistor MP6 is connected to the source of the eighth PMOS transistor MP8.

The drain of the seventh PMOS transistor MP7, the gate of the eighth PMOS transistor MP8, the drain of the ninth NMOS transistor MN9, the drain of the eleventh NMOS transistor MN11, the gate of the eighth NMOS transistor MN8, the seventh NMOS transistor The drain of MN7 and the input of the first buffer module (BUF1) share the same point, and the output terminal QB of the first buffer module (BUF1) is suspended;

The drain of the eighth PMOS transistor MP8, the gate of the seventh PMOS transistor MP7, the drain of the twelfth NMOS transistor MN12, the drain of the tenth NMOS transistor MN10, the gate of the seventh NMOS transistor MN7, the eighth NMOS transistor The drain of MN8 and the input end of the second buffer module BUF2 are in common, and the output end Q of the second buffer module BUF2 is connected to the decoding module;

The gates of the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 are connected to the input terminal of the third buffer module BUF3 in common, and the output terminal of the third buffer module is connected to the reset terminal RST_I, which is connected to the global reset terminal RST; the eleventh After the gates of the NMOS transistor MN11 and the twelfth NMOS transistor MN12 share the same point, the third rising edge detection module RUD3 is set as the reset terminal RST_E;

The sources of the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the first NMOS transistor MN1 and the twelfth NMOS transistor MN12 are connected in common to VSS.

In the initial stage, the reset terminal RST_I is 1, the Q terminal and the QB terminal are both discharged to 0 through the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10, and the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 are pre-conducted. After the reset is completed, the reset terminal RST_I becomes 0. If the S terminal detects the rising edge first, a short negative pulse will be generated by the second rising edge detection module RUD2, the sixth PMOS transistor MP6 is turned on, and then the Q terminal is charged to a high level, and the seventh NMOS transistor MN7 is turned on , the QB terminal is further discharged and set to low level. On the contrary, if the R terminal detects the rising edge first, the Q terminal becomes 0. The other reset terminal RST_E is used for local reset. When the third rising edge detection module RUD3 detects the rising edge of the reset terminal RST_E, it will output a short positive pulse, and then turn on the eleventh NMOS transistors MN11 and tenth Two NMOS transistors MN12 are reset.

As shown in Figure 4, the four fully differential inverters that form the slow loop have the same structure as the other four fully differential inverters that form the fast loop. Each fully differential inverter mainly consists of two inverters, four It consists of PMOS transistors, six NMOS transistors and two capacitor arrays.

The source of the third PMOS transistor MP3 is connected to VDD, the gate is connected to the output terminal of the first inverter INV1, and the drain is connected to the sources of the first PMOS transistor MP1 and the second PMOS transistor MP2, respectively.

The input end of the first inverter INV1 is used as the enabling end of the fully differential inverter; the output end of the first inverter INV1 is connected to the input end of the second inverter INV2. The gate of the first PMOS transistor MP1 and the gate of the first NMOS transistor MN1 share a common point as a non-inverting input terminal, and the gates of the second PMOS transistor MP2 and the second NMOS transistor MN2 share a common point as an inverting input terminal.

The drain of the first PMOS transistor MP1, the drain of the sixth NMOS transistor MN6, the drain of the first NMOS transistor MN1, the drain of the third NMOS transistor MN3, the gate of the fourth NMOS transistor MN4 and the upper plate of the first capacitor array CDAC1 are in common as the inverting output.

The drain of the second PMOS transistor MP2, the drain of the fourth PMOS transistor MP4, the drain of the second NMOS transistor MN2, the drain of the fourth NMOS transistor MN4, the gate of the third NMOS transistor MN3 and the upper plate of the second capacitor array CDAC2 are in common as a non-inverting output.

The source of the sixth NMOS transistor MN6 is connected to VSS, and the gate is connected to the output terminal of the first inverter INV1; the source of the fourth PMOS transistor MP4 is connected to VDD, and the gate is connected to the output terminal of the second inverter INV2; the first The lower plates of the capacitor array CDAC1 and the second capacitor array CDAC2 are respectively connected to the VSS.

The sources of the first NMOS transistor MN1 , the second NMOS transistor MN2 , the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected to the drain of the fifth NMOS transistor MN5 after a common point.

The source of the fifth NMOS transistor MN5 is connected to VSS, and the gate is connected to the output terminal of the second inverter INV2.

EN has two states, which are set to 0 and 1 respectively. When EN is 0, the third PMOS transistor MP3 and the fifth NMOS transistor MN5 are both turned off, the sixth NMOS transistor MN6 and the fourth PMOS transistor MP4 are turned on, Von is discharged to a low level, and Vop is charged to a high level; EN is 1 At this time, the third PMOS transistor MP3 and the fifth NMOS transistor MN5 are turned on, and the inverter works normally. Further, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 accelerate the transition of the output state through positive feedback. The first capacitor array CDAC1 and the second capacitor array CDAC2 located at the output are used to adjust the delay of the inverter. The purpose is to calibrate the delay time in the calibration stage, overcome the influence of PVT robustness on the delay of the inverter, and improve the The accuracy of TDC, compared with existing temporal TDC, is more robust against PVT.

For those skilled in the art, various other corresponding changes and deformations can be made according to the technical solutions and concepts described above, and all these changes and deformations should fall within the protection scope of the claims of the present invention.

Claims (3)

1. a time-to-digital converter based on a fully differential ring oscillator with PVT robustness, comprising a front-end module, a global control module, a delay unit and a decoding module that are electrically connected in turn; a delay calibration module is also provided to connect the described a delay unit and a decoding module for delay calibration of the delay unit; It is characterized in that, The delay unit is a fully differential ring oscillator module; The fully differential ring oscillator module includes, Four fully differential inverters connected end to end to form a slow loop; The other four fully differential inverters are connected end to end to form a fast loop; as well as, Four edge SR flip-flops for collecting and comparing node signals in the slow loop and the fast loop leading or lagging; The four fully differential inverters that make up the slow loop are the first fully differential inverter (FDINV1), the second fully differential inverter (FDINV2), the third fully differential inverter (FDINV3) and the fourth fully differential inverter. Inverter (FDINV4): the non-inverting output terminal of the first fully differential inverter (FDINV1) is connected to the inverting input terminal of the second fully differential inverter (FDINV2), and the first fully differential inverter (FDINV2) (FDINV1) The inverting output terminal is connected to the non-inverting input terminal of the second fully differential inverter (FDINV2); the non-inverting output terminal of the second fully differential inverter (FDINV2) is connected to the third fully differential inverter (FDINV3) The inverting input terminal of the second fully differential inverter (FDINV2) is connected to the non-inverting input terminal of the third fully differential inverter (FDINV3); the third fully differential inverter (FDINV3) The non-inverting output terminal of FDINV3) is connected to the inverting input terminal of the fourth fully differential inverter (FDINV4), and the inverting output terminal of the third fully differential inverter (FDINV3) is connected to the fourth fully differential inverter (FDINV4) The non-inverting input terminal of the fourth fully differential inverter (FDINV4) is connected to the non-inverting input terminal of the first fully differential inverter (FDINV1), and the fourth fully differential inverter (FDINV4) The inverting output terminal is connected to the inverting input terminal of the first fully differential inverter (FDINV1); The four fully differential inverters that make up the fast loop are the fifth fully differential inverter (FDINV5), the sixth fully differential inverter (FDINV6), the seventh fully differential inverter (FDINV7) and the eighth fully differential inverter. Inverter (FDINV8): the non-inverting output terminal of the fifth fully differential inverter (FDINV5) is connected to the inverting input terminal of the sixth fully differential inverter (FDINV6), and the fifth fully differential inverter (FDINV6) (FDINV5) the inverting output terminal is connected to the non-inverting input terminal of the sixth fully differential inverter (FDINV6); the non-inverting output terminal of the sixth fully differential inverter (FDINV6) is connected to the seventh fully differential inverter (FDINV7) The inverting input terminal of the sixth fully differential inverter (FDINV6) is connected to the non-inverting input terminal of the seventh fully differential inverter (FDINV7); the seventh fully differential inverter (FDINV7) The non-inverting output terminal of FDINV7) is connected to the inverting input terminal of the eighth fully differential inverter (FDINV8), and the inverting output terminal of the seventh fully differential inverter (FDINV7) is connected to the eighth fully differential inverter (FDINV8) The non-inverting input terminal of the eighth fully differential inverter (FDINV8) is connected to the non-inverting input terminal of the fifth fully differential inverter (FDINV5), and the eighth fully differential inverter (FDINV8) The inverting output terminal is connected to the inverting input terminal of the fifth fully differential inverter (FDINV5); The four edge SR flip-flops are the first edge SR flip-flop (ARB1), the second edge SR flip-flop (ARB2), the third edge SR flip-flop (ARB3) and the fourth edge SR flip-flop (ARB4): the The slow loop input of the first edge SR flip-flop (ARB1) is connected to the inverting output of the first fully differential inverter (FDINV1), and the fast loop input of the first edge SR flip-flop (ARB1) is connected to the fifth The inverting output terminal of the fully differential inverter (FDINV5), the reset terminal RST_E of the first edge SR flip-flop (ARB1) is connected to the inverting output terminal of the third fully differential inverter (FDINV3); The slow loop input end of the two-edge SR flip-flop (ARB2) is connected to the non-inverting output end of the first fully differential inverter (FDINV1), and the fast loop input end of the second edge SR flip-flop (ARB2) is connected to the fifth fully differential inverter. The non-inverting output terminal of the inverter (FDINV5), the reset terminal RST_E of the second edge SR flip-flop (ARB2) is connected to the non-inverting output terminal of the third fully differential inverter (FDINV3); the third edge SR flip-flop (ARB3) slow loop input terminal is connected to the inverting output terminal of the third full differential inverter (FDINV3), and the fast loop input terminal of the third edge SR flip-flop (ARB3) is connected to the seventh full differential inverter (FDINV7) ), the reset terminal RST_E of the third edge SR flip-flop (ARB3) is connected to the non-inverting output terminal of the first fully differential inverter (FDINV1); the fourth edge SR flip-flop (ARB4) The slow loop input terminal is connected to the non-inverting output terminal of the third fully differential inverter (FDINV3), and the fast loop input terminal of the fourth edge SR flip-flop (ARB4) is connected to the non-inverting output terminal of the seventh fully differential inverter (FDINV7). terminal, the reset terminal RST_E of the fourth edge SR flip-flop (ARB4) is connected to the inverting output terminal of the first fully differential inverter (FDINV1); the first edge SR flip-flop (ARB1), the second edge The reset terminals RST_I of the SR flip-flop (ARB2), the third-edge SR flip-flop (ARB3) and the fourth-edge SR flip-flop (ARB4) are all connected to the external global reset signal RST, and their respective output terminals are connected to the decoding module. 2. a kind of time-to-digital converter with PVT robustness based on fully differential ring oscillator according to claim 1, is characterized in that, described four edge SR flip-flops have the same structure, and each edge SR flip-flop is mainly It consists of three buffer modules, three rising edge detection modules, four PMOS transistors and six NMOS transistors; The source of the fifth PMOS transistor (MP5) and the source of the sixth PMOS transistor (MP6) are connected to VDD in common; The gate of the fifth PMOS transistor (MP5) is preceded by the first rising edge detection module (RUD1) as a slow loop input terminal, and the gate of the sixth PMOS transistor (MP6) is preceded by the second rising edge detection module (RUD2) As a fast loop input; The drain of the fifth PMOS transistor (MP5) is connected to the source of the seventh PMOS transistor (MP7), and the drain of the sixth PMOS transistor (MP6) is connected to the source of the eighth PMOS transistor (MP8); The drain of the seventh PMOS transistor (MP7), the gate of the eighth PMOS transistor (MP8), the drain of the ninth NMOS transistor (MN9), the drain of the eleventh NMOS transistor (MN11), the drain of the eighth NMOS transistor ( The gate of MN8), the drain of the seventh NMOS transistor (MN7) and the input of the first buffer module (BUF1) share the same point, and the output terminal QB of the first buffer module (BUF1) is floating; The drain of the eighth PMOS transistor (MP8), the gate of the seventh PMOS transistor (MP7), the drain of the twelfth NMOS transistor (MN12), the drain of the tenth NMOS transistor (MN10), the drain of the seventh NMOS transistor ( The gate of MN7), the drain of the eighth NMOS transistor (MN8) and the input terminal of the second buffer module (BUF2) are in common, and the output terminal Q of the second buffer module (BUF2) is connected to the decoding module ; The gates of the ninth NMOS transistor (MN9) and the tenth NMOS transistor (MN10) are connected to the input terminal of the third buffer module (BUF3) in common, and the output terminal of the third buffer module is connected to the reset terminal RST_I, and RST_I is externally connected to the global reset terminal RST; after the gates of the eleventh NMOS transistor (MN11) and the twelfth NMOS transistor (MN12) are at the same point, the third rising edge detection module (RUD3) is used as the reset terminal RST_E; Seventh NMOS transistor (MN7), eighth NMOS transistor (MN8), ninth NMOS transistor (MN9), tenth NMOS transistor (MN10), eleventh NMOS transistor (MN11) and twelfth NMOS transistor (MN12) source The pole common point is connected to VSS. 3. a kind of time-to-digital converter based on fully differential ring oscillator with PVT robustness according to claim 1 is characterized in that, four fully differential inverters that form slow loop and another four that form fast loop The fully differential inverter has the same structure, and each fully differential inverter is mainly composed of two inverters, four PMOS transistors, six NMOS transistors and two capacitor arrays; The source of the third PMOS transistor (MP3) is connected to VDD, the gate is connected to the output terminal of the first inverter (INV1), and the drain is connected to the sources of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), respectively ; The input end of the first inverter (INV1) is used as the enabling end of the fully differential inverter; The gate of the first PMOS transistor (MP1) and the gate of the first NMOS transistor (MN1) are in common as a non-inverting input terminal, and the gates of the second PMOS transistor (MP2) and the second NMOS transistor (MN2) are in common as an inverting input. phase input; The drain of the first PMOS transistor (MP1), the drain of the sixth NMOS transistor (MN6), the drain of the first NMOS transistor (MN1), the drain of the third NMOS transistor (MN3), the gate of the fourth NMOS transistor (MN4) and The common point of the upper plate of the first capacitor array (CDAC1) is used as an inverting output terminal; Second PMOS transistor (MP2) drain, fourth PMOS transistor (MP4) drain, second NMOS transistor (MN2) drain, fourth NMOS transistor (MN4) drain, third NMOS transistor (MN3) gate and The upper plate of the second capacitor array (CDAC2) has a common point as a non-inverting output terminal; The source of the sixth NMOS transistor (MN6) is connected to VSS, and the gate is connected to the output terminal of the first inverter (INV1); the source of the fourth PMOS transistor (MP4) is connected to VDD, and the gate is connected to the second inverter ( The output end of INV2); the lower plates of the first capacitor array (CDAC1) and the second capacitor array (CDAC2) are respectively connected to VSS; The sources of the first NMOS transistor (MN1), the second NMOS transistor (MN2), the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4) are connected to the drain of the fifth NMOS transistor (MN5) after the source is common; The source of the fifth NMOS transistor (MN5) is connected to VSS, and the gate is connected to the output end of the second inverter (INV2); The input terminal of the second inverter (INV2) is connected to the output terminal of the first inverter (INV1).

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