CN114038850A - Dynamic random access memory and method of making the same - Google Patents
Dynamic random access memory and method of making the same Download PDFInfo
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- CN114038850A CN114038850A CN202111403345.8A CN202111403345A CN114038850A CN 114038850 A CN114038850 A CN 114038850A CN 202111403345 A CN202111403345 A CN 202111403345A CN 114038850 A CN114038850 A CN 114038850A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
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Abstract
本发明公开了一种动态随机存取存储器及其制作方法，包括衬底、设置在衬底内的隔离结构、设置在衬底上的多条位线、设置在位线之间并与有源区直接接触的多个存储节点接触插塞，以及分别设置在存储节点接触插塞上并且与位线部分重叠的多个存储节点接触垫，其中存储节点接触垫包括位于位线正上方的第一侧壁以及位于存储节点接触插塞正上方的第二侧壁。所述动态随机存取存储器还包括金属氮化物层，至少覆盖在存储节点接触垫的第一侧壁和第二侧壁上。
The invention discloses a dynamic random access memory and a manufacturing method thereof. a plurality of storage node contact plugs in direct contact with the region, and a plurality of storage node contact pads respectively disposed on the storage node contact plugs and partially overlapping the bit lines, wherein the storage node contact pads include a first sidewalls and a second sidewall directly above the storage node contact plugs. The DRAM further includes a metal nitride layer covering at least the first sidewall and the second sidewall of the storage node contact pad.
Description
Technical Field
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a dynamic random access memory and a method for fabricating the same.
Background
A Dynamic Random Access Memory (DRAM), which belongs to a volatile memory, includes an array area (array area) composed of a plurality of memory cells (memory cells) and a peripheral area (peripheral area) composed of a control circuit. Each memory cell is composed of a transistor (transistor) and a capacitor (capacitor) electrically connected with the transistor, and the transistor controls the storage or release of charges in the capacitor to achieve the purpose of storing data. The control circuit is addressable to each memory cell by a Word Line (WL) and a Bit Line (BL) across the array region and electrically connected to each memory cell to control access to data of each memory cell.
In order to reduce the size of the memory cell and manufacture the chip with higher integration density, the structure of the memory cell has been developed towards three-dimensional (three-dimensional), for example, embedded word line connection (buried word line) and stacked capacitor (stacked capacitor) are adopted. The stacked capacitor has the advantages that the capacitor of the storage unit is vertically arranged above the substrate, the substrate area occupied by the capacitor can be saved, and larger capacitance can be conveniently obtained by increasing the height of the electrode plate of the capacitor. Currently, the stacked capacitor is electrically connected to a transistor fabricated in a substrate through a storage node contact structure. There is still a need in the art for a storage node contact structure that provides good electrical connection quality to ensure the performance of a dram.
Disclosure of Invention
The invention provides a dynamic random access memory and a manufacturing method thereof, wherein a metal nitride layer is formed on the surface of a metal material exposed by a storage node contact plug and a storage node contact pad by using a nitridation manufacturing process after the storage node contact plug and the storage node contact pad are formed, and the metal nitride layer can reduce the problem of deterioration of the metal material due to reaction with air and/or gas used in a subsequent process, thereby improving the electrical connection quality of the storage node contact pad.
According to an embodiment of the invention, a dynamic random access memory is provided, which includes a substrate, an isolation structure disposed in the substrate, a plurality of bit lines disposed on the substrate, a plurality of storage node contact plugs disposed between the bit lines and directly contacting the active region, and a plurality of storage node contact pads disposed on the storage node contact plugs and partially overlapping top surfaces of the bit lines, respectively. The storage node contact pad includes a first sidewall directly above the bit line, and a second sidewall directly above the storage node contact plug. A metal nitride layer at least covering the first sidewall and the second sidewall of the storage node contact pad.
According to an embodiment of the present invention, a method for manufacturing a dynamic random access memory includes the following steps. First, a substrate is provided, and a plurality of bit lines are formed on the substrate. Then, a plurality of storage node contact plugs and a plurality of storage node contact pads respectively disposed on the storage node contact plugs are formed between the bit lines, wherein the storage node contact pads partially overlap top surfaces of the bit lines and include first sidewalls directly above the bit lines and second sidewalls directly above the storage node contact plugs. And subsequently, performing a nitridation manufacturing process to form a metal nitride layer at least covering the first side wall and the second side wall of the storage node contact pad.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the invention, and are incorporated in and constitute a part of this specification. These drawings and description are included to explain the principles of some embodiments. It should be noted that all the drawings are schematic drawings, and the relative sizes and proportions are adjusted for the purpose of illustration and drawing convenience. The same reference signs represent corresponding or similar features in different embodiments.
Fig. 1 to 10 are schematic views illustrating a method for manufacturing a dynamic random access memory according to an embodiment of the invention, wherein fig. 1 and 2 are plan views, and fig. 3 to 10 are cross-sectional views taken along a-a' line in fig. 2.
FIG. 11 is a cross-sectional view of a DRAM according to another embodiment of the present invention.
Wherein the reference numerals are as follows:
10 substrate
12 active region
14 isolation structure
16 buried word line
18 recess
20 bit line
20a semiconductor layer
20b metal layer
20c mask layer
32 first side wall
34 second side wall
36 third side wall
38 dielectric layer
42 semiconductor layer
44 barrier layer
50 metal layer
51 groove
52 storage node contact plug
52c top surface
54 storage node contact pad
54a first side wall
54b second side wall
54c top surface
62 metal nitride layer
70 dielectric layer
72 etch stop layer
74 first support layer
76 second support layer
80 capacitor structure
82 bottom electrode layer
84 capacitor dielectric layer
86 top electrode layer
A-A' tangent line
P1 recess manufacturing process
P2 cleaning and manufacturing process
P3 nitriding manufacturing process
P4 planarization process
T1 thickness
T2 thickness
Detailed Description
In order that those skilled in the art will be able to more fully understand the present invention, the following description of the preferred embodiments of the present invention, taken together with the accompanying drawings, will provide a further understanding of the invention. It is to be understood that the embodiments described below may be implemented in various other forms of implementation, which may be substituted, recombined, or mixed with other features of various embodiments without departing from the spirit of the present invention.
Fig. 1 to 10 are schematic views illustrating a method for manufacturing a dynamic random access memory according to an embodiment of the invention, wherein fig. 1 and 2 are plan views, and fig. 3 to 10 are cross-sectional views taken along a-a' line in fig. 2. Referring to fig. 1, a substrate 10, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, is provided, but not limited thereto. Isolation structures 14 are provided within the substrate 10 to define a plurality of active regions 12 in the substrate 10. Isolation structures 14 may comprise a dielectric material, such as silicon oxide (SiO)2) Silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon doped carbon (NDC), low-k dielectric materials such as Fluorinated Silica Glass (FSG), silicon carbon oxide (SiCOH), spin-on-glass (spin-on glass), porous low-k dielectric materials, organic polymer dielectric materials, or combinations thereof, but is not limited thereto. A plurality of buried word lines 16 are disposed in the substrate 10 and cut through each active region 12 to divide each active region 12 into two end portions and a middle portion.
Please refer to fig. 2 and fig. 3. An etch process may then be performed on the substrate 10 to form a recess 18 in the middle portion of the active region 12 and the isolation structures 14 adjacent thereto, and then a plurality of bit lines 20 may be formed on the substrate 10, and the bit lines 20 may be overlapped with the middle portion of the active region 12 through the recess 18. As shown in FIG. 3, bit line 20 may include a plurality ofThe layer structure, for example, may include a semiconductor layer 20a, a metal layer 20b, and a mask layer 20 c. The material of the semiconductor layer 20a may include polysilicon, amorphous silicon, or other semiconductor materials containing silicon or not containing silicon. The material of the metal layer 20b may include aluminum (Al), tungsten (W), copper (Cu), titanium aluminum (TiAl) alloy, or other suitable low-resistance metal material. The masking layer 20c may comprise a dielectric material, which may comprise, for example, silicon oxide (SiO)2) Silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or combinations thereof, but is not limited thereto. In some embodiments, the semiconductor layer 20a and the metal layer 20b may include an interface layer (not shown), such as a single-layer or multi-layer structure layer composed of titanium (Ti), tungsten silicide (WSi), tungsten nitride (WN), and/or other metal silicide or metal nitride, but not limited thereto.
Please refer to fig. 4. Deposition and etching processes may then be performed to form sidewall substructures on the sidewalls of the bit lines 20 and fill the recesses 18 with the sidewall substructures. According to an embodiment of the present invention, the sidewall spacer structure includes a multi-layer structure, for example, a first sidewall spacer 32, a second sidewall spacer 34 and a third sidewall spacer 36, wherein the first sidewall spacer 32 is covered along the sidewall of the bit line 20 and the surface of the recess 18, the second sidewall spacer 34 is located on the first sidewall spacer 32 at the bottom of the bit line 20 and fills the recess 18 at both sides of the bit line 20, and the third sidewall spacer 36 is located on the first sidewall spacer 32 at the sidewall of the bit line 20. The first, second and third spacers 32, 34 and 36, respectively, may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or combinations thereof, but are not limited thereto.
Please refer to fig. 5. A deposition process may then be performed to form a dielectric layer 38 on the substrate 10 and to fill the gaps between the bit lines 20 with the dielectric layer 38, and then a portion of the dielectric layer 38 may be etched away to form a plurality of contact holes (not shown) in the dielectric layer 38 between the bit lines 20 and to expose portions of the substrate 10 (e.g., the ends of the active regions 12). Subsequently, epitaxial growth may be performed to form the semiconductor layer 42 at the bottom of the contact hole, followed by a deposition process to form the barrier layer 44 and the metal layer 50 on the semiconductor layer 42 and the bit line 20. After the metal layer 50 is formed, a planarization process (e.g., a chemical mechanical polishing process) may be performed to remove a portion of the metal layer 50 until the metal layer 50 on the bit line 20 reaches a predetermined thickness and the metal layer 50 has a flat surface as a whole.
The material of dielectric layer 38 may include silicon oxide, but is not limited thereto. In some embodiments, a portion of the dielectric layer 38 may remain on the sidewalls of the bit line 20 between the third sidewall 36 and the barrier layer 44. In some embodiments, the barrier layer 44 and the semiconductor layer 42 may include a metal silicide layer (not shown), which may include titanium silicide (TiSix), tungsten silicide (Wsix), tantalum silicide (TaSix), molybdenum silicide (MoSix), cobalt silicide (CoSix), or nickel silicide (NiSix), or a combination thereof, but is not limited thereto.
Please refer to fig. 6. Next, a recess process P1 may be performed to etch away unwanted portions of the metal layer 50 and the barrier layer 44 to pattern the metal layer 50 and the barrier layer 44, obtaining a storage node contact plug 52 located within the contact hole and a storage node contact pad 54 located above the storage node contact plug 52 and separated by a trench 51. That is, the storage node contact plugs 52 and the storage node contact pads 54 are integrally formed and include the same material (i.e., the metal material of the metal layer 50). As shown in fig. 6, the storage node contact 54 may be offset toward the bit line 20 on one side to partially overlap the top surface of the bit line 20, and includes a first sidewall 54a directly above the bit line 20 and a second sidewall 54b directly above the storage node contact plug 52.
In some embodiments, to ensure that there is no metal layer 50 and/or barrier layer 44 remaining between storage node contact pads 54, the etching step used to form trenches 51 may be performed down until the bottom surfaces of trenches 51 are lower than the top surfaces of bitlines 20 (top surfaces of masking layer 20 c). Therefore, the storage node contact pad 54 may have a sectional shape similar to an inverted L shape, and the bottom end of the second sidewall 54b may be lower than the bottom end of the first sidewall 54a, and the length of the second sidewall 54b in the vertical direction may be greater than the length of the first sidewall 54a in the vertical direction.
In some embodiments, the recess forming process P1 may be followed by a cleaning process P2 to remove etch byproducts (e.g., polymers) attached to the surface and particles of the metal layer 50 material redeposited or otherwise dropped on the surface. The cleaning process P2 may include any suitable dry or wet cleaning method, such as, but not limited to, plasma cleaning, solvent cleaning, spray cleaning, etc.
Please refer to fig. 7. After the cleaning process P2 is completed, a nitridation process P3, such as a Decoupled Plasma Nitridation (DPN) process, may be performed to nitride any exposed metal material of the metal layer 50, thereby forming a metal nitride layer 62 on the exposed surface of the metal layer 50. As shown in fig. 7, the metal nitride layer 62 may continuously cover the first sidewall 54a, the second sidewall 54b, and the top surface 54c of the storage node contact pad 54 and the top surface 52c of the storage node contact plug 52. Metal nitride layer 62 may have a uniform thickness T1. According to one embodiment of the invention, thickness T1 may be between approximately 10-40 angstroms.
The metal nitride layer 62 is a nitride of the metal material of the metal layer 50, that is, when the metal layer 50 includes tungsten (W), the metal nitride layer 62 may include tungsten nitride (WN). The metal nitride layer 62 may block the metal material of the storage node contact plug 52 and the storage node contact pad 54 from air, thereby reducing the occurrence of abnormal conditions caused by the reaction of the metal material with air gas (e.g., oxygen or moisture) during the process wait (Q-time), and further improving the quality of the storage node contact plug 52 and the storage node contact pad 54, particularly the quality of the electrical connection between the storage node contact pad 54 and the stacked capacitor (not shown) subsequently formed thereon.
Please refer to fig. 8 and fig. 9. Next, a deposition process may be performed to form a dielectric layer 70 on the substrate 10, such that the dielectric layer 70 completely covers the storage node contact pad 54 and fills the trench 51, and a planarization process P4 (e.g., a chemical mechanical polishing process) is performed to remove a portion of the dielectric layer 70 until the metal nitride layer 62 on the top surface 54c of the storage node contact pad 54 is exposed. The dielectric layer 70 is separated from direct contact with the storage node contact plug 52 and the storage node contact pad 54 by the metal nitride layer 62 region. The material of the dielectric layer 70 may include silicon oxide (SiO)2) Silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon doped carbon (NDC), low-k dielectric materials such as Fluorinated Silica Glass (FSG), silicon carbon oxide (SiCOH), spin-on-glass (spin-on glass), porous low-k dielectric materials, organic polymer dielectric materials, or combinations thereof, but is not limited thereto. The metal nitride layer 62 may isolate the storage node contact plugs 52 and the storage node contact pads 54 from a process gas used in a deposition process for forming the dielectric layer 70, thereby reducing the chance of the storage node contact plugs 52 and the storage node contact pads 54 reacting with the process gas.
The metal nitride layer 62 on the top surface 54c of the storage node contact pad 54 is also partially removed in the planarization process P4, so that the thickness T2 of the metal nitride layer 62 covering the top surface 54c is less than the thickness T1 of the metal nitride layer 62 covering the first sidewall 54a and the second sidewall 54b after the planarization process P4. According to one embodiment of the invention, thickness T2 may be between approximately 10-20 angstroms. As shown in fig. 9, the metal nitride layer 62 covering the storage node contact pad 54 may have an inverted U-shaped cross-sectional shape, wherein the metal nitride layer 62 on the first sidewall 54a is in direct contact with the top surface of the barrier layer 44 on the bit line 20, and may be vertically aligned with the sidewall of the barrier layer 44. Since the length of the second sidewall 54b is greater than the length of the first sidewall 54a, the length of the portion of the metal nitride layer 62 on the second sidewall 54b is also greater than the length of the portion on the first sidewall 54 a. The metal nitride layer 62 covering the top surface 52c of the storage node contact plug 52 is in direct contact with the sidewall of the barrier layer 44 on the sidewall of the bit line 20, and may be horizontally aligned with the top surface of the barrier layer 44.
Please refer to fig. 10. After the planarization process P4 is completed, the formation of the capacitor structure 80 over the substrate 10 may be continued. According to an embodiment of the present invention, the method for fabricating the capacitor structure 80 may include the following steps. First, a deposition process is performed to sequentially form an etch stop layer 72, a first sacrificial layer (not shown), a first support layer 74, a second sacrificial layer (not shown), and a second support layer 76 on the substrate 10. The materials of the etch stop layer 72, the first support layer 74 and the second support layer 76 are different from the materials of the first sacrificial layer (not shown) and the second sacrificial layer (not shown) so that the first sacrificial layer and the second sacrificial layer can be removed by a selective etching process in a subsequent step. According to an embodiment of the present invention, the first sacrificial layer and the second sacrificial layer may include silicon oxide, and the etch stop layer 72, the first support layer 74 and the second support layer 76 may include silicon nitride (SiN), silicon carbide nitride (SiCN), boron-doped silicon nitride (SiBN), silicon oxynitride (SiON), and the like, respectively, but are not limited thereto.
Next, an etching process may be performed to form a plurality of bottom electrode openings (not shown) penetrating through the second support layer 76, the second sacrificial layer, the first support layer 74, the first sacrificial layer, and the etch stop layer 72 and aligned with the respective storage node contact pads 54, and to penetrate the bottom of the bottom electrode openings through the metal nitride layer 62 directly above the storage node contact pads 54. Then, a deposition process is performed to form a bottom electrode layer 82 along the sidewalls and bottom surface of the bottom electrode opening, and then the bottom electrode layer 82 is used to provide structural support, and the second sacrificial layer and the first sacrificial layer are selectively etched away through the opening of the second support layer 76 and the opening of the first support layer 74 to form a cavity (not shown) between the second support layer 76, the first support layer 74 and the etch stop layer 72, exposing the sidewalls of the bottom electrode layer 82 and the surface of the etch stop layer 72. Next, a deposition process is performed to form a capacitor dielectric layer 84 along the sidewall of the bottom electrode layer 82, the surface of the first support layer 74, the surface of the second support layer 76, and the surface of the etch stop layer 72, and then a top electrode layer 86 is formed to fill the cavity between the second support layer 76, the first support layer 74, and the etch stop layer 72 and the gap between the bottom electrode layer 82, so as to obtain the capacitor structure 80. As shown in fig. 10, the bottom electrode layer 82 of the capacitor structure 80 is disposed directly above the storage node contact pad 54 and directly contacts the storage node contact pad 54 and the metal nitride layer 62. The etch stop layer 72 is separated from and does not directly contact the storage node contact pad 54 by the metal nitride layer 62 region.
The bottom electrode layer 82 and the top electrode layer 86 of the capacitor structure 80 may include a conductive material, such as a low-resistance metal material including, but not limited to, aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W). The capacitor dielectric layer 84 may comprise a dielectric material and may comprise a single layer or a multi-layer structure. According to one embodiment of the present invention, capacitor dielectric layer 84 may comprise a high dielectric constant (high-k) dielectric material, such as hafnium oxide (HfO)2) Hafnium silicon oxide (HfSiO)4) Hafnium silicon oxynitride (HfSiON), zinc oxide (ZrO)2) Titanium oxide (TiO)2) Alumina (Al)2O3) Tantalum oxide (Ta)2O5) And metal oxides such as zirconia-alumina-zirconia (ZAZ), or combinations thereof, but are not limited thereto. According to one embodiment of the present invention, capacitor dielectric layer 84 may comprise an ONO stack of silicon oxide, silicon nitride, silicon oxide.
Referring to fig. 11, a cross-sectional view of a dram according to another embodiment of the present invention is shown, which is substantially the same as the structure of the dram shown in fig. 9, and includes a substrate 10, a bit line 20, a storage node contact plug 52, a storage node contact pad 54, a metal nitride layer 62, and the like, which are not repeated herein. The embodiment is mainly to illustrate that the metal nitride layer 62 on the top surface 54c of the storage node contact pad 54 may be completely removed in the planarization process P4 to expose the top surface 54c of the storage node contact pad 54. Subsequently, an etch stop layer (e.g., etch stop layer 72 of fig. 10) and a capacitor structure (e.g., capacitor structure 80 of fig. 10) may be formed on substrate 10. In the present embodiment, since the metal nitride layer 62 on the top surface 54c of the storage node contact pad 54 is completely removed in the planarization process P4, the etch stop layer may be in direct contact with the storage node contact pad 54.
In summary, the dram of the present invention utilizes a nitridation process to form a metal nitride layer along the surface of the metal material of the storage node contact plug 52 and the storage node contact pad 54, and the metal nitride layer isolates the metal material of the storage node contact plug 52 and the storage node contact pad 54 from air or the process gas used in the subsequent process, thereby reducing the problem of deterioration caused by the reaction between the metal material of the storage node contact plug 52 and the storage node contact pad 54 and the air and/or the process gas, and improving the quality of electrical connection.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (20)
1. A dynamic random access memory, comprising:
a substrate;
an isolation structure disposed within the substrate to define a plurality of active regions in the substrate;
a plurality of bit lines disposed on the substrate;
a plurality of storage node contact plugs disposed between the bit lines and in direct contact with the active region;
a plurality of storage node contact pads respectively disposed on the storage node contact plugs and partially overlapping top surfaces of the bit lines, wherein the storage node contact pads include first sidewalls directly above the bit lines and second sidewalls directly above the storage node contact plugs; and
a metal nitride layer at least covering the first sidewall and the second sidewall of the storage node contact pad.
2. The dynamic random access memory of claim 1, further comprising a dielectric layer disposed between the storage node contact pads, and the dielectric layer and the storage node contact pads are separated by the metal nitride layer without direct contact.
3. The dynamic random access memory of claim 1, wherein the metal nitride layer comprises a nitride of a metal material of the storage node contact pad.
4. The dynamic random access memory of claim 3, wherein the storage node contact pad comprises tungsten and the metal nitride layer comprises tungsten nitride.
5. The dynamic random access memory according to claim 1, wherein a length of a portion of the metal nitride layer on the second sidewall is greater than a length of a portion of the metal nitride layer on the first sidewall.
6. The dynamic random access memory of claim 1, further comprising:
a semiconductor layer under the storage node contact plug and directly contacting the substrate; and
a barrier layer disposed between the semiconductor layer, the bit line, and the storage node contact plug.
7. The dynamic random access memory according to claim 6, wherein the portion of the metal nitride layer on the first sidewall is in direct contact with the top surface of the barrier layer and is aligned with the sidewall of the barrier layer in a vertical direction.
8. The dynamic random access memory of claim 6, wherein the metal nitride layer further covers a top surface of the storage node contact plug.
9. The dynamic random access memory of claim 6, wherein the storage node contact plug and the storage node contact pad are integrally formed and comprise the same material.
10. The dynamic random access memory according to claim 6, wherein the barrier layer comprises titanium nitride and the metal nitride layer comprises tungsten nitride.
11. The dram of claim 1, wherein the metal nitride layer further covers a top surface of the storage node contact pad and has an inverted U-shaped cross-sectional shape.
12. The dynamic random access memory of claim 11, wherein a thickness of a portion of the metal nitride layer on the top surface of the storage node contact pad is less than a thickness of a portion of the metal nitride layer on the first sidewall and the second sidewall.
13. A method for fabricating a dynamic random access memory, comprising:
providing a substrate;
forming a plurality of bit lines on the substrate;
forming a plurality of storage node contact plugs between the bit lines and a plurality of storage node contact pads respectively disposed on the storage node contact plugs, wherein the storage node contact pads partially overlap top surfaces of the bit lines and include a first sidewall directly above the bit lines and a second sidewall directly above the storage node contact plugs; and
and performing a nitridation manufacturing process to form a metal nitride layer at least covering the first side wall and the second side wall of the storage node contact pad.
14. The method of claim 13, further comprising forming a dielectric layer between the storage node contact pads, wherein the dielectric layer and the storage node contact pads are separated by the metal nitride layer without direct contact.
15. The method of claim 13, wherein the metal nitride layer comprises a nitride of the metal material of the storage node contact pad.
16. The method of claim 13, wherein the storage node contact pad comprises tungsten and the metal nitride layer comprises tungsten nitride.
17. The method of claim 13, wherein a length of the portion of the metal nitride layer on the second sidewall is greater than a length of the portion of the metal nitride layer on the first sidewall.
18. The method of claim 13, wherein the step of forming the storage node contact plug and the storage node contact pad comprises:
forming a plurality of contact holes between the bit lines to expose a portion of the substrate;
forming a semiconductor layer at the bottom of the contact hole;
forming a barrier layer along an upper surface of the semiconductor layer and sidewalls of the bit lines;
forming a metal layer, filling the contact hole and covering the bit line; and
and carrying out a recess manufacturing process to pattern the metal layer.
19. The method of claim 13, wherein the metal nitride layer further covers a top surface of the storage node contact pad and has an inverted U-shaped cross-sectional shape.
20. The method of claim 13, wherein the metal nitride layer further covers a top surface of the storage node contact plug.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114678362A (en) * | 2022-03-22 | 2022-06-28 | 福建省晋华集成电路有限公司 | dynamic random access memory |
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