CN114023757A - Split-gate flash memory device and method of making the same - Google Patents
Split-gate flash memory device and method of making the same Download PDFInfo
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- CN114023757A CN114023757A CN202111239220.6A CN202111239220A CN114023757A CN 114023757 A CN114023757 A CN 114023757A CN 202111239220 A CN202111239220 A CN 202111239220A CN 114023757 A CN114023757 A CN 114023757A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 49
- 238000005530 etching Methods 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 55
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 43
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 43
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 229920005591 polysilicon Polymers 0.000 claims description 19
- 235000012239 silicon dioxide Nutrition 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 6
- 125000001475 halogen functional group Chemical group 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 3
- 238000001259 photo etching Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
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Abstract
The invention provides a split-gate flash memory device and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: manufacturing a charge trapping dielectric layer; and etching and removing the charge trapping dielectric layer corresponding to the first target region, wherein the first target region is a region corresponding to the middle region of the grid electrode. The invention provides a new charge trapping type grid-divided flash memory device structure of 2-Bit/cell and its self-manufacturing process, different from NROM of the prior art, the structure removes the self-aligned etching of the charge trapping dielectric layer in the middle of the grid, can avoid the interference brought by the lateral movement of the stored charges between two bits under the action of the electric field, introduce the selective grid device to make the device can tolerate the over-erasing operation, in addition, the process is a self-aligned process, can further reduce the area of the flash memory unit, do not receive the restriction of the photoetching process at the same time.
Description
Technical Field
The invention relates to the technical field of flash memory device manufacturing, in particular to a split gate flash memory device and a manufacturing method thereof.
Background
The structure of a conventional 2-bit/cell charge trap flash memory (also known as NROM: Nitred ROM) is shown in FIG. 1. The operation is shown in table 1, where Program represents programming, Erase represents erasing, Read represents reading, Vg represents gate voltage, Vd represents drain voltage, and Vs represents source voltage. The device structure has the characteristics that the storage medium layer is a charge trapping type material Nitride, and a single grid structure can form a region for storing charges locally above a source-drain junction by utilizing the characteristic that trapped charges cannot move freely in the Nitride, so that 2-Bit storage is realized (refer to fig. 1). The device was programmed with Channel hot electrons (Channel hot electron), erased with Band-to-Band tunneling generated hot holes (Band-to-Band tunneling holes), and read with reverse read operation (see table 1).
TABLE 1
The device cannot tolerate over-erase effects. To avoid over-erase, more complex peripheral circuit designs are required to assist the device in not undergoing an over-erase operation.
Disclosure of Invention
The invention provides a split-gate flash memory device and a manufacturing method thereof, aiming at overcoming the defect that a charge trapping flash memory device in the prior art cannot bear over-erasure.
The invention solves the technical problems through the following technical scheme:
the invention provides a manufacturing method of a split-gate flash memory device, wherein the split-gate flash memory device comprises a two-bit/unit split-gate flash memory device, and the manufacturing method comprises the following steps:
manufacturing a charge trapping dielectric layer;
and etching and removing the charge trapping dielectric layer corresponding to the first target region, wherein the first target region is a region corresponding to the middle region of the grid electrode.
Preferably, the fabricating the charge-trapping dielectric layer comprises:
and manufacturing to form a first silicon oxide layer, and manufacturing to form a first silicon nitride layer above the first silicon oxide layer, wherein the first silicon oxide layer is a bottom gate dielectric layer, and the first silicon nitride layer is a charge trapping dielectric layer.
Preferably, the step of removing the charge-trapping dielectric layer corresponding to the first target region by etching comprises:
s11, sequentially forming a second silicon dioxide layer and a second silicon nitride layer above the first silicon nitride layer;
s12, etching and removing a second silicon nitride layer corresponding to a second target area, wherein the second target area is an area corresponding to the flash memory unit area, and the width of the second target area is greater than that of the first target area;
s13, depositing a polysilicon layer above the second silicon dioxide layer corresponding to the second target region and performing anisotropic etching to form a polysilicon side wall;
and S14, etching the second silicon dioxide layer and the first silicon nitride layer corresponding to the first target region in sequence in a self-alignment mode by taking the polysilicon side wall as a mask.
Preferably, the step of removing the charge-trapping dielectric layer corresponding to the first target region by etching further comprises:
and S15, etching and removing the polysilicon side wall by taking the second silicon nitride layer, the second silicon dioxide layer, the first silicon nitride layer and the first silicon oxide layer as stop layers.
Preferably, the step of removing the charge-trapping dielectric layer corresponding to the first target region by etching further comprises:
and S16, performing anisotropic etching to remove the second silicon oxide layer corresponding to the second target region and the first silicon oxide layer corresponding to the first target region.
Preferably, before the charge-trapping dielectric layer is formed, the method further comprises the steps of:
manufacturing and forming a P-type well on a substrate, wherein the P-type well is a medium-high voltage P-type well;
fabricating a charge-trapping dielectric layer includes:
and forming a charge trapping dielectric layer above the P-type well.
Preferably, after step S16, the manufacturing method further includes the following steps:
s21, depositing to form a gate dielectric layer, wherein the gate dielectric layer covers the side wall of the second silicon nitride layer corresponding to the second target area, the side wall of the second silicon oxide layer corresponding to the second target area, the upper surface of the first silicon nitride layer corresponding to the second target area, the side wall of the first silicon nitride layer corresponding to the first target area and the upper surface of the P-type well corresponding to the first target area;
s22, forming a selection gate polycrystalline silicon layer in the space surrounded by the gate dielectric layer, and doping the selection gate polycrystalline silicon layer;
s23, CMP (chemical mechanical polishing) is performed with the second silicon nitride layer as a stop layer, and thermal oxidation is performed to form an etch protection oxide layer on top of the select gate polysilicon layer.
Preferably, after step S23, the manufacturing method further includes the following steps:
s24, removing the second silicon nitride layer;
s25, etching the second silicon dioxide layer, the first silicon nitride layer and the first silicon oxide layer in sequence in a self-alignment mode by taking the etching protection oxide layer and the grid dielectric layer as masks;
and S26, performing LDD (lightly doped drain)/Halo (Halo) implantation in the P-type well to form a lightly doped drain region, wherein the lightly doped drain region extends to the lower part of the first silicon oxide layer.
Preferably, after step S26, the manufacturing method further includes the following steps:
depositing and etching to form a first side wall dielectric layer and a second side wall dielectric layer, wherein the first side wall dielectric layer is L-shaped, and the second side wall dielectric layer is L-shaped;
and implanting impurities below the lightly doped drain region to form a source-drain heavily doped region.
The invention provides a split-gate flash memory device, which is a two-bit/unit split-gate flash memory device and comprises a charge trapping dielectric layer, wherein the charge trapping dielectric layer comprises a notch, and the notch is arranged in an area corresponding to the middle area of a grid electrode.
Preferably, the split-gate flash memory device is manufactured by the manufacturing method of the split-gate flash memory device.
The positive progress effects of the invention are as follows: the invention provides a new charge trapping type grid-divided flash memory device structure of 2-Bit/cell and its self-manufacturing process, different from NROM of the prior art, the structure removes the self-aligned etching of the charge trapping dielectric layer in the middle of the grid, can avoid the interference brought by the lateral movement of the stored charges between two bits under the action of the electric field, introduce the selective grid device to make the device can tolerate the over-erasing operation, in addition, the process is a self-aligned process, can further reduce the area of the flash memory unit, do not receive the restriction of the photoetching process at the same time.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a schematic structural diagram of an NROM in the prior art.
Fig. 2 is a flow chart of a method for manufacturing a split-gate flash memory device according to a preferred embodiment of the invention.
Fig. 3 is a schematic diagram illustrating the preparation of a P-type well in the method for manufacturing a split-gate flash memory device according to a preferred embodiment of the invention.
Fig. 4 is a schematic diagram of etching by using the polysilicon sidewall as a mask in the method for manufacturing the split-gate flash memory device according to a preferred embodiment of the invention.
Fig. 5 is a schematic diagram of the method for manufacturing a split-gate flash memory device according to a preferred embodiment of the invention after removing the polysilicon sidewalls.
Fig. 6 is a schematic diagram illustrating etching of the second silicon oxide layer and the first silicon oxide layer in the method for manufacturing a split-gate flash memory device according to a preferred embodiment of the invention.
Fig. 7 is a schematic diagram illustrating the formation of an etching protection oxide layer in the method for manufacturing a split-gate flash memory device according to a preferred embodiment of the invention.
Fig. 8 is a schematic diagram illustrating the fabrication of a split-gate flash memory device to form a lightly doped drain region according to a preferred embodiment of the present invention.
Fig. 9 is a schematic diagram of forming a source/drain heavily doped region by the manufacturing method of the split gate flash memory device according to a preferred embodiment of the present invention.
FIG. 10 is a diagram illustrating the Ibl-Vwl curve of a split gate flash memory device according to a preferred embodiment of the present invention.
Detailed Description
The present invention will be more clearly and completely described in the following description of a preferred embodiment thereof, taken in conjunction with the accompanying drawings.
The embodiment provides a manufacturing method of a split gate flash memory device. Referring to fig. 2, the manufacturing method includes at least the steps of:
s1, forming P-type trap on the substrate. The P-well is a medium-high voltage P-well.
And S2, manufacturing a charge trapping dielectric layer.
And S3, etching and removing the charge trapping dielectric layer corresponding to the first target area. The first target region is a region corresponding to a middle region of the gate electrode.
In particular implementation, in step S1, referring to fig. 3, P-type well 101 is implanted on the substrate, where P-type well 101 is a medium-high voltage P-type well.
As an alternative implementation, referring to fig. 4, in step S2, a first silicon oxide layer 102 is formed over the P-well 101, a first silicon nitride layer 103 is formed over the first silicon oxide layer 102, the first silicon oxide layer 102 is a bottom gate dielectric layer, and the first silicon nitride layer 103 is a charge-trapping dielectric layer.
Next, referring to fig. 4, in step S3, a second silicon oxide layer 501 and a second silicon nitride layer 502 are sequentially formed on the first silicon nitride layer 103. Then, the second silicon nitride layer 502 corresponding to a second target region is etched and removed, the second target region is a region corresponding to the flash memory unit region, and the width of the second target region is greater than that of the first target region. In specific implementation, the flash memory cell region is defined by photolithography, and the second silicon nitride layer 502 corresponding to the flash memory cell region is removed by etching. Next, a polysilicon layer is deposited over the second silicon oxide layer 501 corresponding to the second target region and anisotropically etched to form polysilicon sidewalls 503. And sequentially etching the second silicon dioxide layer 501 and the first silicon nitride layer 103 corresponding to the first target region in a self-alignment manner by taking the polysilicon side wall 503 as a mask.
Then, referring to fig. 5, the polysilicon spacers 503 are etched and removed by using the second silicon nitride layer 502, the second silicon oxide layer 501, the first silicon nitride layer 103 and the first silicon oxide layer 102 as stop layers. In specific implementation, the polysilicon sidewall 503 is removed by wet etching.
Next, referring to fig. 6, anisotropic etching is performed to remove the second silicon oxide layer 501 corresponding to the second target region and the first silicon oxide layer 102 corresponding to the first target region.
Then, referring to fig. 7, a gate dielectric layer 105 is deposited, and the gate dielectric layer 105 covers a sidewall of the second silicon nitride layer 502 corresponding to the second target region, a sidewall of the second silicon oxide layer 501 corresponding to the second target region, an upper surface of the first silicon nitride layer 103 corresponding to the second target region, a sidewall of the first silicon nitride layer 103 corresponding to the first target region, and an upper surface of the P-well corresponding to the first target region.
Then, a selection gate polysilicon layer 106 is formed in the space surrounded by the gate dielectric layer 105, and the selection gate polysilicon layer 106 is doped.
Next, CMP is performed with the second silicon nitride layer 502 as a stop layer, and thermal oxidation is performed to form the etch protection oxide layer 107 on top of the select gate polysilicon layer 106.
Next, referring to fig. 8, the second silicon nitride layer 502 is removed. Then, the second silicon oxide layer 501, the first silicon nitride layer 103, and the first silicon oxide layer 102 are sequentially etched in a self-aligned manner by using the etching protection oxide layer 107 and the gate dielectric layer 105 as masks.
Then, LDD/Halo implantation is performed in the P-well to form a lightly doped drain region 109, the lightly doped drain region 109 extending to below the first silicon oxide layer 102.
Next, referring to fig. 9, a first sidewall dielectric layer 104 and a second sidewall dielectric layer 108 are deposited and etched. The first sidewall dielectric layer 104 is L-shaped and the second sidewall dielectric layer 108 is L-shaped. Then, impurities are implanted under the lightly doped drain region 109 to form a source-drain heavily doped region 110.
Referring to fig. 9, the split-gate flash memory device is a two-bit/cell split-gate flash memory device, and the split-gate flash memory device includes a charge trapping dielectric layer, where the charge trapping dielectric layer includes a notch, and the notch is disposed in an area corresponding to a middle area of a gate. The split-gate flash memory device is manufactured by the manufacturing method of the split-gate flash memory device of the embodiment.
Fig. 10 shows Ibl (bit line current) -Vwl (word line voltage) curves of simulation results of the split gate flash memory device, in which the horizontal axis represents Vwl in V, the vertical axis represents Ibl in a/um, the Program state represents the Program state, and the Erase state represents the Erase state. The curve shows: the threshold voltage window of the split-gate flash memory device is 1.7V, and the difference between the read currents (Ir01 and Ir10) of the Program state and the Erase state under the worst condition is 6 orders of magnitude.
The embodiment provides a split-gate flash memory device and a manufacturing method thereof, and the split-gate flash memory device belongs to a novel charge trapping type split-gate flash memory device structure of 2-bit/cell. The structure has two bits/unit and is realized by using a self-alignment process, so that the integration level is improved. Different from NROM, the split-gate flash memory device of the embodiment removes the charge trapping dielectric layer by self-aligned etching in the middle of the gate, can avoid the interference caused by the transverse movement of the stored charges between two bits under the action of an electric field, and can tolerate over-erasing operation by introducing the select gate device. In addition, the manufacturing method of the split-gate flash memory device of the embodiment is a self-aligned process in the etching process, so that the area of the flash memory cell can be further reduced, and meanwhile, the manufacturing method is not limited by the etching process. On the other hand, the manufacturing method of the split-gate flash memory device of the embodiment adopts the sacrificial polysilicon side wall to realize the self-aligned structure, so that the area of the flash memory unit can be further reduced, and meanwhile, the manufacturing method is not limited by the photoetching process.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.
Claims (11)
1. A method of manufacturing a split-gate flash memory device, wherein the split-gate flash memory device comprises a two-bit/cell split-gate flash memory device, the method comprising:
manufacturing a charge trapping dielectric layer;
and etching and removing the charge trapping dielectric layer corresponding to a first target region, wherein the first target region is a region corresponding to the middle region of the grid electrode.
2. The method of manufacturing a split-gate flash memory device of claim 1, wherein said fabricating a charge-trapping dielectric layer comprises:
and manufacturing to form a first silicon oxide layer, and manufacturing to form a first silicon nitride layer above the first silicon oxide layer, wherein the first silicon oxide layer is a bottom gate dielectric layer, and the first silicon nitride layer is the charge trapping dielectric layer.
3. The method of claim 2, wherein the etching away the charge-trapping dielectric layer corresponding to the first target region comprises:
s11, sequentially forming a second silicon oxide layer and a second silicon nitride layer above the first silicon nitride layer;
s12, etching and removing the second silicon nitride layer corresponding to a second target area, wherein the second target area is an area corresponding to a flash memory unit area, and the width of the second target area is greater than that of the first target area;
s13, depositing a polysilicon layer above the second silicon dioxide layer corresponding to the second target region and performing anisotropic etching to form a polysilicon side wall;
and S14, sequentially etching the second silicon dioxide layer and the first silicon nitride layer corresponding to the first target region in a self-alignment mode by taking the polycrystalline silicon side wall as a mask.
4. The method of claim 3, wherein the etching away the charge-trapping dielectric layer corresponding to the first target region further comprises:
and S15, etching and removing the polysilicon side wall by taking the second silicon nitride layer, the second silicon dioxide layer, the first silicon nitride layer and the first silicon oxide layer as stop layers.
5. The method of claim 4, wherein the etching away the charge-trapping dielectric layer corresponding to the first target region further comprises:
and S16, performing anisotropic etching to remove the second silicon oxide layer corresponding to the second target region and the first silicon oxide layer corresponding to the first target region.
6. The method of manufacturing a split-gate flash memory device according to claim 5, wherein before said fabricating a charge-trapping dielectric layer, said method further comprises the steps of:
manufacturing and forming a P-type well on a substrate, wherein the P-type well is a medium-high voltage P-type well;
the manufacturing of the charge trapping dielectric layer comprises the following steps:
and forming the charge trapping dielectric layer above the P-type well.
7. The method of manufacturing a split-gate flash memory device according to claim 6, wherein after the step S16, the method further comprises the steps of:
s21, depositing to form a gate dielectric layer, wherein the gate dielectric layer covers the side wall of the second silicon nitride layer corresponding to the second target area, the side wall of the second silicon dioxide layer corresponding to the second target area, the upper surface of the first silicon nitride layer corresponding to the second target area, the side wall of the first silicon nitride layer corresponding to the first target area and the upper surface of the P-type well corresponding to the first target area;
s22, forming a selection gate polycrystalline silicon layer in the space surrounded by the gate dielectric layer, and doping the selection gate polycrystalline silicon layer;
and S23, performing CMP by taking the second silicon nitride layer as a stop layer, and performing thermal oxidation to form an etching protection oxide layer on the top end of the selection gate polycrystalline silicon layer.
8. The method of manufacturing a split-gate flash memory device according to claim 7, wherein after the step S23, the method further comprises the steps of:
s24, removing the second silicon nitride layer;
s25, etching the second silicon dioxide layer, the first silicon nitride layer and the first silicon oxide layer in sequence in a self-aligning mode by taking the etching protection oxide layer and the grid dielectric layer as masks;
and S26, performing LDD/Halo implantation in the P-type well to form a lightly doped drain region, wherein the lightly doped drain region extends to the lower part of the first silicon oxide layer.
9. The method of manufacturing a split-gate flash memory device according to claim 8, wherein after the step S26, the method further comprises the steps of:
depositing and etching to form a first side wall dielectric layer and a second side wall dielectric layer, wherein the first side wall dielectric layer is L-shaped, and the second side wall dielectric layer is L-shaped;
and injecting impurities below the lightly doped drain region to form a source-drain heavily doped region.
10. The split-gate flash memory device is characterized in that the split-gate flash memory device is a two-bit/unit split-gate flash memory device, the split-gate flash memory device comprises a charge trapping dielectric layer, the charge trapping dielectric layer comprises a notch, and the notch is arranged in an area corresponding to the middle area of a grid electrode.
11. The split-gate flash memory device according to claim 10, wherein the split-gate flash memory device is manufactured by the method for manufacturing a split-gate flash memory device according to any one of claims 1 to 9.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1444774A (en) * | 2000-07-28 | 2003-09-24 | 因芬尼昂技术股份公司 | Method for producing multi-bit memory cell |
| CN102593060A (en) * | 2011-01-07 | 2012-07-18 | 上海宏力半导体制造有限公司 | Split-gate flash memory unit and manufacturing method thereof |
| CN102800675A (en) * | 2011-05-25 | 2012-11-28 | 中国科学院微电子研究所 | Charge trapping non-volatile memory and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1444774A (en) * | 2000-07-28 | 2003-09-24 | 因芬尼昂技术股份公司 | Method for producing multi-bit memory cell |
| CN102593060A (en) * | 2011-01-07 | 2012-07-18 | 上海宏力半导体制造有限公司 | Split-gate flash memory unit and manufacturing method thereof |
| CN102800675A (en) * | 2011-05-25 | 2012-11-28 | 中国科学院微电子研究所 | Charge trapping non-volatile memory and manufacturing method thereof |
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