CN114019736B - Display substrate and display device - Google Patents

Abstract

The present invention provides a display substrate including: the display device comprises an array substrate, a color film substrate, a liquid crystal layer, a grid driving circuit and frame sealing glue, wherein projections of first parts and second parts of a plurality of clock signal lines on a substrate are overlapped, and an overlapping area is formed in the overlapping area; a first inorganic protective layer and a second inorganic protective layer covering the metal oxide thin film transistor, and an organic layer between the first inorganic protective layer and the second inorganic protective layer; the region between the organic layer and one of the side surfaces of the substrate is a hollowed-out region, so that the frame sealing glue completely covers the first inorganic protective layer and the second inorganic protective layer, and part of the region covers the organic layer or does not cover the organic layer at all. According to the invention, according to the relative positions of the organic layer, the frame sealing glue area and the overlapping area, the corrosion risk of the peripheral metal wiring is reduced by arranging the hollowed-out area on the organic layer, changing the material of the peripheral metal wiring and changing the material of the first inorganic protective layer.

Description

Display substrate and display device

Technical field

The present invention relates to the field of display technology, and in particular, to a display substrate and a display device.

Background technique

In the field of display technology, TFT (Thin Film Transistor, thin film transistor) is a key device for controlling pixel switching and signal transmission, and its performance is particularly important. At present, active layer materials mainly include three categories: amorphous silicon, metal oxide, and low-temperature polysilicon. Among them, metal oxide TFTs are widely used in products with high refresh rates, high PPI (Pixels Per Inch), and high transmittance due to their high electron mobility, low off-state current, and good uniformity.

However, metal oxide TFTs are relatively sensitive to impurities such as hydrogen and oxygen. Such impurities have a greater impact on the characteristics of the TFT, and in severe cases may damage the normal operation of the gate drive circuit or the TFT in the display area. Improving the sealing performance of the display panel frame sealant area is one of the key factors.

Contents of the invention

Embodiments of the present invention provide a display substrate and a display device that can improve the high temperature and high humidity resistance of metal oxide products and reduce the risk of corrosion of peripheral metal wiring.

A first aspect of the present invention provides a display substrate, including:

The array substrate and the color filter substrate, the liquid crystal layer located between the array substrate and the color filter substrate, the gate drive circuit and the frame sealing glue located in the peripheral area of the display substrate, the gate drive circuit includes a plurality of metal oxide Thin film transistor;

The array substrate includes a base substrate, the base substrate includes an upper surface and four sides;

A plurality of clock signal lines located on the base substrate, each clock signal line includes a first part and a second part arranged in different layers, the first part and the second part are connected through via holes, and the second part is connected to The metal oxide thin film transistor in the gate drive circuit is connected;

The projection of the first part and the second part of the plurality of clock signal lines on the substrate overlap, and the overlapping area forms an overlapping area;

a first inorganic protective layer and a second inorganic protective layer covering the metal oxide thin film transistor, and an organic layer located between the first inorganic protective layer and the second inorganic protective layer;

The first inorganic protective layer and the second inorganic protective layer extend from the area covering the metal oxide thin film transistor to the sealant area and are flush with one of the side surfaces of the base substrate;

The first inorganic protective layer and the second inorganic protective layer are at least part of the frame sealing glue area and are continuous areas without hollows on the entire surface;

The area between the organic layer and one of the side surfaces of the base substrate is a hollow area, so that the frame sealing glue completely covers the first inorganic protective layer and the second inorganic protective layer, and partially covers The organic layer may or may not cover the organic layer at all.

Optionally, the second portion of the clock signal line is located above the first portion of the clock signal line and closer to the organic layer.

Optionally, the clock signal line includes at least two layers, one of which is a metal line, and the other is a protective layer of the metal line, and the protective layer is an alloy.

Optionally, there is a second spacing between the overlap closest to one of the side surfaces of the substrate substrate and one of the side surfaces of the substrate substrate. When the second spacing is greater than or equal to 1000um, the overlap area and The area between the overlapping area and one of the side surfaces of the base substrate is a hollow area.

Optionally, there is a second spacing between the overlap closest to one of the side surfaces of the substrate substrate and one of the side surfaces of the substrate substrate. When the second spacing is less than 1000um, the overlap area And the area between the overlapping area and one of the side surfaces of the base substrate is a hollow area, and the alloy of the protective layer of the clock signal line is molybdenum nickel titanium.

Optionally, there is a first spacing between the organic layer and one of the side surfaces of the base substrate. When the first spacing is greater than or equal to 600um, the organic layer and one of the side surfaces of the base substrate are The area between the above-mentioned sides is the hollowed-out area,

The organic layer in the overlapping area is provided with a hollow area, and the alloy of the protective layer of the clock signal line is molybdenum nickel titanium.

Optionally, there is a first spacing between the organic layer and one of the side surfaces of the base substrate. When the first spacing is less than 600um, the organic layer and one of the side surfaces of the base substrate are The area between the sides is the hollowed out area,

The organic layer in the overlapping area is provided with a hollow area. The alloy of the protective layer of the clock signal line is molybdenum nickel titanium. The first inorganic protective layer includes at least two layers, and the outer layer close to the organic layer is nitrogen. Silicone, the bottom layer away from the organic layer is silicon oxide, and the second part of the clock signal line is located under the silicon oxide layer and in contact with the silicon oxide layer.

Optionally, the metal oxide thin film transistor includes:

a gate metal layer located on the upper surface of the base substrate;

a gate insulation layer covering the gate metal layer;

an active layer located on the side of the gate insulating layer away from the base substrate;

Source and drain metal layers located above the active layer.

Optionally, the clock signal line and the source and drain metal layers are made of the same material.

A second aspect of the present invention provides a display device, including the above-mentioned display substrate.

Embodiments of the present invention have the following beneficial effects:

The present invention can improve the resistance of metal oxide products by hollowing out the area between the organic layer and one of the side surfaces of the base substrate according to the relative positions of the organic layer, the frame sealant area, and the overlapping area. High temperature and high humidity, reducing the risk of corrosion of peripheral metal wiring.

Description of the drawings

Figure 1 is a structural diagram of a display substrate in the related art;

Figure 2 is a schematic diagram of corrosion occurring at an overlap in the related art;

Figure 3 is a schematic diagram of the connection position between the clock signal line and the gate drive circuit in the related art;

Figure 4 is a schematic cross-sectional view of the first display substrate provided by an embodiment of the present invention;

FIG. 5 is a schematic cross-sectional view of a second display substrate according to an embodiment of the present invention.

Reference signs

1 base substrate

2a first gate insulating layer

2b second gate insulating layer

3 The first inorganic protective layer

3a The first inorganic protective layer is away from the bottom layer of the organic layer

3b The first inorganic protective layer is close to the top layer of the organic layer

4 Second inorganic protective layer

5 organic layer

6 frame sealant

7 liquid crystal layer

8 upper panel

9 black matrix

10 color film

11a The first part of the clock signal line

11b The second part of the clock signal line

L1 first distance

L2 second distance

Detailed ways

In order to make the technical problems, technical solutions and advantages to be solved by the embodiments of the present invention clearer, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

Due to the need for stable TFT characteristics in metal oxide products, the insulating layer located above the active layer generally uses an oxide inorganic layer. However, the water resistance of oxide inorganic materials is poorer than that of nitride inorganic layers, and external water vapor can easily enter the active layer. This causes the metal traces to corrode under the action of H or O or the active layer to fail under the action of H and O.

The setting of a film layer near the frame sealant in the peripheral area of the display panel can effectively reduce the entry of impurities such as peripheral water vapor.

Figure 1 is a structural diagram of a display substrate in the related art. As shown in Figure 1, the display substrate includes an array substrate and a color filter substrate, and a liquid crystal layer 7 located between the array substrate and the color filter substrate. The frame sealing glue 6 of the liquid crystal layer;

Wherein, the array substrate includes a base substrate 1. The base substrate 1 includes an upper surface and four side surfaces. The four side surfaces are cutting surfaces after cutting the motherboard. The base substrate may be a glass substrate or quartz. substrate;

The TFT is located on the base substrate 1. This embodiment is introduced by taking the TFT as a bottom gate structure as an example;

The TFT includes a gate metal layer located on the base substrate 1, wherein the gate metal layer includes at least two layers, one of which is a metal line, and the other is a protective layer of the metal line, and the protective layer is an alloy, The alloy is molybdenum niobium, and the metal wire is copper wire or aluminum wire;

The first gate insulating layer 2a covering the gate metal layer, the first gate insulating layer 2a is a nitride inorganic material, such as silicon nitride;

An active layer located on the side of the first gate insulating layer 2a away from the base substrate 1, wherein the material of the active layer is metal oxide;

The second gate insulating layer 2b covering the active layer, the second gate insulating layer 2b is an oxide inorganic material, such as silicon oxide;

A source-drain metal layer located above the second gate insulating layer 2b, wherein the source-drain metal layer includes at least two layers, one of which is a metal line, and the other is a protective layer for the metal line, and the protective layer is an alloy. , the alloy is molybdenum niobium, the metal wire is copper wire or aluminum wire, the source and drain metal layers and the gate metal layer are made of the same material;

A first inorganic protective layer 3 covering the source and drain metal layers for protecting the TFT. The first inorganic protective layer 3 includes one or more layers, and the one or more layers at least include a silicon oxide film layer, The first inorganic protective layer shown in Figure 1 includes a silicon oxide film layer;

A second inorganic protective layer 4 covering the first inorganic protective layer 3. The second inorganic protective layer 4 includes an inorganic nitride film layer, for example, a silicon nitride or silicon oxynitride film layer;

An organic layer 5 is located between the first inorganic protective layer 3 and the second inorganic protective layer 4. The organic layer 5 is used between the first inorganic protective layer 3 and the second inorganic protective layer 4. Play a flattening role;

Wherein, the display substrate also includes a plurality of clock signal lines located on the substrate substrate. Each clock signal line includes a first part 11a and a second part 11b arranged in different layers. The first part 11a and the second part 11b is connected through a via hole, the second part 11b is connected to the metal oxide thin film transistor in the gate driving circuit, the first part 11a and the second part 11b of the plurality of clock signal lines are on the base substrate 1 The projection has overlap, and the area where the overlap occurs forms an overlap area;

A gate drive circuit is provided in the peripheral area of the display substrate. The gate drive circuit includes a plurality of metal oxide thin film transistors. The second part 11b of the clock signal line is connected to the metal oxide in the gate drive circuit. Thin film transistor connection;

The above display panel introduces the array substrate. The display panel also includes a color filter substrate and a liquid crystal layer 7 located between the color filter substrates. The color filter substrate includes the upper panel 8 of the display panel, a black matrix 9 and a color filter 10 .

The liquid crystals in the liquid crystal layer can achieve different degrees of deflection under different voltages, thereby achieving different transmittances. When light passes through the liquid crystal layer, color display can be achieved with the color filter substrate.

Referring to Figure 1, external water vapor invades the display substrate from the gap between the first inorganic protective layer 3 and the second inorganic protective layer 4. The organic layer 5 has extended to the frame sealant area and covers the overlapping area. Since the organic layer 5 easily absorbs water , and the material of the first inorganic protective layer 3 is silicon oxide with poor water resistance. Therefore, water vapor reaches the source and drain metal layers. The protective layer material of the source-drain metal layer is molybdenum-niobium, which is more susceptible to corrosion by H or O than molybdenum-nickel-titanium. Therefore, the metal traces of the source-drain metal layer (such as the second part of the clock signal line) are prone to corrosion and will The overlapping area creates an electrical connection with the first portion of the clock signal line, causing a short circuit.

Referring to FIG. 1 , the portion of the second portion 11 b of the clock signal line and the first portion 11 a of the clock signal line located in the sealant area have an overlapping area perpendicular to the substrate 1 . In the overlapping area, the second portion 11b of the clock signal line is corroded under the action of H or O, wherein the first portion 11a of the clock signal line and the second portion 11b of the clock signal line are located on different layers.

Figure 2 is a schematic diagram of corrosion occurring at an overlap in the related art. As shown in Figure 2, the first part 11a of the first clock signal line and the second part 11b of the first clock signal line are connected through a via hole. The first part 11a of the clock signal line is connected to the metal oxide thin film transistor of the gate driving circuit and has an intersection with the projection of the first part of the second, third and fourth clock signal lines on the substrate 1. Stack. The first part 11a of the second clock signal line is connected to the second part 11b of the second clock signal line through a via hole, and the first part 11a of the second clock signal line is connected to the metal oxide thin film transistor of the gate drive circuit. The process overlaps with the projection of the first part of the third and fourth clock signal lines on the substrate 1 .

The first part 11a of the first clock signal line has no overlap with the second part 11b of the first clock signal line, and the first part 11a of the second clock signal line has no overlap with the second part 11b of the first clock signal line. The overlapping area is small, so the first part of the first clock signal line and the second clock signal line have not yet been corroded when water vapor accumulates. Since the first part 11a of the third clock signal line overlaps with the second part 11b of the first and second clock signal lines, it is corroded under the action of H or O, and the first clock signal line and the second clock signal line 11a are corroded under the action of H or O. When the signal line transmits the clock signal to the gate drive circuit, a short circuit occurs where the third clock signal line is corroded. That is, for the one or two clock signal lines close to the outer edge of the display substrate, the short circuit is not considered for the time being. , the clock signal line with short circuit usually starts from the third clock signal line.

Figure 3 is a schematic diagram of the connection position between the clock signal line and the gate drive circuit in the related art. As shown in Figure 3, the first clock signal line CLK1, the second clock signal line CLK2 and the third clock signal line CLK3 are connected to The output of the gate drive circuit GOA provides a drive voltage for the gate of the metal oxide thin film transistor located in the active display area (Active Area, AA). The second portion of the first clock signal line CLK1 has an overlap with the first portions of the second clock signal line CLK2 and the third clock signal line CLK3.

It should be noted that since high-frequency signals are transmitted on the clock signal line, heat is easily generated at the overlap. Therefore, corrosion is more likely to occur under the action of H or O. Due to the transmission of DC signals on the DC low-voltage signal line VSS of the gate drive circuit, the heating phenomenon is not obvious between the DC low-voltage signal line and the DC low-voltage signal lead, and the DC low-voltage signal line and the DC low-voltage signal lead overlap. The phenomenon of corrosion is also not obvious. Therefore, the present invention does not consider the short circuit of the DC low-voltage signal line VSS for the time being.

In order to solve the problem in the related art that metal traces in the peripheral area of a display substrate are prone to corrosion, the present invention provides a display substrate and a display device.

The display substrate provided by the embodiment of the present invention includes:

The array substrate and the color filter substrate, the liquid crystal layer located between the array substrate and the color filter substrate, the gate drive circuit and the frame sealing glue located in the peripheral area of the display substrate, the gate drive circuit includes a plurality of metal oxide Thin film transistor; characterized in that,

The array substrate includes a base substrate, the base substrate includes an upper surface and four sides;

A plurality of clock signal lines located on the base substrate, each clock signal line includes a first part and a second part arranged in different layers, the first part and the second part are connected through via holes, and the second part is connected to The metal oxide thin film transistor in the gate drive circuit is connected;

The projection of the first part and the second part of the plurality of clock signal lines on the substrate overlap, and the overlapping area forms an overlapping area;

a first inorganic protective layer and a second inorganic protective layer covering the metal oxide thin film transistor, and an organic layer located between the first inorganic protective layer and the second inorganic protective layer;

The first inorganic protective layer and the second inorganic protective layer extend from the area covering the metal oxide thin film transistor to the sealant area and are flush with one of the side surfaces of the base substrate;

The first inorganic protective layer and the second inorganic protective layer are at least part of the frame sealing glue area and are continuous areas without hollows on the entire surface;

The area between the organic layer and one of the side surfaces of the base substrate is a hollow area, so that the frame sealing glue completely covers the first inorganic protective layer and the second inorganic protective layer, and partially covers The organic layer may or may not cover the organic layer at all.

Figure 4 is a schematic cross-sectional view of a first display substrate provided by an embodiment of the present invention. The display substrate provided by an embodiment of the present invention includes:

The array substrate and the color filter substrate, the liquid crystal layer 7 located between the array substrate and the color filter substrate, the gate drive circuit and the frame sealant 6 located in the peripheral area of the display substrate, the gate drive circuit includes a plurality of Metal oxide thin film transistors;

The array substrate includes a base substrate 1, which includes an upper surface and four side surfaces, and the four side surfaces are cutting surfaces after cutting the motherboard;

There are a plurality of clock signal lines located on the base substrate 1. Each clock signal line includes a first part 11a and a second part 11b arranged in different layers. The first part 11a and the second part 11b are connected through via holes. The second part 11b is connected to the metal oxide thin film transistor in the gate drive circuit;

The projection of the first part 11a and the second part 11b of the plurality of clock signal lines on the substrate 1 overlaps, and the overlapping area forms an overlapping area;

The first inorganic protective layer 3 and the second inorganic protective layer 4 covering the metal oxide thin film transistor, and the organic layer 5 located between the first inorganic protective layer 3 and the second inorganic protective layer 4;

Wherein, the first inorganic protective layer 3 includes a bottom layer 3a far away from the organic layer 5 and a top layer 3b close to the organic layer 5;

The first inorganic protective layer 3 and the second inorganic protective layer 4 extend from the area covering the metal oxide thin film transistor to the frame sealant area and are flush with one of the side surfaces of the base substrate 1;

The first inorganic protective layer 3 and the second inorganic protective layer 4 are at least part of the frame sealing glue area and are continuous areas without hollows on the entire surface;

The area between the organic layer 5 and one of the side surfaces of the base substrate 1 is a hollow area, so that the frame sealing glue 6 completely covers the first inorganic protective layer 3 and the second inorganic protective layer 4. Partial area covers the organic layer 5 or does not cover the organic layer 5 at all.

Optionally, the metal oxide thin film transistor includes:

a gate metal layer located on the upper surface of the base substrate;

a gate insulation layer covering the gate metal layer;

an active layer located on the side of the gate insulating layer away from the base substrate;

Source and drain metal layers located above the active layer.

Referring to Figure 4, this embodiment is introduced by taking a TFT as a bottom-gate structure as an example. The TFT includes a gate metal layer located on the base substrate 1;

The first gate insulating layer 2a covering the gate metal layer, the first gate insulating layer 2a is a nitride inorganic material, such as silicon nitride;

The active layer located on the side of the first gate insulating layer 2a away from the base substrate 1, and the active layer material is metal oxide;

The second gate insulating layer 2b covering the active layer, the second gate insulating layer 2b is an oxide inorganic material, such as silicon oxide;

A source-drain metal layer located above the second gate insulating layer 2b, wherein the source-drain metal layer includes at least two layers, one of which is a metal line, and the other is a protective layer for the metal line, and the protective layer is an alloy. , the alloy is molybdenum niobium, the metal wire is copper wire or aluminum wire, the source and drain metal layers and the gate metal layer are made of the same material.

Optionally, the second portion 11b of the clock signal line is located above the first portion 11a of the clock signal line and closer to the organic layer 5 .

Optionally, there is a second spacing between the overlap closest to one of the side surfaces of the substrate substrate and one of the side surfaces of the substrate substrate. When the second spacing is greater than or equal to 1000um, the overlap area and The area between the overlapping area and one of the side surfaces of the base substrate is a hollow area.

Among them, in the display substrate shown in Figure 4, the organic layer 5 has extended to the frame sealant area, but does not cover the overlapping area.

As shown in Figure 4, the overlap closest to one of the side surfaces of the base substrate and where the short circuit phenomenon occurs is located on the third clock signal line. One of the side surfaces of the base substrate is connected to the third clock signal line. There is a second spacing L2 between the lines. When the second spacing L2 is greater than or equal to 1000um, the overlap area and the area between the overlap area and one side of the base substrate are hollow areas, that is, the The organic layer 5 in the overlapping area and the area between the overlapping area and one side of the base substrate is dug out. At this time, the distance from the water vapor to the overlapping area is not very small, and it is only necessary to dig out the overlapping area and the organic layer between the overlapping area and one side of the substrate, thereby making the organic layer 5 The further away from one side of the base substrate, the farther away the organic layer 5 is from absorbing water. The organic layer 5 absorbs less water vapor, and the moisture that penetrates from the organic layer 5 to the gate metal layer or the source and drain metal layers is reduced, thereby reducing the moisture at the overlap to prevent short circuits at the overlap.

Furthermore, if the distance from the water vapor to the overlapping area is not very small, there is no need to change the film structure of the display substrate, and there is no need to change the material of the film layer with poor waterproof performance in the film structure. The distance between the organic layer 5 and one side surface of the base substrate only needs to be increased.

Furthermore, when the second distance L2 is less than 1000um, that is, the distance for water vapor to reach the overlapping area is smaller than when L2 is greater than or equal to 1000um, then the display substrate needs to further enhance its waterproofing capability and the protective layer of the source and drain metal layers needs to be protected. Materials are changed to increase water resistance.

Optionally, there is a second spacing between the overlap closest to one of the side surfaces of the substrate substrate and one of the side surfaces of the substrate substrate. When the second spacing is less than 1000um, the overlap area And the area between the overlapping area and one of the side surfaces of the base substrate is a hollow area, and the alloy of the protective layer of the clock signal line is molybdenum nickel titanium.

In the related art, the source and drain metal layer includes at least two layers, one of which is a metal line, and the other layer is a protective layer of the metal line. The protective layer is an alloy, the alloy is molybdenum and niobium, and the metal line is copper. wire or aluminum wire. Exemplarily, the source-drain metal layer includes a molybdenum-niobium layer, a copper layer, and a molybdenum-niobium layer stacked in sequence.

However, as the distance between water vapor reaching the overlapping area becomes smaller and smaller, in addition to the need to increase the distance between the organic layer 5 and one of the side surfaces of the substrate, it is also necessary to improve the membrane structure's poor waterproof performance. The material of the film layer is changed, but there is no need to change the film layer structure of the display substrate.

Specifically, the protective layer material of the source and drain metal layers can be changed to molybdenum nickel titanium. The source and drain metal layer provided by the embodiment of the present invention includes at least two layers, one of which is a metal line, and the other layer is a protective layer of the metal line. The protective layer is an alloy, and the alloy is molybdenum nickel titanium.

The clock signal leads are made of the same layer and material as the source and drain metal layers. When the protective layer material of the source and drain metal layers is changed, the material of the clock signal leads is also changed.

If the source-drain metal layer in the related art is a molybdenum-niobium layer, a copper layer and a molybdenum-niobium layer that are stacked in sequence, the molybdenum-niobium layer on the side of the source-drain metal layer close to the organic layer 5 needs to be changed to a molybdenum-nickel-titanium layer, away from it. The bottom molybdenum-niobium layer of the organic layer 5 may be changed to a molybdenum-nickel-titanium layer or may remain unchanged.

If the source and drain metal layers in the related art only include a copper layer and a molybdenum-niobium layer, the molybdenum-niobium layer only needs to be changed to a molybdenum-nickel-titanium layer.

The molybdenum nickel titanium material is less susceptible to corrosion by H or O than the molybdenum niobium material. Therefore, it can avoid the metal traces of the source and drain metal layers (such as the second part of the clock signal line) from growing vertically due to water absorption and interfering with the clock signal in the overlapping area. The first part of the wire creates an electrical connection, causing a short circuit.

It should be noted that the material of the gate metal layer may or may not be changed.

Referring to Figure 5, Figure 5 is a schematic cross-sectional view of a second display substrate provided by an embodiment of the present invention. The display substrate provided by an embodiment of the present invention includes:

The array substrate and the color filter substrate, the liquid crystal layer 7 located between the array substrate and the color filter substrate, the gate drive circuit and the frame sealant 6 located in the peripheral area of the display substrate, the gate drive circuit includes a plurality of metal oxide thin film transistors;

The array substrate includes a base substrate 1, which includes an upper surface and four side surfaces, and the four side surfaces are cutting surfaces after cutting the motherboard;

There are a plurality of clock signal lines located on the base substrate 1. Each clock signal line includes a first part 11a and a second part 11b arranged in different layers. The first part 11a and the second part 11b are connected through via holes. The second part 11b is connected to the metal oxide thin film transistor in the gate drive circuit;

The projection of the first part 11a and the second part 11b of the plurality of clock signal lines on the substrate 1 overlaps, and the overlapping area forms an overlapping area;

The first inorganic protective layer 3 and the second inorganic protective layer 4 covering the metal oxide thin film transistor, and the organic layer 5 located between the first inorganic protective layer 3 and the second inorganic protective layer 4;

Wherein, the first inorganic protective layer 3 includes a bottom layer 3a far away from the organic layer 5 and a top layer 3b close to the organic layer 5;

The first inorganic protective layer 3 and the second inorganic protective layer 4 extend from the area covering the metal oxide thin film transistor to the frame sealant area and are flush with one of the side surfaces of the base substrate 1;

The first inorganic protective layer 3 and the second inorganic protective layer 4 are at least part of the frame sealing glue area and are continuous areas without hollows on the entire surface;

The area between the organic layer 5 and one of the side surfaces of the base substrate 1 is a hollow area, so that the frame sealing glue 6 completely covers the first inorganic protective layer 3 and the second inorganic protective layer 4. Partial area covers the organic layer 5 or does not cover the organic layer 5 at all.

Optionally, the metal oxide thin film transistor includes:

a gate metal layer located on the upper surface of the base substrate;

a gate insulation layer covering the gate metal layer;

an active layer located on the side of the gate insulating layer away from the base substrate;

Source and drain metal layers located above the active layer.

This embodiment is introduced by taking a TFT as a bottom gate structure as an example. The TFT includes a gate metal layer located on the base substrate 1;

The first gate insulating layer 2a covering the gate metal layer, the first gate insulating layer 2a is a nitride inorganic material, such as silicon nitride;

The active layer located on the side of the first gate insulating layer 2a away from the base substrate 1, and the active layer material is metal oxide;

The second gate insulating layer 2b covering the active layer, the second gate insulating layer 2b is an oxide inorganic material, such as silicon oxide;

A source-drain metal layer located above the second gate insulating layer 2b, wherein the source-drain metal layer includes at least two layers, one of which is a metal line, and the other is a protective layer for the metal line, and the protective layer is an alloy. , the alloy is molybdenum niobium, the metal wire is copper wire or aluminum wire, the source and drain metal layers and the gate metal layer are made of the same material.

Optionally, there is a first spacing between the organic layer and one of the side surfaces of the base substrate. When the first spacing is greater than or equal to 600um, the organic layer and one of the side surfaces of the base substrate are The area between the above-mentioned sides is the hollowed-out area,

The organic layer in the overlapping area is provided with a hollow area, and the alloy of the protective layer of the clock signal line is molybdenum nickel titanium.

Among them, in the display substrate shown in Figure 5, on the basis of Figure 4, the organic layer 5 has not only extended to the sealant area, but also covered the overlapping area, that is, the distance between the organic layer and one of the base substrates is The distance between the sides is further reduced. At this time, the distance between one of the side surfaces of the base substrate and the third clock signal line cannot be used as a reference, because the distance between the organic layer and one of the side surfaces of the base substrate is The distance between the third clock signal line and one of the side surfaces of the base substrate is closer than that of the third clock signal line. Therefore, the first distance L1 between the organic layer and one of the side surfaces of the base substrate is as a baseline.

Further, when L1 is greater than or equal to 600um, the area between the organic layer and one of the side surfaces of the base substrate is a hollowed area, and a hollowed area needs to be provided for the organic layer in the overlapping area.

The organic layer 5 in the overlapping area has a hollow area, which can further prevent the accumulation of water vapor and prevent H or O from corroding the metal wiring in the overlapping area.

Furthermore, it is necessary to change the material of the film layer with poor waterproof performance in the film layer structure, but there is no need to change the film layer structure of the display substrate.

Specifically, the protective layer material of the source and drain metal layers can be changed to molybdenum nickel titanium. The source and drain metal layer provided by the embodiment of the present invention includes at least two layers, one of which is a metal line, and the other layer is a protective layer of the metal line. The protective layer is an alloy, and the alloy is molybdenum nickel titanium.

If the source-drain metal layer in the related art is a molybdenum-niobium layer, a copper layer and a molybdenum-niobium layer that are stacked in sequence, the molybdenum-niobium layer on the side of the source-drain metal layer close to the organic layer 5 needs to be changed to a molybdenum-nickel-titanium layer, away from it. The bottom molybdenum-niobium layer of the organic layer 5 may be changed to a molybdenum-nickel-titanium layer or may remain unchanged.

If the source and drain metal layers in the related art only include a copper layer and a molybdenum-niobium layer, the molybdenum-niobium layer only needs to be changed to a molybdenum-nickel-titanium layer.

The molybdenum nickel titanium material is less susceptible to corrosion by H or O than the molybdenum niobium material. Therefore, it can avoid the metal traces of the source and drain metal layers (such as the second part of the clock signal line) from growing vertically due to water absorption and interfering with the clock signal in the overlapping area. The first part of the wire creates an electrical connection, causing a short circuit.

It should be noted that the material of the gate metal layer may or may not be changed.

Optionally, there is a first spacing between the organic layer and one of the side surfaces of the base substrate. When the first spacing is less than 600um, the organic layer and one of the side surfaces of the base substrate are The area between the sides is the hollowed out area,

The organic layer in the overlapping area is provided with a hollow area. The alloy of the protective layer of the clock signal line is molybdenum nickel titanium. The first inorganic protective layer includes at least two layers, and the outer layer close to the organic layer is nitrogen. Silicone, the bottom layer away from the organic layer is silicon oxide, and the second part of the clock signal line is located under the silicon oxide layer and in contact with the silicon oxide layer.

Furthermore, when L1 is less than 600um, that is, the distance between the organic layer and one of the side surfaces of the substrate substrate is further reduced, then the display substrate needs to further enhance the waterproof capability, not only for the organic layer in the overlapping area To set up the hollow area, it is also necessary to change the material of the protective layer of the source and drain metal layers, and it is also necessary to change the material of the first inorganic protective layer.

Optionally, the first inorganic protective layer includes at least two layers, the outer layer close to the organic layer is made of silicon nitride, and the bottom layer far away from the organic layer is made of silicon oxide, and the clock signal lead is located below the silicon oxide layer and the The silicon oxide contact.

If the material of the top layer of the first inorganic protective layer close to the organic layer in the related art is an oxide inorganic material, the oxide inorganic material needs to be changed to a nitride inorganic material, for example, from silicon oxide to silicon nitride.

Specifically, the top layer is a SiNx layer with a thickness of The bottom layer is SiOx and the thickness is/>

Alternatively, another layer of inorganic nitride layer can be superimposed on the top layer of the first inorganic protective layer close to the organic layer.

The material, specifically, is a layer of SiNx with a thickness of 500A superimposed on the original structure.

Since silicon nitride material has better water resistance than silicon oxide, using silicon nitride material for the first inorganic protective layer can enhance the water vapor resistance of the display substrate.

In addition, the molybdenum nickel titanium material is less susceptible to corrosion by H or O than the molybdenum niobium material, so it can prevent the metal traces of the source and drain metal layers (such as the second part of the clock signal line) from growing vertically at the intersection due to water absorption. The stacked area is electrically connected to the first portion of the clock signal line, causing a short circuit.

An embodiment of the present invention also provides a display device, including the above-mentioned display substrate.

The display device includes but is not limited to: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, a power supply and other components. Those skilled in the art can understand that the structure of the display device described above does not constitute a limitation on the display device. The display device may include more or less of the above components, or combine certain components, or arrange different components. In embodiments of the present invention, display devices include but are not limited to monitors, mobile phones, tablet computers, televisions, wearable electronic devices, navigation display devices, etc.

The display device may be any product or component with a display function such as an LCD TV, an LCD monitor, a digital photo frame, a mobile phone, a tablet computer, etc. The display device further includes a flexible circuit board, a printed circuit board and a backplane.

In the various method embodiments of the present invention, the serial numbers of each step cannot be used to limit the order of each step. For those of ordinary skill in the art, without exerting creative work, the sequence of each step can be changed. It is also within the protection scope of the present invention.

It should be noted that each embodiment in this specification is described in a progressive manner, and the same and similar parts between the various embodiments can be referred to each other. Each embodiment focuses on its differences from other embodiments. In particular, the embodiments are described simply because they are basically similar to the product embodiments. For relevant details, please refer to the partial description of the product embodiments.

Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the usual meaning understood by a person with ordinary skill in the art to which this disclosure belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprising" mean that the elements or things appearing before the word include the elements or things listed after the word and their equivalents, without excluding other elements or things. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", etc. are only used to express relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element. Or intermediate elements may be present.

In the above description of the embodiments, specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure. should be covered by the protection scope of this disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims (10)

1. A display substrate, comprising: The array substrate and the color filter substrate, the liquid crystal layer located between the array substrate and the color filter substrate, the gate drive circuit and the frame sealing glue located in the peripheral area of the display substrate, the gate drive circuit includes a plurality of metal oxide Thin film transistor; characterized in that, The array substrate includes a base substrate, the base substrate includes an upper surface and four sides; A plurality of clock signal lines located on the base substrate, each clock signal line includes a first part and a second part arranged in different layers, the first part and the second part are connected through via holes, and the second part is connected to The metal oxide thin film transistor in the gate drive circuit is connected; The projection of the first part and the second part of the plurality of clock signal lines on the substrate overlap, and the overlapping area forms an overlapping area; a first inorganic protective layer and a second inorganic protective layer covering the metal oxide thin film transistor, and an organic layer located between the first inorganic protective layer and the second inorganic protective layer; The first inorganic protective layer and the second inorganic protective layer extend from the area covering the metal oxide thin film transistor to the sealant area and are flush with one of the side surfaces of the base substrate; The first inorganic protective layer and the second inorganic protective layer are at least part of the frame sealing glue area and are continuous areas without hollows on the entire surface; The area between the organic layer and one of the side surfaces of the base substrate is a hollow area, so that the frame sealing glue completely covers the first inorganic protective layer and the second inorganic protective layer, and partially covers The organic layer may or may not cover the organic layer at all. 2. The display substrate according to claim 1, characterized in that, The second portion of the clock signal line is located above the first portion of the clock signal line and closer to the organic layer. 3. The display substrate according to claim 2, characterized in that: The clock signal line includes at least two layers, one of which is a metal line, and the other is a protective layer of the metal line, and the protective layer is an alloy. 4. The display substrate according to claim 1, wherein there is a second spacing between the overlap closest to one of the side surfaces of the base substrate and one of the side surfaces of the base substrate. When the spacing is greater than or equal to 1000um, the overlapping area and the area between the overlapping area and one of the side surfaces of the base substrate are hollow areas. 5. The display substrate according to claim 3, wherein there is a second spacing between the overlap closest to one of the side surfaces of the base substrate and one of the side surfaces of the base substrate. When the second spacing is less than 1000um, the overlapping area and the area between the overlapping area and one of the side surfaces of the base substrate are hollow areas, and the alloy of the protective layer of the clock signal line is molybdenum nickel titanium. . 6. The display substrate according to claim 3, wherein there is a first spacing between the organic layer and one of the side surfaces of the base substrate, and when the first spacing is greater than or equal to 600um, the The area between the organic layer and one of the side surfaces of the base substrate is a hollow area, the organic layer in the overlapping area is provided with a hollow area, and the alloy of the protective layer of the clock signal line is molybdenum nickel. titanium. 7. The display substrate according to claim 3, wherein there is a first spacing between the organic layer and one of the side surfaces of the base substrate, and when the first spacing is less than 600um, the organic layer The area between the layer and one of the side surfaces of the base substrate is a hollow area, The organic layer in the overlapping area is provided with a hollow area. The alloy of the protective layer of the clock signal line is molybdenum nickel titanium. The first inorganic protective layer includes at least two layers, and the outer layer close to the organic layer is nitrogen. Silicone, the bottom layer away from the organic layer is silicon oxide, and the second part of the clock signal line is located under the silicon oxide layer and in contact with the silicon oxide layer. 8. The display substrate according to claim 1, wherein the metal oxide thin film transistor includes: a gate metal layer located on the upper surface of the base substrate; a gate insulation layer covering the gate metal layer; an active layer located on the side of the gate insulating layer away from the base substrate; Source and drain metal layers located above the active layer. 9. The display substrate according to claim 8, wherein the clock signal line and the source and drain metal layer are made of the same material. 10. A display device, comprising the display substrate according to any one of claims 1 to 9.