CN114005400A

CN114005400A - Pixel circuit and display panel

Info

Publication number: CN114005400A
Application number: CN202111272606.7A
Authority: CN
Inventors: 朱正勇; 贾溪洋; 赵欣; 孙光远; 段培; 何国冰; 马志丽
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd
Priority date: 2021-10-29
Filing date: 2021-10-29
Publication date: 2022-02-01
Anticipated expiration: 2041-10-29
Also published as: CN114005400B

Abstract

The embodiment of the invention discloses a pixel circuit and a display panel, wherein the pixel circuit comprises a driving transistor, a data writing module, a first initialization module and a first leakage suppression module, the first leakage suppression module is used for coupling the grid voltage variation of the driving transistor to a first intermediate node connected with the first leakage suppression module in a positive correlation manner, so that after the data writing stage, the potential of the first intermediate node of the first leakage suppression module is the sum of the first initialization voltage and the coupling amount (namely the voltage positively correlated with the grid voltage variation of the driving transistor), and further compared with the prior art, after the data writing stage, the voltage difference between the grid of the driving transistor and the first intermediate node in the first initialization module is reduced, the leakage of the first initialization module is reduced, and the grid voltage of the driving transistor can be well maintained in the light emitting stage, thereby ensuring the stability of the driving current generated by the driving transistor and improving the screen body flicker phenomenon.

Description

Pixel circuit and display panel

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a pixel circuit and a display panel.

Background

With the development of display technology, the requirements of people on display quality are higher and higher.

The display panel comprises a pixel circuit, the existing pixel circuit comprises a driving transistor and an initialization transistor for initializing the driving transistor, the electric leakage of the initialization transistor is large in the display panel prepared by the low-temperature polysilicon process, and the initialization transistor is generally set to be a double-gate transistor in the prior art.

However, when the light emitting device emits light, the potential difference between the intermediate node of the initialization transistor of the dual gate and the gate of the driving transistor is large, so that the leakage of the initialization transistor is still large, the gate potential of the driving transistor cannot be well maintained, and the screen flicker is caused.

Disclosure of Invention

The invention provides a pixel circuit and a display panel, which are used for reducing electric leakage of a first initialization module in the pixel circuit of a low-temperature polycrystalline silicon process display panel and reducing screen flicker.

In a first aspect, an embodiment of the present invention provides a pixel circuit, including: the device comprises a driving transistor, a data writing module, a storage module, a first initialization module and a first electric leakage suppression module;

the first initialization module is used for writing a first initialization voltage into the grid electrode of the driving transistor in an initialization stage; the first initialization module comprises at least two first sub-transistors connected in series, adjacent first sub-transistors are electrically connected through a first intermediate node between the adjacent first sub-transistors, the first leakage suppression module is electrically connected with at least one first intermediate node, and the first leakage suppression module is used for positively correlating the variation of the gate potential of the driving transistor to the first intermediate node connected with the first leakage suppression module;

the data writing module is used for writing the voltage of data into the grid electrode of the driving transistor in the data writing stage; the storage module is used for storing the grid voltage of the driving transistor.

Optionally, the first leakage suppression module includes a first capacitor, a first plate of the first capacitor is electrically connected to the gate of the driving transistor, and a second plate of the first capacitor is electrically connected to the at least one first intermediate node.

Optionally, in the first initialization module, a channel width-to-length ratio of a first sub-transistor between a first intermediate node to which the first leakage suppression module is connected and a first end of the first initialization module is smaller than a channel width-to-length ratio of a first sub-transistor between a first intermediate node to which the first leakage suppression module is connected and a second end of the first initialization module; the first end of the first initialization module is connected to a first initialization voltage, and the second end of the first initialization module is connected with the grid electrode of the driving transistor;

optionally, a channel width of the first sub-transistor between the first intermediate node to which the first leakage suppression module is connected and the first end of the first initialization module is less than or equal to 1.8 micrometers, and a channel length is greater than or equal to 4 micrometers.

Optionally, the pixel circuit further includes a compensation module, where the compensation module is configured to write information including a threshold voltage of the driving transistor into a gate of the driving transistor in a data writing phase;

the compensation module comprises at least two second sub-transistors connected in series, and the adjacent second sub-transistors are electrically connected through a second intermediate node between the two second sub-transistors;

optionally, a control end of the first initialization module is connected to a first scanning signal, a first end of the first initialization module is connected to a first initialization voltage, and a second end of the first initialization module is electrically connected to a gate of the driving transistor;

optionally, the control end of the data writing module is connected to the second scanning signal, the first end of the data writing module is connected to the data voltage, and the second end of the data writing module is electrically connected to the first pole of the driving transistor; the control end of the compensation module is connected with a second scanning signal, the first end of the compensation module is electrically connected with the second pole of the driving transistor, and the second end of the compensation module is electrically connected with the grid electrode of the driving transistor;

optionally, the pixel circuit further includes a first light-emitting control module and a second light-emitting control module, the first light-emitting control module is configured to control a conduction state between the first power voltage input end and the first pole of the driving transistor according to a first light-emitting control signal accessed by the control end of the first light-emitting control module, the second light-emitting control module is configured to control a conduction state between the second pole of the driving transistor and the first pole of the light-emitting device according to a second light-emitting control signal accessed by the control end of the second light-emitting control module, and the second pole of the light-emitting device is connected to the second power voltage input end.

Optionally, the first leakage suppression module includes a connection line connecting the at least one second intermediate node and the at least one first intermediate node.

Optionally, the first leakage suppression module further includes a second capacitor, one end of the second capacitor is connected to the fixed voltage, and the other end of the second capacitor is electrically connected to the connection line.

Optionally, the pixel circuit further includes a second leakage suppression module, where the second leakage suppression module includes a third capacitor, a first end of the third capacitor is connected to a fixed voltage, and a second end of the third capacitor is electrically connected to at least one second intermediate node;

optionally, in the compensation module, a channel width-to-length ratio of a second sub-transistor between a second intermediate node connected to the second leakage suppression module and the second pole of the driving transistor is smaller than a channel width-to-length ratio of a second sub-transistor between a second intermediate node connected to the second leakage suppression module and the gate of the driving transistor;

optionally, a channel width of the second sub-transistor between the second intermediate node connected to the second leakage suppression module and the second pole of the driving transistor is less than or equal to 1.8 micrometers, and a channel length of the second sub-transistor between the second intermediate node connected to the second leakage suppression module and the second pole of the driving transistor is greater than or equal to 4 micrometers.

Optionally, the pixel circuit further includes a second leakage suppression module, where the second leakage suppression module includes a fourth capacitor and a first control transistor;

a grid electrode of the first control transistor is connected with a second scanning signal, a first pole of the first control transistor is connected with a first fixed voltage, a second pole of the first control transistor is electrically connected with a first end of a fourth capacitor, and a second end of the fourth capacitor is electrically connected with at least one second intermediate node;

optionally, the second leakage suppression module further includes a second control transistor, a gate of the second control transistor is connected to the first light emitting control signal or the second light emitting control signal, a first pole of the second control transistor is connected to the second fixed voltage, and a second pole of the second control transistor is electrically connected to the first end of the fourth capacitor; wherein the second fixed voltage is less than the first fixed voltage;

optionally, a capacitance value of the fourth capacitor is smaller than a capacitance value of a storage capacitor included in the storage module.

Optionally, the first light-emitting control module and the second light-emitting control module are configured to be turned on in a plurality of light-emitting sub-phases included in the light-emitting phase, and the driving transistor is configured to drive the light-emitting module to emit light in the light-emitting sub-phases;

the pixel circuit further comprises a second initialization module and a third initialization module, wherein a control end of the second initialization module and a control end of the third initialization module are connected with a reset control signal, the second initialization module is used for writing a second initialization voltage into a first pole of the driving transistor in a plurality of reset sub-stages included in the light-emitting stage, and the third initialization module is used for writing a third initialization voltage into a second pole of the driving transistor and the first pole of the light-emitting device in the reset sub-stages, wherein each reset stage corresponds to one light-emitting sub-stage, and the reset sub-stages are before the corresponding light-emitting sub-stages;

optionally, the first end of the third initialization module is connected to a third initialization voltage, and the second end of the third initialization module is electrically connected to the first pole of the light emitting device or the second end of the third initialization module is electrically connected to the second pole of the driving transistor; and the reset control signal is overlapped with the active level of the second light-emitting control signal, the first light-emitting control signal is overlapped with the active level of the second light-emitting control signal, and the active level of the reset control signal is before the active level of the first light-emitting control signal.

In a second aspect, an embodiment of the present invention further provides a display panel, including the pixel circuit provided in the first aspect.

Embodiments of the present invention provide a pixel circuit and a display panel, wherein the pixel circuit includes a driving transistor, a data writing module, a first initialization module, and a first leakage suppression module, the first leakage suppression module is configured to couple a gate voltage variation of the driving transistor to a first intermediate node to which the first leakage suppression module is connected in a positive correlation, such that after the data writing phase, a potential of the first intermediate node of the first leakage suppression module is a sum of a first initialization voltage and a coupling amount (i.e., a voltage positively correlated with the gate voltage variation of the driving transistor), thereby making a voltage difference between a gate of the driving transistor and the first intermediate node in the first initialization module after the data writing phase smaller than that in the prior art, further reducing a leakage of the first initialization module, such that the gate voltage of the driving transistor can be well maintained during the light emitting phase, thereby ensuring the stability of the driving current generated by the driving transistor and improving the screen body flicker phenomenon.

Drawings

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 5 is a driving timing diagram of a pixel circuit according to an embodiment of the invention;

fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of another pixel circuit according to an embodiment of the invention;

fig. 11 is a timing diagram of driving another pixel circuit according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

As described in the background art, in the display panel prepared by the low-temperature polysilicon process, the initialization transistor has large leakage, and after the initialization transistor is set as the dual-gate transistor, when the light emitting device emits light, the potential difference between the intermediate node of the initialization transistor and the gate of the driving transistor of the dual-gate transistor is large, which causes screen flicker. The inventors have found that the above-mentioned problems occur because the operation of the conventional pixel circuit includes an initialization phase, a data writing phase, and a light emitting phase. In the initialization phase, the initialization transistor writes an initialization voltage to the gate of the driving transistor, and the potential of the intermediate node of the initialization transistor is also equal to the initialization voltage. In the data writing phase, the data voltage is written into the grid electrode of the driving transistor, and the potential of the middle node of the initialization transistor does not change greatly and is still close to the initialization voltage. In the light emitting stage, the driving transistor drives the light emitting device to emit light according to the data voltage written in the gate of the driving transistor, because the voltage difference between the data voltage and the initialization voltage is large, the voltage difference between the gate of the driving transistor and the intermediate node of the initialization transistor is large in the light emitting stage, the electric leakage of the initialization transistor is still large, the data voltage written in the gate of the driving transistor cannot be well maintained, and the driving current generated by the driving transistor is related to the voltage of the gate of the driving transistor, so that the driving current generated by the driving transistor of the light emitting device is unstable, the luminance of the light emitting device is changed, and finally the screen body flickers.

For the above reasons, an embodiment of the present invention provides a pixel circuit, and fig. 1 is a schematic structural diagram of the pixel circuit provided in the embodiment of the present invention, and referring to fig. 1, the pixel circuit includes: the driving transistor DT, the data writing module 110, the storage module 120, the first initialization module 130, and the first leakage suppression module 140;

the first initialization module 130 is configured to write a first initialization voltage Vref1 to the gate of the driving transistor DT in an initialization phase; the first initialization module 130 includes at least two first sub-transistors T01 connected in series, adjacent first sub-transistors T01 are electrically connected through a first intermediate node N1 therebetween, the first leakage suppression module 140 is electrically connected with at least one first intermediate node N1, the first leakage suppression module 140 is configured to positively-correlatively couple the gate potential variation of the driving transistor DT to the first intermediate node N1 to which the first leakage suppression module 140 is connected;

the data writing module 110 is configured to write a data voltage Vdata to the gate of the driving transistor DT in a data writing phase; the storage module 120 is used to store the gate voltage of the driving transistor DT.

The pixel circuit further includes a light emitting device D1, and the driving transistor DT and the light emitting device D1 are connected between a first power voltage input terminal VDD and a second power voltage input terminal VSS. Fig. 1 exemplarily shows that the control terminal of the first initialization module 130 is connected to the first Scan signal Scan1, and the control terminal of the data write module 110 is connected to the second Scan signal Scan 2.

Optionally, the data writing module 110 includes a data writing transistor. As shown in fig. 1, the data writing module 110 may be directly electrically connected to the gate of the driving transistor DT, and the data writing module 110 may directly write the data voltage Vdata to the gate of the driving transistor DT. In other optional embodiments of the present invention, the data writing module 110 may also be electrically connected to the first pole of the driving transistor DT, and when the data writing module 110 is electrically connected to the first pole of the driving transistor DT, the pixel circuit may further include a compensation module, and the data writing module 110 writes the data voltage Vdata to the gate of the driving transistor DT through the driving transistor DT and the compensation module.

Specifically, the first initialization module 130 includes at least two first sub-transistors T01 connected in series, that is, the first initialization module 130 includes multi-gate transistors, wherein the number of gates of the multi-gate transistors is determined by the number of first sub-transistors T01 connected in series and included in the first initialization module 130. Specifically, when the first initialization module 130 includes n (n ≧ 2) first sub-transistors T01 connected in series, the multi-gate transistor included in the first initialization module 130 is an n-gate transistor. Optionally, in this embodiment, the transistors included in each module in the pixel circuit are all low-temperature polysilicon transistors prepared by using a low-temperature polysilicon process.

The operation process of the pixel circuit of this embodiment may include an initialization phase, a data writing phase, and a light emitting phase.

In the initialization phase, the first initialization block 130 writes the first initialization voltage Vref1 to the gate of the driving transistor DT, and in the initialization phase, the gate voltage of the driving transistor DT is equal to the first initialization voltage Vref1, and the voltage of the first intermediate node N1 between the adjacent first sub-transistors T01 of the first initialization block is also equal to the initialization voltage. In the data writing phase, the data writing module 110 writes the data voltage Vdata to the gate of the driving transistor DT, and thus the gate voltage of the driving transistor DT varies from the initialization phase to the data writing phase, i.e., the initialization voltage varies to the data voltage Vdata. In the light emitting phase, the driving transistor DT generates a driving current according to its gate voltage to drive the light emitting device D1 to emit light.

In the present embodiment, since the first leakage suppression module 140 is disposed in the pixel circuit, the first leakage suppression module 140 is configured to couple the gate voltage variation of the driving transistor DT to the first intermediate node N1 connected to the first leakage suppression module 140 in a positive correlation manner, so that after the data writing phase, the potential of the first intermediate node N1 of the first leakage suppression module 140 is the sum of the first initialization voltage Vref1 and the coupling amount (i.e. the voltage positively correlated to the gate voltage variation of the driving transistor DT), and thus compared with the prior art, after the data writing phase, the voltage difference between the gate of the driving transistor DT and the first intermediate node N1 in the first initialization module 130 is reduced, and thus the leakage of the first initialization module 130 is reduced, so that during the light emitting phase, the gate voltage of the driving transistor DT can be well maintained, and thus the stability of the driving current generated by the driving transistor DT is ensured, improve the screen flicker phenomenon. In addition, in the pixel circuit of the embodiment, no matter which gray scale the data voltage Vdata corresponding to is written into the gate of the driving transistor DT in the data writing phase, due to the effect of the first leakage suppression module 140, after the data writing phase, the variation of the gate voltage of the driving transistor DT (for example, for the pixel circuit shown in fig. 1, the variation of the gate voltage of the driving transistor DT is equal to the difference between the data voltage Vdata and the first initialization voltage Vref1) is positively correlated to the first intermediate node N1 in the first initialization module 130 connected to the first leakage suppression module 140, so that no matter any display gray scale, the voltage difference between the gate voltage of the driving transistor DT and the voltage of the first intermediate node N1 of the first initialization module 130 is reduced after the data writing phase, and further, the leakage of the first initialization module 130 is reduced in any display gray scale, the flickering phenomenon of the screen can be improved.

In the prior art, the initialization transistor corresponding to the first initialization module 130 in part of the pixel circuits is set as an oxide transistor to reduce the leakage, but the oxide transistor has a complicated preparation process and a large size, which is not favorable for realizing high pixel density. And because the channel type of the oxide transistor is different from that of the low-temperature polysilicon transistor in the pixel circuit, a new gate drive circuit needs to be added in the frame area of the display panel, which is not beneficial to realizing a narrow frame. The pixel circuit of the embodiment does not need to set the initialization transistor included in the first initialization module 130 as an oxide transistor, and the pixel circuit is prepared by adopting a low-temperature polysilicon process, which is beneficial to simplifying the preparation process and realizing a high-pixel-density display panel and a narrow frame.

The pixel circuit of the embodiment includes a driving transistor, a data writing module, a first initialization module and a first leakage suppression module, the first leakage suppression module is configured to couple a gate voltage variation of the driving transistor to a first intermediate node connected to the first leakage suppression module in a positive correlation, so that after a data writing phase, a potential of the first intermediate node of the first leakage suppression module is a sum of a first initialization voltage and a coupling amount (i.e., a voltage positively correlated to the gate voltage variation of the driving transistor), and further compared with the prior art, after the data writing phase, a voltage difference between a gate of the driving transistor and the first intermediate node in the first initialization module is reduced, and further a leakage of the first initialization module is reduced, so that in a light emitting phase, the gate voltage of the driving transistor can be well maintained, and further stability of a driving current generated by the driving transistor is ensured, improve the screen flicker phenomenon.

Fig. 2 is a schematic structural diagram of another pixel circuit according to an embodiment of the invention, and referring to fig. 2, optionally, the first leakage suppression module 140 includes a first capacitor C1, a first plate of the first capacitor C1 is electrically connected to the gate of the driving transistor DT, and a second plate of the first capacitor C1 is electrically connected to at least one first intermediate node N1.

Specifically, the capacitors have a coupling effect, and the first leakage suppression module 140 is configured to include a first capacitor C1, where the first capacitor C1 is connected to the gate of the driving transistor DT and at least one first intermediate node N1 of the first initialization module 130, so that after the data writing phase, the first capacitor C1 can couple the voltage variation of the gate of the driving transistor DT to the first intermediate node N1 connected to the first leakage suppression module 140 in a positive correlation manner, thereby reducing the voltage difference between the gate of the driving transistor DT and the first intermediate node N1 of the first initialization module 130 after the data writing phase, and further reducing the leakage of the first initialization module 130, compared to the prior art.

It should be noted that, a person skilled in the art may reasonably set the capacitance value of the first capacitor according to the voltage coupling amount of the gate voltage of the driving transistor to the first intermediate node, and the capacitance value of the first capacitor is not specifically limited in this embodiment, so that compared with the prior art, after the data writing stage, the voltage difference between the gate voltage of the driving transistor and the first intermediate node is reduced.

Specifically, in the above embodiment, after the data writing phase, the voltage difference between the gate of the driving transistor DT and the first intermediate node N1 connected to the first leakage suppression module 140 in the first initialization module 130 is decreased, so that the leakage of the first sub-transistor T01 between the first intermediate node N1 connected to the first leakage suppression module 140 and the gate of the driving transistor DT is decreased.

Based on the above technical solution, optionally, in the first initialization module 130, a channel width-to-length ratio of the first sub-transistor T01 between the first intermediate node N1 connected to the first leakage suppression module 140 and the first end of the first initialization module 130 is smaller than a channel width-to-length ratio of the first sub-transistor T01 between the first intermediate node N1 connected to the first leakage suppression module 140 and the second end of the first initialization module 130; the first terminal of the first initialization module 130 is connected to the first initialization voltage Vref1, and the second terminal of the first initialization module 130 is connected to the gate of the driving transistor DT.

Specifically, the smaller the width-to-length ratio of the first sub-transistor T01, the smaller the leakage of the first sub-transistor T01. In this embodiment, by setting the channel width-to-length ratio of the first sub-transistor T01 between the first intermediate node N1 connected to the first leakage suppression module 140 and the first end of the first initialization module 130 to be smaller than the channel width-to-length ratio of the first sub-transistor T01 between the first intermediate node N1 connected to the first leakage suppression module 140 and the second end of the first initialization module 130, the leakage of the first sub-transistor T01 between the first intermediate node N1 connected to the first leakage suppression module 140 and the first end of the first initialization module 130 can be made smaller, and the leakage of the first initialization module 130 can be further reduced.

Optionally, the channel width of the first sub-transistor T01 between the first intermediate node N1 connected to the first leakage suppression module 140 and the first end of the first initialization module 130 is less than or equal to 1.8 micrometers, and the channel length of the first sub-transistor T01 between the first intermediate node N1 connected to the first leakage suppression module 140 and the first end of the first initialization module 130 is greater than or equal to 4 micrometers, so that the channel width-to-length ratio of the first sub-transistor T01 between the first intermediate node N1 connected to the first leakage suppression module 140 and the first end of the first initialization module 130 in the first initialization module 130 may be smaller.

Fig. 3 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present invention, and referring to fig. 3, optionally, the pixel circuit further includes a compensation module 150, where the compensation module 150 is configured to write information containing a threshold voltage of the driving transistor DT to a gate of the driving transistor DT in a data writing phase; the compensation module 150 includes at least two second sub-transistors T02 connected in series, and adjacent second sub-transistors T02 are electrically connected by a second intermediate node N2 therebetween.

Specifically, a first terminal of the compensation module 150 is electrically connected to the second terminal of the driving transistor DT, and a second terminal of the compensation module 150 is electrically connected to the gate of the driving transistor DT. Since the compensation module 150 is connected to the gate of the driving transistor DT, the leakage of the compensation module 150 also prevents the gate voltage of the driving transistor DT from being well maintained during the light emitting period. In this embodiment, the compensation module 150 includes at least two second sub-transistors T02 connected in series, that is, the compensation module 150 is also a multi-gate transistor, so that the leakage of the compensation module 150 is small, the gate potential of the driving transistor DT in the light-emitting phase can be maintained well, the light-emitting brightness of the light-emitting device D1 is stable, and the flicker phenomenon of the display panel is improved.

With continued reference to fig. 3, optionally, the control terminal of the first initialization module 130 is connected to the first Scan signal Scan1, the first terminal of the first initialization module 130 is connected to the first initialization voltage Vref1, and the second terminal of the first initialization module 130 is electrically connected to the gate of the driving transistor DT. Optionally, the first initialization module 130 includes a first initialization transistor T1, a gate of the first initialization transistor T1 is used as a control terminal of the first initialization module 130, a first pole of the first initialization transistor T1 is used as a first terminal of the first initialization module 130, and a second pole of the first initialization transistor T1 is used as a second terminal of the first initialization module 130.

Fig. 3 also illustrates the first leakage suppression module 140 including the first capacitor C1 as an example.

Optionally, the control terminal of the data writing module 110 is connected to the second Scan signal Scan2, the first terminal of the data writing module 110 is connected to the data voltage Vdata, and the second terminal of the data writing module 110 is electrically connected to the first pole of the driving transistor DT; the control terminal of the compensation module 150 is connected to the second Scan signal Scan2, the first terminal of the compensation module 150 is electrically connected to the second pole of the driving transistor DT, and the second terminal of the compensation module 150 is electrically connected to the gate of the driving transistor DT. Optionally, the data writing module 110 includes a data writing transistor T2, a gate of the data writing transistor T2 is used as a control terminal of the data writing module 110, a first pole of the data writing transistor T2 is used as a first terminal of the data writing module 110, and a second pole of the data writing transistor T2 is used as a second terminal of the data writing module 110. Optionally, the compensation module 150 includes a compensation transistor T3, a gate of the compensation transistor T3 is used as a control terminal of the compensation module 150, a first pole of the compensation transistor T3 is used as a first terminal of the compensation module 150, and a second pole of the compensation transistor T3 is used as a second terminal of the compensation module 150.

Optionally, the pixel circuit further includes a first light-emitting control module 160 and a second light-emitting control module 170, the first light-emitting control module 160 is configured to control a conduction state between the first power voltage input terminal VDD and the first pole of the driving transistor DT according to a first light-emitting control signal EM1 accessed by the control terminal of the first light-emitting control module 160, the second light-emitting control module 170 is configured to control a conduction state between the second pole of the driving transistor DT and the first pole of the light-emitting device D1 according to a second light-emitting control signal EM2 accessed by the control terminal of the second light-emitting device D1, and the second pole of the light-emitting device D1 is connected to the second power voltage input terminal VSS.

A control terminal of the first light-emitting control module 160 is connected to the first light-emitting control signal EM1, a first terminal of the first light-emitting control module 160 is electrically connected to the first power voltage input terminal VDD, and a second terminal of the first light-emitting control module 160 is electrically connected to the first pole of the driving transistor DT. Optionally, the first light emitting control module 160 includes a first light emitting control transistor T4, a gate of the first light emitting control transistor T4 is used as a control terminal of the first light emitting control module 160, a first pole of the first light emitting control transistor T4 is used as a first terminal of the first light emitting control module 160, and a second pole of the first light emitting control transistor T4 is used as a second terminal of the first light emitting control module 160.

A control terminal of the second light emission control module 170 is connected to the second light emission control signal EM2, a first terminal of the second light emission control module 170 is electrically connected to the first pole of the driving transistor DT, a second terminal of the second light emission control module 170 is electrically connected to the first pole of the light emitting device D1, and a second pole of the light emitting device D1 is electrically connected to the second power supply voltage input terminal VSS. Optionally, the second light-emitting control module 170 includes a second light-emitting control transistor T5, a gate of the second light-emitting control transistor T5 is used as a control terminal of the second light-emitting control module 170, a first pole of the second light-emitting control transistor T5 is used as a first terminal of the second light-emitting control module 170, and a second pole of the second light-emitting control transistor T5 is used as a second terminal of the second light-emitting control module 170.

Fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and referring to fig. 4, optionally, the first leakage suppression module 140 includes a connection line 141 connecting at least one second intermediate node N2 and at least one first intermediate node N1.

Fig. 5 is a driving timing diagram of a pixel circuit according to an embodiment of the present invention, where the driving timing diagram can be used to drive the pixel circuit shown in fig. 4, and optionally, each transistor in the pixel circuit shown in fig. 4 is a P-type transistor. Referring to fig. 4 and 5, the operation process of the pixel circuit includes an initialization phase t0, a data writing phase t1, and a light emitting phase t 2.

In the initialization period T0, the first Scan signal Scan1 is at a low level, the first initialization transistor T1 is turned on, and the first initialization voltage Vref1 is transmitted to the gate of the driving transistor DT. Therefore, when the initialization phase is completed, the gate of the driving transistor DT and the potential of the first intermediate node N1 of the first initialization transistor T1 are both equal to the first initialization voltage Vref 1.

In the data writing phase T1, the second Scan signal Scan2 is at a low level, the data writing transistor T2 and the compensation transistor T3 are turned on, the data voltage Vdata is written to the gate of the driving transistor DT through the data writing transistor T2, the driving transistor DT and the compensation transistor T3, until the gate voltage of the driving transistor DT is equal to Vdata + Vth (where Vth represents the threshold voltage of the driving transistor DT), the driving transistor DT is turned off, and the writing of the data voltage Vdata to the gate of the driving transistor DT and the compensation of the threshold voltage of the driving transistor DT are realized. When the data writing phase T1 is completed, the voltage of the gate of the driving transistor DT and the voltage of the second intermediate node N2 of the compensation transistor T3 are both equal to Vdata + Vth.

In the light-emitting period T2, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at a low level, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are turned on, the driving transistor DT generates a driving current according to the gate voltage thereof and the first voltage, and the light-emitting device D1 is driven to emit light.

In this embodiment, the first leakage suppression module 140 includes a connection line 141 connecting the at least one second intermediate node N2 and the at least one first intermediate node N1, such that when the data writing phase t1 is completed, the potential of the first intermediate node N1 is equal to the potential of the second intermediate node N2, and therefore the potential of the first intermediate node N1 of the first initialization module 130 connected to the second intermediate node N2 is also equal to Vdata + Vth, and further the voltage difference between the intermediate node of the first initialization module 130 and the driving transistor DT is approximately equal to 0, so as to reduce the leakage of the first initialization module 130, and further the gate potential of the driving transistor DT can be maintained well in the light emitting phase t 2.

Fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and referring to fig. 6, on the basis of the pixel circuit shown in fig. 4, optionally, the first leakage suppression module 140 further includes a second capacitor C2, one end of the second capacitor C2 is connected to a fixed voltage, and the other end is electrically connected to the connection line 141.

The fixed voltage inputted by the second capacitor C2 may be equal to the first power voltage inputted by the first power voltage input terminal VDD. The connection of the fixed voltage to one end of the second capacitor C2 may also be equal to the first initialization voltage Vref1 or other fixed voltages, which is not specifically limited herein, and fig. 6 illustrates an example where the second capacitor C2 is connected to the first power voltage input terminal VDD.

Specifically, due to the parasitic capacitance between the second intermediate node N2 of the compensation transistor T3 and the gate of the compensation transistor T3, the potential jump of the second Scan signal Scan2 connected to the gate of the compensation transistor T3 affects the potential of the second intermediate node N2 of the compensation transistor T3. Here, the amount of potential jump of the second intermediate node N2 of the compensation transistor T3 caused by the amount of gate potential jump of the compensation transistor T3 can be expressed by the following formula:

wherein, is Δ V_Scan2Voltage jump quantity, Δ V, of the second Scan signal Scan2 representing the gate turn-on of the compensation transistor T3_N2A voltage jump amount of the second Scan signal Scan2 representing the gate turn-on of the compensation transistor T3 causes a voltage jump amount of the second intermediate node N2, C' represents a capacitance value of a parasitic capacitance between the second intermediate node N2 and the gate of the compensation transistor T3, C₀Indicating the capacitance of the other capacitor connected to the second intermediate node N2 (except the parasitic capacitance between the second intermediate node N2 and the gate of the compensation transistor T3).

In this embodiment, the other capacitors connected to the second intermediate node N2 include the second capacitor C2, so that the amount of the jump of the second intermediate node N2 caused by the jump of the second Scan signal Scan2 can be small, the potential of the second intermediate node N2 can be kept stable when the second Scan signal Scan2 jumps, and the potential of the first intermediate node N1 connected to the second intermediate node N2 through the second connection line 141 can be kept stable. Illustratively, after the data writing phase is completed, the second Scan signal Scan2 jumps from a low potential to a high potential, and the second capacitor C2 is disposed in the second leakage suppression module, so that the potential of the second intermediate node N2 is not greatly affected by the jump of the second Scan signal Scan2, and the potential of the second intermediate node N2 is still close to Vdata + Vth, and then the potential of the first intermediate node N1 connected to the second intermediate node N2 through the connection line 141 is still close to Vdata + Vth, so that after the data writing phase is completed, the voltage difference between the second intermediate node N2 of the compensation transistor T3 and the DT gate of the driving transistor is small, the voltage difference between the first intermediate node N1 of the first initialization transistor T1 and the DT gate of the driving transistor is small, and further, the leakage currents of the compensation transistor T3 and the first initialization transistor T1 are small in the light emitting phase after the data writing phase, the grid potential of the driving transistor DT can be well maintained, and the flicker phenomenon of the screen body is further improved.

In addition, the second leakage suppression module includes a second capacitor C2, one end of the second capacitor C2 is connected to a fixed voltage, and the other end of the second capacitor C2 is electrically connected to the connection line 141 (i.e., the other end of the second capacitor C2 is connected to the first intermediate node N1 and the second intermediate node N2), so that the total capacitance connected to the first intermediate node N1 of the first initialization module 130 is increased, and further, the leakage speed of the first sub-transistor T01 between the first intermediate node N1 and the first end of the first initialization module 130 (the first end of the first initialization module 130 is connected to the first initialization voltage Vref1) is reduced, thereby performing a voltage stabilizing effect on the first intermediate node N1. And the total capacitance connected to the second intermediate node N2 of the compensation module 150 is increased, so that the leakage speed between the second intermediate node N2 and the first end of the compensation module 150 (the first end of the compensation module 150 is electrically connected to the second pole of the driving transistor DT) is reduced, and the voltage stabilizing effect on the second intermediate node N2 is achieved.

Fig. 7 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, referring to fig. 7, optionally, the pixel circuit further includes a second leakage suppression module 180, the second leakage suppression module 180 includes a third capacitor C3, a first end of the third capacitor C3 is connected to a fixed voltage, and a second end of the third capacitor C3 is electrically connected to at least one second intermediate node N2.

The fixed voltage inputted by the third capacitor C3 may be equal to the first power voltage inputted by the first power voltage input terminal VDD. The connection of the one end of the third capacitor C3 to the fixed voltage may also be equal to the first initialization voltage Vref1 or other fixed voltages, which is not specifically limited herein, and fig. 7 illustrates an example where the third capacitor C3 is connected to the first power voltage input terminal VDD.

Specifically, by setting the pixel circuit to include the second leakage suppression module 180, the first end of the third capacitor C3 included in the second leakage suppression module 180 is connected to a fixed voltage, a voltage value of the fixed voltage remains unchanged, that is, a potential of the first end of the third capacitor C3 is always stable, the second end of the third capacitor C3 is electrically connected to at least one second intermediate node N2 in the compensation module 150, so as to increase a total capacitance connected to the second intermediate node N2, so that the data writing phase is completed, and when the second Scan signal Scan2 jumps, a potential jump amount of the second intermediate node N2 may be smaller. Moreover, since the gate of the driving transistor DT is connected to the storage module 120, the storage module 120 includes a storage capacitor, so that the total capacitance connected to the gate of the driving transistor DT is relatively large, the data writing phase is completed, when the second Scan signal Scan2 jumps, the voltage jump amount of the gate of the driving transistor DT can be relatively small, and further, when the data writing phase is completed, the voltage difference between the second intermediate node N2 of the compensation module 150 and the gate of the driving transistor DT can be relatively small, thereby ensuring that the leakage current of the compensation module 150 can be relatively small, and ensuring that the gate voltage of the driving transistor DT can be relatively well maintained in the light emitting phase.

Specifically, the voltage difference between the second intermediate node N2 of the compensation module 150 and the gate of the driving transistor DT may be small, so that the leakage of the second sub-transistor T02 between the second intermediate node N2 and the gate of the driving transistor DT in the compensation module 150 may be small. In other optional embodiments of the present invention, in the compensation module 150, a channel width-to-length ratio of the second sub-transistor T02 between the second intermediate node N2 connected to the second leakage suppression module 180 and the second pole of the driving transistor DT is smaller than a channel width-to-length ratio of the second sub-transistor T02 between the second intermediate node N2 connected to the second leakage suppression module 180 and the gate of the driving transistor DT, so that leakage of the second sub-transistor T02 between the second intermediate node N2 and the second pole of the driving transistor DT in the compensation module 150 may be smaller, thereby further reducing leakage of the compensation module 150, further ensuring that the gate potential of the driving transistor DT in the light emitting phase can be well maintained, and further improving the screen flicker phenomenon.

Optionally, the channel width of the second sub-transistor T02 between the second intermediate node N2 connected to the second leakage suppression module 180 and the second pole of the driving transistor DT is less than or equal to 1.8 micrometers, and the channel length of the second sub-transistor T02 between the second intermediate node N2 connected to the second leakage suppression module 180 and the second pole of the driving transistor DT is greater than or equal to 4 micrometers, so that the channel width-to-length ratio of the second sub-transistor T02 between the second intermediate node N2 connected to the second leakage suppression module 180 and the second pole of the driving transistor DT in the compensation module 150 may be smaller.

Fig. 8 is a schematic structural diagram of another pixel circuit provided in the embodiment of the present invention, and referring to fig. 8, optionally, the pixel circuit further includes a second leakage suppression module 180, where the second leakage suppression module 180 includes a fourth capacitor C4 and a first control transistor T6;

the gate of the first control transistor T6 is connected to the second Scan signal Scan2, the first pole of the first control transistor T6 is connected to the first fixed voltage V1, the second pole of the first control transistor T6 is electrically connected to the first end of the fourth capacitor C4, and the second end of the fourth capacitor C4 is electrically connected to at least one second intermediate node N2.

In this embodiment, the first control transistor T6 of the second leakage suppression module 180 is the same as the channel type of the compensation transistor T3. The driving sequence shown in fig. 5 is also used for driving the pixel circuit shown in fig. 8, and alternatively, each transistor in the pixel circuit shown in fig. 8 is a P-type transistor, and referring to fig. 8 and 5, the working process of the pixel circuit includes an initialization phase t0, a data writing phase t1, and a light emitting phase t 2.

In the initialization period T0, the first Scan signal Scan1 is at a low level, the first initialization transistor T1 is turned on, and the first initialization voltage Vref1 is transmitted to the gate of the driving transistor DT. Thus, at the completion of the initialization phase T0, the potentials of the gate of the driving transistor DT and the first intermediate node N1 of the first initialization transistor T1 are both equal to the first initialization voltage Vref 1.

In the data writing phase T1, the second Scan signal Scan2 is at a low level, the data writing transistor T2 and the compensation transistor T3 are turned on, the data voltage Vdata is written to the gate of the driving transistor DT through the data writing transistor T2, the driving transistor DT and the compensation transistor T3, until the gate voltage of the driving transistor DT is equal to Vdata + Vth (where Vth represents the threshold voltage of the driving transistor DT), the driving transistor DT is turned off, and the writing of the data voltage Vdata to the gate of the driving transistor DT and the compensation of the threshold voltage of the driving transistor DT are realized. When the data writing phase T1 is completed, the voltage of the gate of the driving transistor DT and the voltage of the second intermediate node N2 of the compensation transistor T3 are both equal to Vdata + Vth. Also, in the data writing phase T1, the first control transistor T6 is turned on in response to the low level of the second Scan signal Scan2, so that the first terminal of the fourth capacitor C4 is the first fixed voltage V1.

When the data writing phase is finished at T1, the second Scan signal Scan2 jumps from low level to high level, the first control transistor T6 is turned off, and since no signal is input to the first terminal of the fourth capacitor C4, the first terminal of the fourth capacitor C4 is maintained at the first fixed voltage V1. Due to the existence of the fourth capacitor C4, the potential jump of the second Scan signal Scan2 does not have a great influence on the potential of the second intermediate node N2 between two adjacent second sub-transistors T02 of the compensation transistor T3, so that the potential difference between the second intermediate node N2 and the gate of the driving transistor DT is not too large, and thus the leakage of the compensation module 150 can be ensured to be small, and the gate potential of the driving transistor DT can be well maintained.

In the light-emitting period T2, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at a low level, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are turned on, the driving transistor DT generates a driving current according to the gate voltage thereof and the first voltage, and the light-emitting device D1 is driven to emit light. Since the potential variation of the second intermediate node N2 of the compensation transistor T3 connected to the second leakage suppression module 180 may be small when the data writing phase T1 is finished, so that in the light emitting phase, the difference between the second intermediate node N2 of the compensation transistor T3 connected to the second leakage suppression module 180 and the gate potential of the driving transistor DT is small, so that in the light emitting phase, the leakage of the compensation transistor T3 is still small, and it is further ensured that the gate potential of the driving transistor DT is well maintained in the light emitting phase, so that the driving current generated by the driving transistor DT in the light emitting phase T2 is relatively stable, and the light emitting brightness of the light emitting device D1 is ensured to be stable, thereby improving the flicker phenomenon of the display panel including the pixel circuit of the present embodiment.

Optionally, the first emission control signal EM1 and the second emission control signal EM2 are the same. The first emission control signal EM1 and the second emission control signal EM2 are the same, and for the same pixel circuit, the control end of the first emission control module 160 and the control end of the second emission control module 170 are connected to the same emission control signal line in the display panel, so that the number of wires in the display panel is reduced, and the difficulty of the wires is reduced.

In the pixel circuit shown in fig. 8, by providing the second leakage suppression module 180 including the first control transistor T6 and the fourth capacitor C4, the potential of the second intermediate node N2 of the compensation transistor T3 connected to the second leakage suppression module 180 is less affected by the transition of the second Scan signal Scan2, and the leakage of the second sub-transistor T02 in the compensation transistor T3 between the second intermediate node N2 and the gate of the driving transistor DT is less, so that the gate potential of the driving transistor DT can be well maintained.

In other alternative embodiments of the present invention, the leakage of the second sub-transistor T02 between the second intermediate node N2 of the compensation transistor T3 and the second pole of the driving transistor DT, which is connected to the second leakage suppression module 180, may also be reduced by different structural arrangements of the second leakage suppression module 180. In the prior art, the display effect of the display panel is not ideal in the low gray scale, partly due to the leakage of the second sub-transistor T02 between the second intermediate node N2 of the compensation transistor T3 and the second pole of the driving transistor DT, and in order to reduce the leakage of the second sub-transistor T02 between the second intermediate node N2 of the compensation transistor T3 and the second pole of the driving transistor DT, the embodiment of the invention provides the pixel circuit structure shown in fig. 9.

Fig. 9 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and referring to fig. 9, optionally, the second leakage suppressing module 180 further includes a second control transistor T7, a gate of the second control transistor T7 is connected to the first emission control signal EM1 or the second emission control signal EM2, a first pole of the second control transistor T7 is connected to the second fixed voltage V2, and a second pole of the second control transistor T7 is electrically connected to the first end of the fourth capacitor C4; wherein the second fixed voltage V2 is less than the first fixed voltage V1.

The channel type of the second control transistor T7 is the same as the channel types of the first light emission control transistor T4 and the second light emission control transistor T5, and optionally, in this embodiment, the first control transistor T6, the first light emission control transistor T4 and the second light emission control transistor T5 are all P-type transistors.

Specifically, the second leakage suppression module 180 further controls whether the first end of the fourth capacitor C4 is connected to the second fixed voltage V2 according to the first emission control signal EM1 or the second emission control signal EM 2. In one frame, the active potential signal of the first emission control signal EM1 and the active potential signal of the second emission control signal EM2 are both after the active potential signal of the second Scan signal Scan 2. In the pixel circuit of this embodiment, during the data writing phase, the first control transistor T6 is turned on according to the active potential signal of the second Scan signal Scan2, the potential of the first terminal of the fourth capacitor C4 is equal to the first fixed voltage V1, during the light emitting phase, the second control transistor T7 is turned on in response to the active potential of the first light emitting control signal EM1 or the second light emitting control signal EM2, and the potential of the first terminal of the fourth capacitor C4 is equal to the second fixed voltage V2.

In the array substrate prepared by the low-temperature polysilicon process, each transistor in the pixel circuit is generally a P-type transistor, and in this embodiment, each transistor in the pixel circuit may be a P-type transistor. In the low gray scale, after the data voltage Vdata is written to the gate of the driving transistor DT in the pixel circuit, the voltages of the gate and the second pole of the driving transistor DT and the voltage of the second intermediate node N2 of the compensating transistor T3 are generally positive values, for example, 2V to 3V. In the light emitting period, the first light emitting control transistor T4 and the second light emitting control transistor T5 are turned on, and the driving transistor DT is turned on, so that the voltage of the second pole of the driving transistor DT is generally negative, for example, -1V, and the voltage of the second intermediate node N2 of the compensating transistor T3 is still positive (2V to 3V), so that the difference between the voltage of the second intermediate node N2 of the compensating transistor T3 and the voltage of the second pole of the driving transistor DT is large in the light emitting period. By providing the second leakage suppression module 180 further including the second control transistor T7, the gate of the second control transistor T7 is connected to the first emission control signal EM1 or the second emission control signal EM2, the first pole of the second control transistor T7 is connected to the second fixed voltage V2, the second pole of the second control transistor T7 is electrically connected to the first end of the fourth capacitor C4, so that the first end of the fourth capacitor C4 is connected to the second fixed voltage V2 during the emission phase, since the second fixed voltage V2 is smaller than the first fixed voltage V1, the data writing phase enters the emission phase, the voltage of the first end of the fourth capacitor C4 is decreased (from the first fixed voltage V1 to the second fixed voltage V2), and due to the coupling effect of the fourth capacitor C4, the voltage of the second intermediate node N2 of the compensation transistor T3 connected to the fourth capacitor C4 is also decreased, and further the intermediate node N57324 of the compensation transistor T3 connected to the fourth capacitor C4 is driven by the second fixed voltage DT 57324 The voltage difference between the electrodes is reduced, so that the leakage of the second sub-transistor T02 between the second intermediate node N2 of the compensation transistor T3 connected to the fourth capacitor C4 and the second electrode of the driving transistor DT is reduced, the leakage of the compensation transistor T3 is further reduced, the stability of the gate potential of the driving transistor DT is further ensured, and the display effect is improved.

In the light emitting period, the second pole potential of the driving transistor DT is the sum of the voltage input from the second power voltage input terminal VSS and the voltage across the light emitting device D1. At the end of the light emitting period, the first light emitting control signal EM1 and the second light emitting control signal EM2 jump from the active potential signal to the inactive potential signal, the first light emitting control module 160 and the second light emitting control module 170 are turned off, the driving transistor DT remains on, the first voltage of the driving transistor DT is the first power voltage input from the first power voltage input terminal VDD, the first power voltage is higher than the sum of the second power voltage input from the second power voltage input terminal VSS and the voltage across the light emitting device D1, and therefore the voltage of the second pole of the driving transistor DT is pulled up. And since a parasitic capacitance exists between the gate of the second control transistor T7 and the second pole of the second control transistor T7, at the end of the lighting phase, the second pole of the second control transistor T7 is coupled to rise, and due to the coupling effect of the fourth capacitance C4, the potential of the second intermediate node N2 of the compensation transistor T3 is coupled to rise, that is, the potential of the second intermediate node N2 of the compensation transistor T3 rises simultaneously with the potential of the second pole of the driving transistor DT, so that the potential difference between the second intermediate node N2 of the compensation transistor T3 and the second pole of the driving transistor DT is still small, and the leakage of the sub-transistor between the second intermediate node N2 of the compensation transistor T3 and the second pole of the driving transistor DT is small.

Optionally, the capacitance value of the fourth capacitor C4 is smaller than the capacitance value of the storage capacitor included in the storage module 120.

Specifically, since a parasitic capacitance exists between the gate of the compensation transistor T3 and the second pole of the compensation transistor T3 (the second pole of the compensation transistor T3 is electrically connected to the gate of the driving transistor DT as the second terminal of the compensation module 150), and a parasitic capacitance also exists between the second intermediate node N2 of the compensation transistor T3 and the gate of the compensation transistor T3, when the second Scan signal Scan2 transitions from the active potential signal to the inactive potential signal at the end of the data writing phase, the potential of the second intermediate node N2 of the compensation transistor T3 and the potential of the second pole of the compensation transistor T3 both change due to the potential transition of the second Scan signal Scan2, and accordingly, the gate potential of the driving transistor DT changes due to the transition of the second Scan signal Scan 2. The compensation transistor T3 is a P-type transistor, the active potential signal of the second Scan signal Scan2 is a low potential signal, and the inactive potential signal is a high potential signal, so that at the end of the data writing phase, the second Scan signal Scan2 jumps from a low potential signal to a high potential signal, and accordingly, the gate potential of the driving transistor DT and the potential of the second intermediate node N2 of the compensation transistor T3 will rise accordingly, and since the capacitance value of the fourth capacitor C4 is smaller than that of the storage capacitor Cst, the potential rise amount of the gate of the driving transistor DT is smaller than that of the second intermediate node N2. By arranging the second leakage suppressing module 180 to include the second control transistor T7, so that the voltage at the end of the light emitting phase where the fourth capacitor C4 is connected to the second control transistor T7 is reduced relative to the data writing phase, thereby causing the potential of the second intermediate node N2 of the compensation transistor T3 to which the fourth capacitor C4 is connected to be coupled down, further, during the light emitting period, the potential difference between the second intermediate node N2 of the compensation transistor T3 and the gate of the driving transistor DT is also decreased, thereby further reducing the leakage of the sub-transistor between the second intermediate node N2 of the compensation transistor T3 and the gate of the driving transistor DT connected by the second leakage suppression module 180, that is, the leakage of the compensating transistor T3 is further reduced, so that the stability of the gate potential of the driving transistor DT during the light emitting period is further ensured, and the flicker phenomenon of the display panel is further improved.

Fig. 10 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present invention, and referring to fig. 10, optionally, the first light-emitting control module 160 and the second light-emitting control module 170 are configured to be turned on in a plurality of light-emitting sub-phases included in the light-emitting phase, and the driving transistor DT is configured to drive the light-emitting modules to emit light in the light-emitting sub-phases;

the pixel circuit further comprises a second initialization module 180 and a third initialization module 190, a control terminal of the second initialization module 180 and a control terminal of the third initialization module 190 are connected to the reset control signal EMR, the second initialization module 180 is configured to write a second initialization voltage Vref2 to the first pole of the driving transistor DT in a plurality of reset sub-phases included in the light-emitting phase, and the third initialization module 190 is configured to write a third initialization voltage Vref3 to the second pole of the driving transistor DT and the first pole of the light-emitting device D1 in the reset sub-phases, wherein each reset phase corresponds to one light-emitting sub-phase and the reset sub-phase precedes the corresponding light-emitting sub-phase.

Optionally, the second initialization module 180 includes a second initialization transistor T8, and the third initialization module 190 includes a third initialization transistor T9. Optionally, the second initialization voltage Vref2 is equal to the first initialization voltage Vref1 or the first power voltage input from the first power voltage input terminal VDD. Optionally, the third initialization voltage Vref3 is equal to the first initialization voltage Vref 1.

Optionally, the first terminal of the third initialization module 190 is connected to the third initialization voltage Vref3, and the second terminal of the third initialization module 190 is electrically connected to the first pole of the light emitting device D1 or the second terminal of the third initialization module 190 is electrically connected to the second pole of the driving transistor DT (fig. 10 schematically shows that the second terminal of the third initialization module 190 is electrically connected to the first pole of the light emitting device D1); wherein, there is an overlap of the reset control signal EMR with the active level of the second emission control signal EM2, there is an overlap of the active levels of the first emission control signal EM1 and the second emission control signal EM2, and the active level of the reset control signal EMR precedes the active level of the first emission control signal EM 1.

Fig. 11 is a driving timing diagram of another pixel circuit according to an embodiment of the invention, where the driving timing diagram can be used to drive the pixel circuit shown in fig. 10, where each transistor in the pixel circuit shown in fig. 10 can be a P-type transistor. Referring to fig. 10 and 11, the operation process of the pixel circuit includes an initialization phase t01, a data writing phase t11, and a light emitting phase t21, wherein the light emitting phase t21 includes a plurality of light emitting sub-phases t212 and a plurality of reset sub-phases t 211.

In the initialization period T01, the first Scan signal Scan1 is at a low level, the first initialization transistor T1 is turned on, and the first initialization voltage Vref1 is transmitted to the gate of the driving transistor DT. Thus, at the completion of the initialization phase T01, the potentials of the gate of the driving transistor DT and the first intermediate node N1 of the first initialization transistor T1 are both equal to the first initialization voltage Vref 1.

In the data writing phase T11, the second Scan signal Scan2 is at a low level, the data writing transistor T2 and the compensation transistor T3 are turned on, the data voltage Vdata is written to the gate of the driving transistor DT through the data writing transistor T2, the driving transistor DT and the compensation transistor T3, until the gate voltage of the driving transistor DT is equal to Vdata + Vth (where Vth represents the threshold voltage of the driving transistor DT), the driving transistor DT is turned off, and the writing of the data voltage Vdata to the gate of the driving transistor DT and the compensation of the threshold voltage of the driving transistor DT are realized. When the data writing phase T11 is completed, the voltage of the gate of the driving transistor DT and the voltage of the second intermediate node N2 of the compensation transistor T3 are both equal to Vdata + Vth.

In the reset sub-phase T211 of the lighting phase T21, the first lighting control signal EM1 is at a high level, and the first lighting control transistor T4 is turned off; the second emission control signal EM2 is at a low level, and the second emission control transistor T5 is turned on. The reset control signal EMR is low level, the second initialization transistor T8 and the third initialization transistor T9 are both turned on, the second initialization voltage Vref2 is written to the first pole of the driving transistor DT through the second initialization transistor T8 to realize the reset of the first pole of the driving transistor DT, the third initialization voltage Vref3 is written to the first pole of the light emitting device D1 through the third initialization transistor T9, wherein the first pole of the light emitting device D1 may be the anode of the light emitting device D1 to realize the reset of the anode of the light emitting device D1; and the third initialization voltage Vref3 is transmitted to the second pole of the driving transistor DT through the third initialization transistor T9 and the second light emission controlling transistor T5, and the reset of the second pole of the driving transistor DT is implemented.

It should be noted that, when the second end of the third initialization module is electrically connected to the second pole of the driving transistor, in the reset sub-stage of the light emitting stage, the third initialization voltage is written into the second pole of the driving transistor through the third initialization transistor, so as to reset the second pole of the driving transistor; and the third initialization voltage is transmitted to the first pole of the light emitting device through the third initialization transistor and the second light emitting control transistor, wherein the first pole of the light emitting device can be the anode of the light emitting device, so that the anode of the light emitting device is reset;

in the light-emitting sub-phase T212 of the light-emitting phase T21, the first and second light-emitting control signals EM1 and EM2 are both low level, the first and second light-emitting control transistors T4 and T5 are turned on, and the driving transistor DT drives the light-emitting device D1 to emit light.

The pixel circuit of this embodiment, by providing that the pixel circuit further includes a second initialization module 180 and a third initialization module 190, a control terminal of the second initialization module 180 and a control terminal of the third initialization module 190 are connected to the reset control signal EMR, the second initialization module 180 is configured to write a second initialization voltage Vref2 to a first pole of the driving transistor DT in a plurality of reset sub-phases t211 included in a light-emitting phase t21, the third initialization module 190 is configured to write a third initialization voltage Vref3 to a second pole of the driving transistor DT and a first pole of the light-emitting device D1 in the reset sub-phases t211, wherein each reset phase corresponds to one light-emitting sub-phase t212, the reset sub-phase t211 precedes the corresponding light-emitting sub-phase t212, such that, for a display panel including the pixel circuit of this embodiment, after each reset sub-phase t211, the potential of the first pole of the driving transistor DT in the pixel circuit is equal, the potentials of the second poles of the driving transistors DT are also equal. Since the light-emitting sub-phase t212 is performed after the corresponding reset sub-phase t211, and before entering each light-emitting sub-phase t212, the potentials of the first electrodes of the driving transistors DT are equal, the potentials of the second electrodes of the driving transistors DT are equal, and the influence degrees of the potentials of the first electrodes and the second electrodes of the driving transistors DT on the driving current generated by the driving transistors DT are the same, the light-emitting intensities of the light-emitting devices D1 are more uniform, so that the difference of the light-emitting brightness of the light-emitting devices D1 in different light-emitting sub-phases t212 is reduced, the visual effect is improved, and the overall display effect is further improved. In addition, the potentials of the first electrodes of the light emitting devices D1 in the pixel circuits are equal, so that the light emitting sub-phase t212 and the light emitting device D1 have the same light emitting process, and correspondingly, the light emitting brightness of the light emitting devices D1 is more consistent, thereby further improving the visual effect of human eyes and further improving the display effect. In the reset sub-stage before each light-emitting sub-stage, the first pole of the light-emitting device D1 is reset to the third initialization voltage, so that the problem that the potential at the first end of the light-emitting sub-stage light-emitting device gradually increases due to the increase of the second pole potential of the driving transistor DT after the first light-emitting control module 160 and the second light-emitting control module 170 are turned off in multiple light-emitting sub-stages and the light-emitting device is more and more easily turned on but is difficult to turn off in a dark state can be avoided, and thus a higher dark-state data voltage does not need to be set in the driving chip, and the power consumption of the driving chip is saved.

In addition, the pixel circuit of this embodiment, by setting that the pixel circuit includes the first leakage suppression module 140 and the second leakage suppression module 180, the gate potential of the driving transistor can be well maintained in the light-emitting phase, so that the driving currents generated by the driving transistor in each light-emitting sub-phase of the light-emitting phase can be relatively consistent, the light-emitting brightness of the light-emitting devices in each light-emitting sub-phase of the light-emitting phase is further ensured to be consistent, and the display effect is improved.

An embodiment of the present invention further provides a display panel, where the display panel includes the pixel circuit according to any of the above embodiments of the present invention.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A pixel circuit, comprising: the device comprises a driving transistor, a data writing module, a storage module, a first initialization module and a first electric leakage suppression module;

the first initialization module is used for writing a first initialization voltage into the grid electrode of the driving transistor in an initialization stage; the first initialization module comprises at least two first sub-transistors connected in series, adjacent first sub-transistors are electrically connected through a first intermediate node therebetween, the first leakage suppression module is electrically connected with at least one first intermediate node, and the first leakage suppression module is used for positively correlating the variation of the gate potential of the driving transistor to the first intermediate node to which the first leakage suppression module is connected;

the data writing module is used for writing data voltage to the grid electrode of the driving transistor in a data writing stage; the storage module is used for storing the grid voltage of the driving transistor.

2. The pixel circuit according to claim 1, wherein the first leakage suppression module comprises a first capacitor having a first plate electrically connected to the gate of the driving transistor and a second plate electrically connected to at least one of the first intermediate nodes.

3. The pixel circuit according to claim 1, wherein in the first initialization block, a channel width-to-length ratio of the first sub-transistor between the first intermediate node to which the first leakage suppression block is connected and a first terminal of the first initialization block is smaller than a channel width-to-length ratio of the first sub-transistor between the first intermediate node to which the first leakage suppression block is connected and a second terminal of the first initialization block; the first end of the first initialization module is connected to the first initialization voltage, and the second end of the first initialization module is connected to the grid electrode of the driving transistor;

preferably, a channel width of the first sub-transistor between the first intermediate node to which the first leakage suppression module is connected and the first end of the first initialization module is less than or equal to 1.8 micrometers, and a channel length is greater than or equal to 4 micrometers.

4. The pixel circuit according to claim 1, further comprising a compensation module for writing information including a threshold voltage of the driving transistor to a gate of the driving transistor in a data writing phase;

preferably, a control end of the first initialization module is connected to a first scanning signal, a first end of the first initialization module is connected to a first initialization voltage, and a second end of the first initialization module is electrically connected to a gate of the driving transistor;

preferably, a control end of the data writing module is connected to a second scanning signal, a first end of the data writing module is connected to a data voltage, and a second end of the data writing module is electrically connected to the first pole of the driving transistor; the control end of the compensation module is connected to the second scanning signal, the first end of the compensation module is electrically connected with the second pole of the driving transistor, and the second end of the compensation module is electrically connected with the grid electrode of the driving transistor;

preferably, the pixel circuit further includes a first light-emitting control module and a second light-emitting control module, the first light-emitting control module is configured to control a conduction state between a first power voltage input end and a first pole of the driving transistor according to a first light-emitting control signal accessed by a control end of the first light-emitting control module, the second light-emitting control module is configured to control a conduction state between a second pole of the driving transistor and a first pole of the light-emitting device according to a second light-emitting control signal accessed by the control end of the second light-emitting control module, and the second pole of the light-emitting device is connected to the second power voltage input end.

5. The pixel circuit according to claim 4, wherein the first leakage suppression module comprises a connection line connecting at least one of the second intermediate nodes and at least one of the first intermediate nodes.

6. The pixel circuit according to claim 5, wherein the first leakage suppression module further comprises a second capacitor, one end of the second capacitor is connected to a fixed voltage, and the other end of the second capacitor is electrically connected to the connection line.

7. The pixel circuit according to claim 4, further comprising a second leakage suppression module, wherein the second leakage suppression module comprises a third capacitor, a first end of the third capacitor is connected to a fixed voltage, and a second end of the third capacitor is electrically connected to at least one of the second intermediate nodes;

preferably, in the compensation module, a channel width-to-length ratio of the second sub-transistor between the second intermediate node to which the second leakage suppression module is connected and the second pole of the driving transistor is smaller than a channel width-to-length ratio of the second sub-transistor between the second intermediate node to which the second leakage suppression module is connected and the gate of the driving transistor;

preferably, a channel width of the second sub-transistor between the second intermediate node to which the second leakage suppression module is connected and the second pole of the driving transistor is less than or equal to 1.8 micrometers, and a channel length of the second sub-transistor between the second intermediate node to which the second leakage suppression module is connected and the second pole of the driving transistor is greater than or equal to 4 micrometers.

8. The pixel circuit according to claim 4, further comprising a second leakage suppression module, the second leakage suppression module comprising a fourth capacitor and a first control transistor;

a gate of the first control transistor is connected to the second scanning signal, a first pole of the first control transistor is connected to a first fixed voltage, a second pole of the first control transistor is electrically connected to a first end of the fourth capacitor, and a second end of the fourth capacitor is electrically connected to at least one second intermediate node;

preferably, the second leakage suppression module further includes a second control transistor, a gate of the second control transistor is connected to the first light emission control signal or the second light emission control signal, a first pole of the second control transistor is connected to a second fixed voltage, and a second pole of the second control transistor is electrically connected to the first end of the fourth capacitor; wherein the second fixed voltage is less than the first fixed voltage;

preferably, a capacitance value of the fourth capacitor is smaller than a capacitance value of a storage capacitor included in the storage module.

9. The pixel circuit according to claim 4, wherein the first and second light emission control modules are configured to be turned on during a plurality of light emission sub-phases included in a light emission phase, and the driving transistor is configured to drive the light emission module to emit light during the light emission sub-phases;

the pixel circuit further comprises a second initialization module and a third initialization module, wherein a control terminal of the second initialization module and a control terminal of the third initialization module are connected with a reset control signal, the second initialization module is used for writing a second initialization voltage into a first pole of a driving transistor in a plurality of reset sub-phases included in a light-emitting phase, and the third initialization module is used for writing a third initialization voltage into a second pole of the driving transistor and a first pole of the light-emitting device in the reset sub-phases, wherein each reset phase corresponds to one light-emitting sub-phase, and the reset sub-phases are before the corresponding light-emitting sub-phases;

preferably, a first end of the third initialization module is connected to the third initialization voltage, and a second end of the third initialization module is electrically connected to the first pole of the light emitting device or the second end of the third initialization module is electrically connected to the second pole of the driving transistor; wherein the reset control signal overlaps an active level of the second emission control signal, and the first emission control signal overlaps an active level of the second emission control signal, the active level of the reset control signal preceding the active level of the first emission control signal.

10. A display panel comprising the pixel circuit according to any one of claims 1 to 9.