CN112289267A - Pixel circuit and display panel - Google Patents
Pixel circuit and display panel Download PDFInfo
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- CN112289267A CN112289267A CN202011194234.6A CN202011194234A CN112289267A CN 112289267 A CN112289267 A CN 112289267A CN 202011194234 A CN202011194234 A CN 202011194234A CN 112289267 A CN112289267 A CN 112289267A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
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Abstract
The embodiment of the invention discloses a pixel circuit and a display panel, wherein the pixel circuit comprises a leakage suppression module, the leakage suppression module comprises a first double-gate transistor, the middle node of the first double-gate transistor is electrically connected with an initialization signal input end through a first coupling capacitor, the voltage input by the initialization signal input end is constant and is always an initialization voltage, the voltage of a polar plate connected with the initialization signal input end of the first coupling capacitor is constant, and further when the first double-gate transistor is turned off, the voltage of the polar plate connected with the middle node of the first double-gate transistor of the first coupling capacitor is also constant and cannot be influenced by the jump of other signals in the display panel, so that the potential of the middle node of the first double-gate transistor is stable, the leakage current of the first double-gate transistor is smaller, the leakage current of the grid of a driving transistor is improved, and the brightness attenuation of the display panel in one frame is reduced, thereby improving the flicker phenomenon of the display panel and improving the display quality.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a pixel circuit and a display panel.
Background
With the development of display technology, the requirements on display quality are higher and higher.
The conventional display panel generally comprises a plurality of pixel circuits, and the conventional display panel has the problems that the display quality is affected due to the flicker phenomenon easily generated during display.
Disclosure of Invention
The invention provides a pixel circuit and a display panel, which aim to solve the problem of electric leakage of a grid electrode of a driving transistor, reduce the flicker phenomenon of the display panel and improve the display quality.
In a first aspect, an embodiment of the present invention provides a pixel circuit, including: the device comprises a driving transistor, a first initialization module and a leakage suppression module; the first initialization module is used for transmitting an initialization signal input by the initialization signal input end to a first pole of the light-emitting device in an initialization stage;
the leakage suppression module is electrically connected with the grid electrode of the driving transistor and comprises a first double-gate transistor and a first coupling capacitor, and the middle node of the first double-gate transistor is electrically connected with the initialization signal input end through the first coupling capacitor.
Optionally, the first double-gate transistor includes a first sub-transistor and a second sub-transistor, the first sub-transistor and the second sub-transistor are connected in series through the active layer, and a common node at which the first sub-transistor and the second sub-transistor are connected in series serves as an intermediate node of the first double-gate transistor.
Optionally, the initialization signal input terminal is electrically connected to an initialization signal line, and the initialization signal line overlaps with an active layer of the first sub-transistor and the second sub-transistor connected in series to form a first coupling capacitor.
Optionally, the first initialization module includes a first initialization transistor, a gate of the first initialization transistor is electrically connected to the first scan signal input terminal, a first pole of the first initialization transistor is electrically connected to the initialization input terminal, and a second pole of the first initialization transistor is electrically connected to the first pole of the light emitting device; a first double-gate transistor of the electric leakage suppression module is used as a compensation transistor of the pixel circuit; the pixel circuit further includes a data writing transistor, a first light emission control transistor, and a second light emission control transistor; a first pole of the driving transistor is electrically connected with the first power voltage input end through the first light-emitting control transistor, and a second pole of the driving transistor is electrically connected with the first pole of the light-emitting device through the second light-emitting control transistor; the first grid and the second grid of the compensation transistor are electrically connected with the second scanning signal input end, and the compensation transistor is connected between the grid of the driving transistor and the second pole of the driving transistor; the gate of the data writing transistor is electrically connected to the second scanning signal input terminal, the first pole of the data writing transistor is electrically connected to the data voltage input terminal, and the second pole of the data writing transistor is electrically connected to the first pole of the driving transistor.
Optionally, the pixel circuit further includes a second initialization module, where the second initialization module includes a second double-gate transistor, a first gate and a second gate of the second double-gate transistor are electrically connected to the third scan signal input terminal, and the second double-gate transistor is connected between the initialization input terminal and the gate of the driving transistor; the second double-gate transistor comprises a third sub-transistor and a fourth sub-transistor which are connected in series through the active layer; the first power supply voltage input end is electrically connected with a first power supply line, and an active layer between the third sub-transistor and the fourth sub-transistor is overlapped with the first power supply line to form a second coupling capacitor.
In a second aspect, an embodiment of the present invention further provides a display panel, including the pixel circuit of the first aspect.
Optionally, the display panel further includes a plurality of initialization signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, and a plurality of light-emitting control lines extending along the first direction, a first scanning signal line, an initialization signal line, and a second scanning signal line are included in a region between two adjacent light-emitting control signal lines, and in a region between two adjacent light-emitting control signal lines, in the second direction, the initialization signal line is located between the first scanning signal line and the second scanning signal line; the second direction intersects the first direction.
Optionally, the display panel includes an active layer, a first metal layer and a second metal layer, which are stacked, wherein the first scanning signal line and the second scanning signal line are located in the first metal layer, and the initialization signal line is located in the second metal layer;
the second scanning signal line includes a first main body portion extending in the first direction and a plurality of first protrusion portions, the active layer includes a first active portion extending in the first direction and overlapping the first protrusion portions, and a second active portion contiguous with the first active portion and extending in the second direction, the second active portion overlapping the first main body portion;
the first bulge part and the first active part are overlapped to form a first sub transistor, and the first main body part and the second active part are overlapped to form a second sub transistor;
the initialization signal line comprises a second main body part extending along the first direction and a second bulge part bulging out of the main body part in the second direction, and the second active part is overlapped with at least part of the second bulge part; the protruding directions of the first protruding part and the second protruding part are opposite;
preferably, the second active portion extends to the second body portion along the second direction.
Optionally, in an area between two adjacent light emission control signal lines, in the first direction, the first initialization transistor is located on a side of the second protrusion portion away from the first protrusion portion;
in the first direction, the second sub-transistor is located between the first sub-transistor and the first initialization transistor.
Optionally, the display panel further includes a plurality of block-shaped first electrodes arranged in an array, and the first initialization transistor is located between two adjacent rows of the first electrodes along the first direction; in the second direction, the first initialization transistor is positioned between the first electrodes of two adjacent columns;
the first pole of the first initialization transistor, which is positioned between the first electrodes of the ith row and the (i + 1) th row in the first direction, is electrically connected with the first electrode of the jth column in the ith row in the second direction, and the second pole of the first initialization transistor is electrically connected with the second initialization transistor connected with the first electrodes of the (i + 1) th row and the (j + 1) th column in the ith row; wherein i is more than or equal to 1, and j is more than or equal to 1.
The pixel circuit and the display panel provided by the embodiment of the invention have the advantages that the pixel circuit comprises the electric leakage suppression module, the electric leakage suppression module comprises the first double-gate transistor, the middle node of the first double-gate transistor is electrically connected with the initialization signal input end through the first coupling capacitor, the voltage input by the initialization signal input end is constant and is always the initialization voltage, the voltage of the polar plate connected with the initialization signal input end through the first coupling capacitor is constant, the voltage of the polar plate connected with the middle node of the first double-gate transistor through the first coupling capacitor is constant when the first double-gate transistor is turned off, the voltage of the polar plate connected with the middle node of the first double-gate transistor through the first coupling capacitor is not influenced by the jump of other signals in the display panel, the potential of the middle node of the first double-gate transistor is stable, the leakage current of the first double-gate transistor is smaller, the electric leakage of, thereby improving the flicker phenomenon of the display panel and improving the display quality.
Drawings
Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 4 is a driving timing diagram of a pixel circuit according to an embodiment of the invention;
fig. 5 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a prior art display panel;
fig. 7 is a schematic structural diagram of an active layer and a first metal layer in a display panel according to an embodiment of the invention;
fig. 8 is a schematic structural diagram of an active layer, a first metal layer, and a second metal layer in a display panel according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background art, the conventional display panel has a problem that a flicker phenomenon is easily generated when displaying, which affects display quality. The inventor researches and finds that the above problem occurs because the conventional pixel circuit includes a driving transistor and a switching transistor electrically connected to the gate of the driving transistor, and the leakage current of the switching transistor is large, so that the leakage current of the gate of the driving transistor is serious, and the display brightness in one frame is greatly attenuated, so that the display panel flickers. In the conventional pixel circuit, it is common to reduce the leakage current by providing a switching transistor connected to a driving transistor as a double gate transistor. However, after the switching transistor connected to the driving transistor is a dual-gate transistor, there still exists a problem that when the dual-gate transistor is turned off, the middle node of the dual-gate transistor is floated, so that the potential of the middle node is easily affected by other signals in the display panel, which causes the potential of the middle node of the dual-gate transistor to be unstable, and the leakage current may still be large, which still causes the problem of flicker of the display panel.
For the above reasons, an embodiment of the present invention provides a pixel circuit, and fig. 1 is a schematic structural diagram of the pixel circuit provided in the embodiment of the present invention, and referring to fig. 1, the pixel circuit includes: a driving transistor DT, a first initialization module 110, and a leakage suppression module 120; the first initialization module 110 is configured to transmit an initialization signal input from the initialization signal input terminal Vref to a first pole of the light emitting device D1 in an initialization phase; the leakage suppression module 120 is electrically connected to the gate of the driving transistor DT, the leakage suppression module 120 includes a first double-gate transistor 121 and a first coupling capacitor C1, and an intermediate node of the first double-gate transistor 121 is electrically connected to the initialization signal input terminal Vref through the first coupling capacitor C1.
Wherein the first double-gate transistor 121 includes a first sub-transistor T11 and a second sub-transistor T12, the first sub-transistor T11 and the second sub-transistor T12 are connected in series through an active layer, wherein a common node at which the first sub-transistor T11 and the second sub-transistor T12 are connected in series serves as an intermediate node of the first double-gate transistor 121.
The pixel circuit of this embodiment is configured such that the pixel circuit includes a leakage suppression module, the leakage suppression module includes a first double-gate transistor, an intermediate node of the first double-gate transistor is electrically connected to the initialization signal input terminal through a first coupling capacitor, and since a voltage input by the initialization signal input terminal is constant and is always an initialization voltage, a voltage of a plate connected to the first coupling capacitor and the initialization signal input terminal is constant, and further when the first double-gate transistor is turned off, a voltage of a plate connected to the intermediate node of the first double-gate transistor of the first coupling capacitor is also constant and is not affected by other signal jumps in the display panel, so that a potential of the intermediate node of the first double-gate transistor is stable, and further a leakage current of the first double-gate transistor is small, leakage current of a gate of the driving transistor is improved, and luminance attenuation of the display panel in one frame is reduced, thereby improving the flicker phenomenon of the display panel and improving the display quality.
The above is the core idea of the present invention, and the following will clearly and completely describe the technical solution in the embodiment of the present invention with reference to the drawings in the embodiment of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.
Fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention, where the display panel includes a pixel circuit according to any embodiment of the present invention, and referring to fig. 2, optionally, the initialization signal input terminal Vref is electrically connected to an initialization signal line Ref, and the initialization signal line Ref overlaps with an active layer of the first sub-transistor T11 and the second sub-transistor T12 connected in series to form a first coupling capacitor C1.
Specifically, an initialization signal line Ref is arranged to overlap with an active layer of the first sub-transistor T11 and the second sub-transistor T12 connected in series to form a first coupling capacitor C1, where the initialization signal line Ref and the initialization signal line Ref at an overlapping position of the active layer of the first sub-transistor T11 and the second sub-transistor T12 connected in series are used as one plate of the first coupling capacitor C1, and the active layer of the first sub-transistor T11 and the second sub-transistor T12 connected in series is used as the other plate of the first coupling capacitor C1, so that a capacitor structure is formed without additionally arranging a metal layer in the display panel, and the number of film layers of the display panel is not increased, and the first coupling capacitor C1 is formed to keep the potential of the middle node of the first double-gate transistor stable, and the thickness of the display panel is not increased, which is beneficial to realize the lightness and thinness of the display panel.
Fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the invention, and referring to fig. 3, optionally, the first initialization module 110 includes a first initialization transistor T2, a gate of the first initialization transistor T2 is electrically connected to the first Scan signal input terminal Scan1, a first pole of the first initialization transistor T2 is electrically connected to the initialization signal input terminal, a second pole of the first initialization transistor T2 is electrically connected to the first pole of the light emitting device D1, and a second pole of the light emitting device D1 is electrically connected to the second power voltage input terminal VSS; the first double-gate transistor 121 of the leakage suppression module 120 serves as a compensation transistor of the pixel circuit; the pixel circuit further includes a data writing transistor T3, a first light emission controlling transistor T4, and a second light emission controlling transistor T5; a first pole of the driving transistor DT is electrically connected to the first power voltage input terminal VDD through the first light emission control transistor T4, and a second pole of the driving transistor DT is electrically connected to the first pole of the light emitting device D1 through the second light emission control transistor T5; the first gate electrode and the second gate electrode of the compensation transistor are electrically connected to the second Scan signal input terminal Scan2, and the compensation transistor is connected between the gate electrode of the driving transistor DT and the second pole of the driving transistor DT; the gate of the data writing transistor T3 is electrically connected to the second Scan signal input terminal Scan2, the first pole of the data writing transistor T3 is electrically connected to the data voltage input terminal, and the second pole of the data writing transistor T3 is electrically connected to the first pole of the driving transistor DT. The pixel circuit further includes a storage capacitor Cst.
Fig. 4 is a driving timing diagram of a pixel circuit according to an embodiment of the present invention, where the driving timing diagram shown in fig. 4 can be used to drive the pixel circuit shown in fig. 3, where each transistor included in the pixel circuit may be a P-type transistor or an N-type transistor, and all the transistors included in the pixel circuit are illustrated as P-type transistors in fig. 3. Referring to fig. 3 and 4, the operation process of the pixel circuit shown in fig. 3 may include an initialization phase t1, a data writing phase t2, and a light emitting phase t 3.
In the initialization period T1, a low level signal is input from the first Scan signal input terminal Scan1, the first initialization transistor T2 is turned on, and the initialization voltage input from the initialization signal input terminal Vref is transmitted to the first electrode of the light emitting device D1, and optionally, when the light emitting device D1 is the organic light emitting device D1, the first electrode of the light emitting device D1 is the anode of the light emitting device D1.
In the data writing phase T2, the second Scan signal input terminal Scan2 inputs a low level signal, the data writing transistor T3 and the compensation transistor are turned on, the data voltage is turned on through the data writing transistor T3 and the compensation transistor, the data voltage is written to the gate electrode of the driving transistor DT through the data writing transistor T3, the driving transistor DT and the compensation transistor, and, in the data writing phase, compensation for the threshold voltage of the driving transistor DT is achieved.
In the light emitting period T3, a low level signal is input to the light emitting control signal input end Emit, the first light emitting control transistor T4 and the second light emitting control transistor T5 are turned on, and the driving transistor DT drives the light emitting device D1 to Emit light.
As can be known from the above analysis of the working process of the pixel circuit, the compensation transistor is turned on only in the data writing stage, and is turned off in both the initialization stage and the light emitting stage, because one plate of the first coupling capacitor C1 is connected to the intermediate node between the first sub-transistor T11 and the second sub-transistor T12 of the compensation transistor, and the other plate is electrically connected to the initialization signal input terminal Vref, and the initialization voltage input by the initialization signal input terminal Vref is constant, the potential of the intermediate node between the first sub-transistor T11 and the second sub-transistor T12 is fixed in the initialization stage and the light emitting stage, and further the leakage current of the compensation transistor is small, and the flicker phenomenon of the display panel is improved.
Fig. 5 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present invention, and referring to fig. 5, optionally, the pixel circuit further includes a second initialization module 130, where the second initialization module 130 includes a second double-gate transistor 131, a first gate and a second gate of the second double-gate transistor 131 are electrically connected to a third Scan signal input terminal Scan3, and the second double-gate transistor 131 is connected between an initialization signal input terminal Vref and a gate of the driving transistor DT;
the second double-gate transistor 131 includes a third sub-transistor T61 and a fourth sub-transistor T62, the third sub-transistor T61 and the fourth sub-transistor T62 being connected in series through an active layer; the first power voltage input terminal VDD is electrically connected to the first power line ELVDD, and the active layer between the third and fourth sub-transistors T61 and T62 overlaps the first power line ELVDD to form a second coupling capacitor.
Since the second double-gate transistor 131 is electrically connected to the gate of the driving transistor DT, the magnitude of the leakage current of the second double-gate transistor 131 also affects the degree of the leakage current of the driving transistor DT. In the pixel circuit of this embodiment, the middle node of the second double-gate transistor 131 is electrically connected to the first power voltage input terminal VDD through the second coupling capacitor, the first power voltage input terminal VDD is electrically connected to the first power line ELVDD, wherein the voltage on the first power line ELVDD is constant, so that when the second double-gate transistor 131 is turned off, the potential of the middle node of the third sub-transistor T61 and the fourth sub-transistor T62 can be kept constant, which is favorable for reducing the leakage current of the second double-gate transistor 131, so that the gate potential of the driving transistor DT can be more stable, thereby reducing the luminance change of the display panel within one frame, and improving the flicker phenomenon of the display panel. With reference to fig. 2, in the pixel circuit of this embodiment, the active layer between the third sub-transistor T61 and the fourth sub-transistor T62 is overlapped with the first power line ELVDD to form a second coupling capacitor, so that a capacitor structure is formed without additionally disposing a metal layer in the display panel, and the number of the film layers of the display panel is not increased.
The pixel circuits are arranged in the display panel in an array mode, and for two adjacent rows of pixel circuits, the first scanning signal input end of the pixel circuit in the previous row and the third scanning signal input end of the pixel circuit in the next row are connected with the same first scanning signal line.
An embodiment of the present invention further provides a display panel, where the display panel includes the pixel circuit provided in any of the above embodiments of the present invention, and a schematic structural diagram of the display panel may refer to fig. 2.
With continued reference to fig. 2, optionally, the display panel further includes a plurality of initialization signal lines Ref, a plurality of first scan signal lines S1, a plurality of second scan signal lines S2, and a plurality of emission control signal lines EM extending along the first direction x, a region between two adjacent emission control signal lines EM includes one first scan signal line S1, one initialization signal line Ref, and one second scan signal line S2, and a region between two adjacent emission control signal lines is between the first scan signal line S1 and the second scan signal line S2 in the second direction y; the second direction y intersects the first direction x.
Here, the initialization signal line Ref may be electrically connected to an initialization signal input terminal of the pixel circuit in the above-described embodiment of the present invention, the first scan signal line S1 may be electrically connected to the first scan signal input terminal, the second scan signal line S2 may be electrically connected to the second scan signal input terminal, and the emission control signal line EM may be electrically connected to the emission control signal input terminal.
Fig. 6 is a schematic structural diagram of a display panel in the prior art, wherein only a part of the structure of the display panel is shown in fig. 6, and referring to fig. 6, in the region between two adjacent light emission control signal lines (not shown in the figure), an initialization signal line Ref is usually disposed on one side of the first scanning signal line S1 away from the second scanning signal line S2, so that the distance between an active layer (an active layer in the region outlined by a dotted line in fig. 5) connecting two sub-transistors in a dual-gate transistor, which is formed by overlapping the second scanning signal line S2 with the active layer, and the initialization signal line Ref is relatively long, and it is difficult to achieve the overlapping of the initialization signal line Ref and the active layer of the dual-gate transistor.
Unlike the display panel shown in fig. 6, in the display panel of this embodiment, in the region between two adjacent light emission control signal lines EM, in the second direction y, the initialization signal line Ref is located between the first scanning signal line S1 and the second scanning signal line S2, that is, with respect to the display panel shown in fig. 6, in the display panel of this embodiment, the initialization signal line Ref is reversed with respect to the first scanning signal line S1, so that the initialization signal line Ref easily overlaps with the active layer at the set position, which is the active layer of two sub-transistors (the first sub-transistor and the second sub-transistor) connected in series in the dual-gate transistor (i.e., the first dual-gate transistor 121 in the above embodiment) formed by overlapping the second scanning signal line Ref with the active layer, so that the first coupling capacitor C1 can be formed by the overlapping of the initialization signal line Ref with the active layer, and when the first dual-gate transistor 121 is turned off, the potential of the middle node of the first double-gate transistor 121 is stabilized by the first coupling capacitor C1, so that the first double-gate transistor 121 is ensured to have a smaller leakage current.
Fig. 7 is a schematic structural diagram of an active layer and a first metal layer in a display panel provided in an embodiment of the invention, and fig. 8 is a schematic structural diagram of an active layer, a first metal layer and a second metal layer in a display panel provided in an embodiment of the invention. With reference to fig. 2, 7 and 8, optionally, the display panel includes an active layer 210, a first metal layer 220 and a second metal layer 230, which are stacked, wherein the first scanning signal line S1 and the second scanning signal line S2 are located in the first metal layer 220, and the initialization signal line Ref is located in the second metal layer 230; the display panel may further include a third metal layer, and the first power line ELVDD and the Data line Data in the display panel are located in the third metal layer.
The second scan signal line S2 includes a first main body portion S21 and a plurality of first protrusion portions S22 extending in the first direction x, the active layer includes a first active portion 211 extending in the first direction x and overlapping the first protrusion portions S22, and a second active portion 212 contiguous with the first active portion 211 and extending in the second direction y, the second active portion 212 overlapping the first main body portion S21; the first protrusion S22 overlapping the first active portion 211 to form a first sub-transistor T11, and the first body portion S21 overlapping the second active portion 212 to form a second sub-transistor T12; the initialization signal line Ref includes a second main body portion Ref1 extending in the first direction x and a second protrusion portion Ref2 protruding the main body portion in the second direction y, the second active portion 212 overlapping with at least a part of the second protrusion portion Ref 2; the projecting directions of the first projecting portion S22 and the second projecting portion Ref2 are opposite.
Specifically, the active layer connecting the first sub-transistor T11 and the second sub-transistor T12 may serve as an intermediate node of the first double-gate transistor 121 to which the second active portion 212 between the first scan signal line S1 and the second scan signal line S2 is connected, and the second active portion 212 and the overlapping second protrusion portion Ref2 form a first coupling capacitor C1, so that the potential of the intermediate node of the first double-gate transistor 121 may be maintained stable when the first double-gate transistor 121 is turned off. The first protrusion S22 of the active layer is opposite to the protrusion direction of the second protrusion Ref2 of the initialization signal line Ref (i.e., the protrusion directions of the first protrusion S22 and the second protrusion Ref2 are opposite, the first protrusion S22 protrudes in a direction close to the initialization signal line Ref, and the second protrusion Ref2 protrudes in a direction of the second scan line S2), the active layer between the first sub-transistor T11 and the second sub-transistor T12 of the first double-gate transistor 121 may be located at a side of the first main body portion of the second scan signal line S2 close to the initialization signal line Ref, so that the second protrusion Ref2 of the initialization signal line Ref may overlap the active layer between the first and second sub-transistors T11 and T12 (i.e., the active layer connecting the first and second sub-transistors T11 and T12 in series), thereby ensuring that the formation of the first coupling capacitor C1 may be easily achieved.
With reference to fig. 2, 7 and 8, the second active portion 212 extends to the second main body portion Ref1 along the second direction y, so that the overlapping area between the second active portion 212 and the second main body portion Ref1 is relatively large, and the overlapping area between the second active portion 212 and the second main body portion Ref1 is increased because the capacitance is related to the positive area of the plate, so that the capacitance of the first coupling capacitor C1 is increased, and further when the first double-gate transistor 121 is turned off, the potential of the intermediate node can be better maintained, which is more beneficial to reducing the leakage current of the first double-gate transistor 121, and further improves the flicker phenomenon of the display.
Continuing to refer to fig. 8 in conjunction with the pixel circuit shown in fig. 5, where fig. 2 shows the positions of the transistors in the pixel circuit shown in fig. 5, optionally, the first initialization transistor T2 is located on the side of the second protrusion portion Ref2 away from the first protrusion portion S22 in the first direction x in the area between two adjacent light emission control signal lines; in the first direction x, the second sub transistor T12 is located between the first sub transistor T11 and the first initialization transistor T2.
Comparing the schematic structural diagram of the display panel in the prior art with fig. 8 of the display panel in this embodiment, the position of the first initialization transistor T2 in the prior art is on the left side of the first protrusion, and the first initialization transistor T2 in this embodiment is located on one side of the second protrusion Ref2 away from the first protrusion S22 (i.e., on the right side of the first protrusion S22 and the second protrusion Ref2 in fig. 8), i.e., compared with the prior art, the second initialization transistor T2 is located on the opposite side of the first protrusion S22, so that the second protrusion Ref2 can have a sufficient setting space, and a relatively large first coupling capacitor is formed more easily.
With continued reference to fig. 2, optionally, the display panel further includes a plurality of block-shaped first electrodes 240 arranged in an array, and the first initialization transistor T2 is located between two adjacent rows of the first electrodes 240 along the first direction x; in the second direction y, the first initialization transistor T2 is located between the first electrodes 240 of two adjacent columns; a first pole of a first initialization transistor T2 located between the first electrode 240 of the ith row and the first electrode 240 of the (i + 1) th row in the first direction x, and between the first electrode 240 of the jth column and the jth +1 th column in the second direction y is electrically connected to the first electrode 240 of the jth column in the ith row, and a second pole is electrically connected to a second initialization transistor connected to the first electrode 240 of the (i + 1) th row and the jth +1 th column; wherein i is more than or equal to 1, and j is more than or equal to 1. Wherein the first electrode 240 may be a light emitting device anode.
Fig. 2 exemplarily shows four incomplete first electrodes 240 respectively located in two adjacent rows and two adjacent columns in the display panel, wherein the four first electrodes 240 are respectively referred to as the first electrode 240 in the first row and the first column, the first electrode 240 in the first row and the second column, the first electrode 240 in the second row and the first column, and the first electrode 240 in the second row and the second column, where the row direction is a first direction x, and the column direction is a second direction y. The first pole of the first initialization transistor T2 is electrically connected to the first electrode 240 at the upper left corner (located in the first row and the first column), the second pole is electrically connected to the second initialization transistor connected to the first electrode 240 at the lower right corner (located in the second row and the second column), while the first pole of the first initialization transistor T2 in the pixel circuit of the display panel shown in fig. 6 in the prior art is electrically connected to the first electrode 240 at the ith row and the jth column, and the second pole is electrically connected to the second initialization transistor connected to the first electrode 240 at the (i + 1) th row and the jth column. Compared with the prior art display panel, the connection mode and the arrangement position of the first initialization transistor T2 in the solution of the present embodiment, so that for a pixel circuit to which the first electrode 240 of the lower left corner (second row and first column) is connected, at the intermediate node position of the first sub-transistor T11 and the second sub-transistor T12 of the first double-gate transistor 121, a space in which the second active portion 212 can be disposed is large, a space in which the second protrusion portion Ref2 of the initialization signal line Ref is disposed is also large, thereby ensuring that the second active portion 212 and the second protrusion portion Ref2 can have a large overlapping area, thereby ensuring that the polar plate of the first coupling capacitor C1 has a larger dead-against area, further ensuring that the capacitance value of the first coupling capacitor C1 is larger, the potential of the middle node of the first double-gate transistor 121 can be kept more stable when being turned off, and the flicker of the display picture is further improved.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A pixel circuit, comprising: the device comprises a driving transistor, a first initialization module and a leakage suppression module; the first initialization module is used for transmitting an initialization signal input by an initialization signal input end to a first pole of the light-emitting device in an initialization stage;
the leakage suppression module is electrically connected with the gate of the driving transistor, the leakage suppression module comprises a first double-gate transistor and a first coupling capacitor, and the middle node of the first double-gate transistor is electrically connected with the initialization signal input end through the first coupling capacitor.
2. The pixel circuit according to claim 1, wherein the first double-gate transistor comprises a first sub-transistor and a second sub-transistor, the first sub-transistor and the second sub-transistor being connected in series through an active layer, wherein a common node of the series connection of the first sub-transistor and the second sub-transistor serves as an intermediate node of the first double-gate transistor.
3. The pixel circuit according to claim 1 or 2, wherein the initialization signal input terminal is electrically connected to an initialization signal line overlapping with an active layer connecting the first sub-transistor and the second sub-transistor in series to form a first coupling capacitance.
4. The pixel circuit according to claim 1 or 2, wherein the first initialization module comprises a first initialization transistor, a gate of the first initialization transistor is electrically connected to a first scan signal input terminal, a first pole of the first initialization transistor is electrically connected to the initialization input terminal, and a second pole of the first initialization transistor is electrically connected to a first pole of the light emitting device;
the first double-gate transistor of the electric leakage suppression module is used as a compensation transistor of the pixel circuit;
the pixel circuit further includes a data writing transistor, a first light emission control transistor, and a second light emission control transistor;
a first pole of the driving transistor is electrically connected to a first power voltage input terminal through the first light emission control transistor, and a second pole of the driving transistor is electrically connected to a first pole of the light emitting device through the second light emission control transistor;
the first grid electrode and the second grid electrode of the compensation transistor are electrically connected with the second scanning signal input end, and the compensation transistor is connected between the grid electrode of the driving transistor and the second pole of the driving transistor;
the gate of the data writing transistor is electrically connected to the second scanning signal input terminal, the first pole of the data writing transistor is electrically connected to the data voltage input terminal, and the second pole of the data writing transistor is electrically connected to the first pole of the driving transistor.
5. The pixel circuit according to claim 4, further comprising a second initialization module comprising a second double-gate transistor, a first gate and a second gate of the second double-gate transistor being electrically connected to a third scan signal input terminal, the second double-gate transistor being connected between the initialization input terminal and the gate of the driving transistor;
the second double-gate transistor includes a third sub-transistor and a fourth sub-transistor, which are connected in series through an active layer; the first power supply voltage input end is electrically connected with a first power supply line, and an active layer between the third sub-transistor and the fourth sub-transistor is overlapped with the first power supply line to form a second coupling capacitor.
6. A display panel comprising the pixel circuit according to any one of claims 1 to 5.
7. The display panel according to claim 6, further comprising a plurality of initialization signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, and a plurality of light-emission control lines extending in a first direction, wherein one of the first scanning signal lines, one of the initialization signal lines, and one of the second scanning signal lines are included in a region between adjacent two of the light-emission control signal lines, and wherein the initialization signal line is located between the first scanning signal line and the second scanning signal line in a second direction in a region between adjacent two of the light-emission control signal lines; the second direction intersects the first direction.
8. The display panel according to claim 7, comprising an active layer, a first metal layer, and a second metal layer, wherein the first scan signal line and the second scan signal line are located in the first metal layer, and the initialization signal line is located in the second metal layer;
the second scan signal line includes a first main body portion extending in the first direction and a plurality of first protrusion portions, the active layer includes a first active portion extending in the first direction and overlapping the first protrusion portions, and a second active portion contiguous with the first active portion and extending in the second direction, the second active portion overlapping the first main body portion;
the first bulge part and the first active part are overlapped to form a first sub transistor, and the first main body part and the second active part are overlapped to form a second sub transistor;
the initialization signal line includes a second main body portion extending in the first direction and a second protrusion portion protruding the main body portion in the second direction, the second active portion overlapping with at least a part of the second protrusion portion; the first protruding part and the second protruding part protrude in opposite directions;
preferably, the second active portion extends to the second body portion along the second direction.
9. The display panel according to claim 8, wherein the first initialization transistor is located on a side of the second projecting portion away from the first projecting portion in the first direction in a region between two adjacent light emission control signal lines;
in the first direction, the second sub-transistor is located between the first sub-transistor and the first initialization transistor.
10. The display panel according to claim 9, further comprising a plurality of block-shaped first electrodes arranged in an array, wherein the first initialization transistor is located between two adjacent rows of the first electrodes along a first direction; in a second direction, the first initialization transistor is positioned between two adjacent columns of the first electrodes;
the first pole of the first initialization transistor, which is positioned between the first electrodes of the ith row and the (i + 1) th row in the first direction, is electrically connected with the first electrode of the jth column in the ith row in the second direction, and the second pole of the first initialization transistor, which is positioned between the first electrodes of the jth column and the (j + 1) th column in the second direction, is electrically connected with the second initialization transistor connected with the first electrodes of the (i + 1) th row and the (j + 1) th column; wherein i is more than or equal to 1, and j is more than or equal to 1.
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| CN202011194234.6A CN112289267A (en) | 2020-10-30 | 2020-10-30 | Pixel circuit and display panel |
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| CN202011194234.6A CN112289267A (en) | 2020-10-30 | 2020-10-30 | Pixel circuit and display panel |
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