CN113992004A

CN113992004A - Dual mode switching frequency control system

Info

Publication number: CN113992004A
Application number: CN202111462723.XA
Authority: CN
Inventors: 薛尚嵘; 冯翰雪; 李冬超
Original assignee: Yishi Semiconductor Shanghai Co ltd
Current assignee: Yishi Semiconductor Shanghai Co ltd
Priority date: 2021-12-02
Filing date: 2021-12-02
Publication date: 2022-01-28
Anticipated expiration: 2041-12-02
Also published as: CN113992004B

Abstract

The invention discloses a dual-mode switching frequency control system, which comprises: an oscillator, a phase detector, and a loop filter. In the RT mode, the oscillator can output a clock signal with a preset frequency; in the PLL mode, the oscillator is capable of outputting a clock signal synchronized with an external clock signal; and under the RT mode and/or the PLL mode, when the oscillator works in the lowest-frequency working state, the clock signal with the lowest frequency can be output. The dual-mode switching frequency control system can realize the mutual switching between the RT mode and the PLL mode, has high phase-locked loop establishing speed, can shorten the establishing time required when the frequency of the clock signal output by the oscillator is synchronized to the frequency of the external clock signal when the two modes are switched, and effectively solves the problem of single-mode control of the switching frequency in a common switching power supply.

Description

Dual mode switching frequency control system

Technical Field

The present invention relates to the field of integrated circuit technology, and more particularly, to a dual mode switching frequency control system.

Background

Switching power supplies, which are high-frequency power conversion devices, are widely used in the field of integrated circuits, and convert a level voltage into a voltage or a current required by a user terminal through different types of architectures. The switching frequency control system in the conventional switching power supply has a single mode and is difficult to meet the requirements of various application scenes.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.

Disclosure of Invention

The invention aims to provide a dual-mode switching frequency control system, which adopts dual modes to control the switching frequency.

To achieve the above object, an embodiment of the present invention provides a dual mode switching frequency control system, including: an oscillator, a phase detector, and a loop filter.

In the RT mode, the oscillator can output a CLOCK signal CLOCK with a preset frequency; in the PLL mode, the oscillator is capable of outputting a CLOCK signal CLOCK synchronized with an external CLOCK signal CLK _ SYNC; and in the RT mode and/or the PLL mode, when the oscillator works in the lowest-frequency working state, the CLOCK signal CLOCK with the lowest frequency can be output.

In the PLL mode, the phase detector is configured to compare the CLOCK signal CLOCK with the external CLOCK signal CLK _ SYNC to generate an error voltage corresponding to a phase difference between the CLOCK signal CLOCK and the external CLOCK signal CLK _ SYNC.

In the PLL mode, the loop filter is used to remove high frequency signals and noise signals in the error voltage and output a control voltage VCONT _ PRE that controls the oscillator, under the control of which the CLOCK signal CLOCK output by the oscillator can be synchronized to the external CLOCK signal CLK _ SYNC.

In one or more embodiments of the present invention, the oscillator includes a mode conversion circuit, a current mirror circuit, a lowest frequency circuit, a frequency maintenance circuit, a ramp voltage generation circuit, a comparator, a logic circuit, and a BUFFER; wherein the mode conversion circuit is used for the RT mode and/or the PLL modeOutputting corresponding current through the current mirror circuit according to the corresponding control voltage; the lowest frequency circuit is used for enabling the oscillator to output a CLOCK signal CLOCK with the lowest frequency; the frequency maintaining circuit is used for maintaining the frequency corresponding to the control voltage VCONT _ PRE in the RT mode; the ramp voltage generating circuit is used for outputting a corresponding ramp voltage V according to the current output by the current mirror circuit_RAMP(ii) a The comparator is used for converting the ramp voltage V_RAMPAnd a reference voltage V_{REF_OSC}After comparison, the CLOCK signal CLOCK is output through the logic circuit and the BUFFER in sequence.

In one or more embodiments of the invention, the lowest frequency circuit includes a PMOS transistor P7, a resistor R3, a capacitor C3, a PMOS transistor P4, and a bias current source IBIAS2_ FMIN;

the drain of the PMOS transistor P7 is grounded through the resistor R3, the gate of the PMOS transistor P7 is grounded through the bias current source IBIAS2_ FMIN and connected to the power supply VDD through the capacitor C3, the gate of the PMOS transistor P7 is simultaneously connected to the drain of the PMOS transistor P4, the source of the PMOS transistor P7 is connected to the gate of the PMOS transistor P4, the current mirror circuit and the frequency maintaining circuit, and the source of the PMOS transistor P4 is connected to the power supply VDD.

In one or more embodiments of the invention, the mode conversion circuit includes a resistor R2, an NMOS transistor N3, a bias current source IBIAS1, an operational amplifier, a switch S3, a switch S4, a switch S5, a switch S6, a resistor R_SETResistance R_PLLNMOS transistor N4;

wherein the positive input end of the operational amplifier is connected with a reference voltage V through a switch S3_REFOne end of the resistor R2 is connected with a power supply VDD, the other end of the resistor R2 is connected with the drain electrode of an NMOS tube N3, the gate electrode of the NMOS tube N3 is connected with a control voltage VCONT _ PRE, the source electrode of the NMOS tube N3 is grounded through a bias current source IBIAS1, the source electrode of the NMOS tube N3 is simultaneously connected with the positive input end of the operational amplifier through a switch S4, and the negative input end of the operational amplifier is connected with the resistor R5 through a switch S5_SETConnection, the resistance R_SETThe other end of the operational amplifier is grounded, and the negative input end of the operational amplifier passes through a switch S6 and a resistor R_PLLConnection, the resistance R_PLLThe other end of the NMOS transistor N4 is grounded, the drain of the NMOS transistor N4 is connected with the current mirror circuit, the grid of the NMOS transistor N4 is connected with the output end of the operational amplifier, and the source of the NMOS transistor N4 is connected with the negative input end of the operational amplifier.

In one or more embodiments of the invention, the current mirror circuit includes a PMOS transistor P3 and a PMOS transistor P6, a source of the PMOS transistor P3 is connected to a power supply VDD, a drain and a gate of the PMOS transistor P3 are shorted and connected to a gate of the PMOS transistor P6, a frequency maintaining circuit, a lowest frequency circuit and a mode converting circuit, a source of the PMOS transistor P6 is connected to the power supply VDD, and a drain of the PMOS transistor P6 is connected to the ramp voltage generating circuit and a positive input terminal of the comparator.

In one or more embodiments of the present invention, the frequency maintaining circuit includes a PMOS transistor P5, an NMOS transistor N5, a resistor R4, and a switch S7, a source of the PMOS transistor P5 is connected to a power VDD, a gate of the PMOS transistor P5 is connected to the current mirror circuit and the lowest frequency circuit, a drain of the PMOS transistor P5 is connected to an output terminal of the loop filter and an input terminal of the oscillator, a drain and a gate of the NMOS transistor N5 are shorted and connected to a drain of the PMOS transistor P5 through the switch S7, a source of the NMOS transistor N5 is grounded through the resistor R4, and the switch S7 is in a closed state in the RT mode.

In one or more embodiments of the invention, the ramp voltage generating circuit includes an NMOS transistor N6 and a capacitor Cosc, the capacitor Cosc has one end connected to the drain of the NMOS transistor N6 and the positive input terminal of the comparator, the other end connected to the source of the NMOS transistor N6 and simultaneously grounded, and the gate of the NMOS transistor N6 is connected to the output terminal of the logic circuit.

In one or more embodiments of the invention, in the RT mode, the frequency f of the CLOCK signal CLOCK₁The expression of (a) is:

f₁＝K*[V_REF/(R_SET*C_OSC*V_{REF_OSC})]；

frequency f of the CLOCK signal CLOCK in PLL mode₂The expression of (a) is:

f₂＝K*[V_CONT/(R_PLL*C_OSC*V_{REF_OSC})]＝f_{CLK_SYNC}；

wherein K is the number ratio of PMOS tubes P6 to P3, V_CONTIs the control voltage at the source of NMOS transistor N3, f_{CLK_SYNC}Is the frequency of the external clock signal CLK _ SYNC.

The invention also discloses a dual-mode switching frequency control system, which comprises: a first phase-locked loop including a phase discriminator, a loop filter, and a first oscillator;

in the PLL mode, the first oscillator is capable of outputting a CLOCK signal CLOCK synchronized with an external CLOCK signal CLK _ SYNC; under the RT mode and/or the PLL mode, when the first oscillator works in the lowest frequency working state, the CLOCK signal CLOCK with the lowest frequency can be output;

a second oscillator capable of forming a second phase-locked loop by switching with the first oscillator;

the second oscillator is capable of outputting a clock signal CLK _ OSC2 synchronized to the external clock signal CLK _ SYNC while the second oscillator provides a control voltage VCONT corresponding to the frequency of the external clock signal CLK _ SYNC; the CLOCK signal CLOCK output by the first oscillator in the PLL mode and exiting from the lowest frequency operating state is enabled by the control voltage VCONT to be synchronized to the external CLOCK signal CLK _ SYNC bypassing the abnormal state.

In another or more embodiments of the present invention, in the RT mode, the first oscillator can output a CLOCK signal CLOCK of a preset frequency.

In another or more embodiments of the present invention, the dual-mode switching frequency control system further includes a first selector and a second selector, an I0 input terminal and an output terminal of the first selector are connected to the first oscillator, an I1 input terminal of the first selector is connected to the second oscillator, an I0 input terminal of the second selector is connected to an output terminal of the first oscillator, an I1 input terminal of the second selector is connected to an output terminal of the second oscillator, and an output terminal of the second selector is connected to an input terminal of the phase detector, and the first selector and the second selector are used to switch between the first oscillator and the second oscillator.

In another or more embodiments of the present invention, the first oscillator includes a mode conversion circuit, a first current mirror circuit, a lowest frequency circuit, a frequency maintenance circuit, a first ramp voltage generation circuit, a first comparator, a first logic circuit, and a BUFFER2, the mode conversion circuit, the first ramp voltage generation circuit, and the first comparator are all connected to the first current mirror circuit, and the first current mirror circuit, the lowest frequency circuit, and the frequency maintenance circuit are all connected to the first selector;

the mode conversion circuit is used for outputting corresponding mirror current through the first current mirror circuit in the RT mode; the lowest frequency circuit is used for enabling the first oscillator to output a CLOCK signal CLOCK with the lowest frequency; the frequency maintaining circuit is used for maintaining the frequency corresponding to the control voltage VCONT in the RT mode; the first ramp voltage generating circuit is used for outputting a corresponding ramp voltage V according to the mirror current output by the first current mirror circuit_RAMP1(ii) a The first comparator is used for converting a ramp voltage V_RAMP1And a reference voltage V_{REF_OSC}The comparison is performed and then the CLOCK signal CLOCK is outputted through the first logic circuit and the BUFFER 2.

In another or more embodiments of the invention, the mode conversion circuit includes an operational amplifier, a switch S3, and a resistor R_SETAnd an NMOS transistor N5;

wherein the positive input end of the operational amplifier is connected with a reference voltage V_REFThe negative electrode input end of the operational amplifier is connected with the resistor R through the switch S3_SETOne end of said resistor R_SETThe other end of the operational amplifier is grounded, the negative electrode input end of the operational amplifier is simultaneously connected with the source electrode of the NMOS tube N5, the grid electrode of the NMOS tube N5 is connected with the output end of the operational amplifier, the drain electrode of the NMOS tube N5 is connected with the first current mirror circuit, and the switch S3 is in a closed state in the RT mode.

In another embodiment or a plurality of embodiments of the invention, the first current mirror circuit includes a PMOS transistor P5 and a PMOS transistor P8, the source of the PMOS transistor P5 is connected to the VDD, the drain and the gate of the PMOS transistor P5 are shorted and connected to the mode converting circuit and the I0 input terminal of the first selector, the gate of the PMOS transistor P8 is connected to the output terminal of the first selector, the source of the PMOS transistor P8 is connected to the VDD, and the drain of the PMOS transistor P8 is connected to the positive input terminal of the first comparator.

In another or more embodiments of the invention, the lowest frequency circuit includes a PMOS transistor P9, a resistor R3, a capacitor C3, a PMOS transistor P6, and a bias current source IBIAS2_ FMIN;

the drain of the PMOS transistor P9 is grounded through the resistor R3, the gate of the PMOS transistor P9 is grounded through the bias current source IBIAS2_ FMIN and is connected to the power supply VDD through the capacitor C3, the source of the PMOS transistor P9 is connected to the I0 input terminal of the first selector, the gate of the PMOS transistor P9 is connected to the drain of the PMOS transistor P6, the gate of the PMOS transistor P6 is connected to the I0 input terminal of the first selector, and the source of the PMOS transistor P6 is connected to the power supply VDD.

In another or more embodiments of the present invention, the frequency maintaining circuit includes a PMOS transistor P7, a switch S4, an NMOS transistor N6, and a resistor R4;

the source electrode of the PMOS tube P7 is connected with a power supply VDD, the grid electrode of the PMOS tube P7 is connected with the I0 input end of the first selector, the drain electrode of the PMOS tube P7 is connected with one end of the switch S4 and the output end of the loop filter, the drain electrode and the grid electrode of the NMOS tube N6 are in short circuit and are connected with the other end of the switch S4, the source electrode of the NMOS tube N6 is grounded through the resistor R4, and the switch S4 is in a closed state in the RT mode.

In one or more embodiments of the present invention, the first ramp voltage generating circuit includes an NMOS transistor N7 and a capacitor C_OSC1Said capacitor C_OSC1One end of the first comparator is connected with the drain electrode of the NMOS tube N7 and the positive electrode input end of the first comparator, the other end of the first comparator is connected with the source electrode of the NMOS tube N7 and is grounded simultaneously, and the grid electrode of the NMOS tube N7 is connected with a first logicAn output terminal of the circuit.

In one or more embodiments of the present invention, the second oscillator includes an NMOS transistor N3, a resistor R2, a PMOS transistor P3, a PMOS transistor P4, an NMOS transistor N4, and a capacitor C_OSC2A second comparator, a second logic circuit and a BUFFER 3;

wherein, the gate of NMOS pipe N3 is connected the output of loop filter, the source of NMOS pipe N3 is passed through resistance R2 ground connection, the source of NMOS pipe N3 is connected the I1 input of first selector, the drain and the gate short circuit of PMOS pipe P3 and connect the drain of NMOS pipe N3 and the gate of PMOS pipe P4, the source of PMOS pipe P3 is connected power VDD, the source of PMOS pipe P4 is connected power VDD, the drain of PMOS pipe P4 is connected the positive input of second comparator, electric capacity C is connected_OSC2One end of the second comparator is connected with the drain electrode of the NMOS tube N4 and the positive input end of the second comparator, and the capacitor C_OSC2The other end of the first comparator is connected with the source electrode of the NMOS tube N4 and is grounded, the grid electrode of the NMOS tube N4 is connected with the output end of the second logic circuit, and the negative electrode input end of the second comparator is connected with a reference voltage V_{REF_OSC}The output terminal of the second comparator is connected to the input terminal of the BUFFER3 through the second logic circuit, and the output terminal of the BUFFER3 is connected to the I1 input terminal of the second selector.

Compared with the prior art, the dual-mode switching frequency control system and the improved control system can realize the mutual switching between the RT mode and the PLL mode, the phase-locked loop is high in establishing speed, the establishing time required when the frequency of the CLOCK signal CLOCK output by the oscillator is synchronized to the frequency of the external CLOCK signal CLK _ SYNC during the switching between the two modes can be shortened, and the problem of single-mode control of the switching frequency in a common switching power supply is effectively solved.

Drawings

FIG. 1 is a circuit schematic of a dual mode switching frequency control system according to one embodiment of the present invention;

fig. 2 is a circuit schematic of a phase detector according to an embodiment of the present invention;

FIG. 3 is a circuit schematic of a loop filter according to an embodiment of the present invention;

FIG. 4 is a circuit schematic of an oscillator according to an embodiment of the present invention;

FIG. 5 is a circuit timing diagram of a dual mode switching frequency control system according to one embodiment of the present invention;

FIG. 6 is a circuit schematic of a dual mode switching frequency control system according to another embodiment of the present invention;

fig. 7 is a circuit schematic of a phase detector and a second selector according to another embodiment of the present invention;

FIG. 8 is a circuit schematic of a loop filter according to another embodiment of the present invention;

FIG. 9 is a circuit schematic of a first oscillator according to another embodiment of the present invention;

FIG. 10 is a circuit schematic of a second oscillator according to another embodiment of the present invention;

fig. 11 is a circuit timing diagram of a dual mode switching frequency control system according to another embodiment of the present invention.

Detailed Description

The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.

Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.

Example 1

As shown in fig. 1, a dual mode switching frequency control system includes: enable circuit 10, mode decision circuit 20, phase detector 30, loop filter 40, and oscillator 50.

The enable circuit 10 outputs an enable signal EN, which is an enable signal of the entire switching frequency control system, according to an input signal EN _ CK. The input signal EN _ CK is equal to the enable signal EN, and when both are "1", the entire switching frequency control system operates normally, and when the enable signal EN is "0", the entire switching frequency control system does not operate, so that the following analysis assumes that the enable signal EN is "1". The input signal FORCE _ FMIN is used to indicate whether the system is operating at the lowest frequency and simultaneously output the enable signal EN1 through the enable circuit 10, when the input signal FORCE _ FMIN is "1", the enable signal EN1 is set to "0", and the surface system is operating at the lowest frequency.

MODE decision circuit 20 has an RT/SYNC terminal for deciding whether oscillator 50 is operating in RT MODE and/or PLL MODE, and MODE decision circuit 20 is capable of outputting an external clock signal CLK _ SYNC, a control signal RT _ MODE for switching oscillator 50 to RT MODE, and a control signal PLL _ MODE for switching oscillator 50 to PLL MODE. The mode determination circuit 20 is controlled by an enable signal EN.

In this embodiment, when only resistor R is connected between RT/SYNC terminal and ground_SETResistance R_SETIf the input signal FORCE _ FMIN is "0", the operating frequency of the oscillator 50 is determined by the resistor R, and the MODE decision circuit 20 outputs the control signal RT _ MODE as "1" and the control signal PLL _ MODE as "0", and the oscillator 50 operates in the RT MODE_SETDetermining the value of (c); when the external CLOCK signal CLK _ SYNC is directly connected to the RT/SYNC terminal, the MODE decision circuit outputs a control signal PLL _ MODE of "1" and a control signal RT _ MODE of "0", at this time, the oscillator 50 operates in the PLL MODE, and if the input signal FORCE _ FMIN is "0", the frequency of the CLOCK signal CLOCK output by the oscillator 50 is synchronized to the frequency of the external CLOCK signal CLK _ SYNC through the phase detector 30 and the loop filter 40; if both are present, the PLL MODE overrides the RT MODE by automatic detection, the MODE decision circuit 20 outputs the control signal PLL _ MODE to "1" and the control signal RT _ MODE to "0", and the oscillator 50 operates in the PLL MODE.

In this embodiment, the phase detector 30 is a phase comparison module, and the phase detector 30 can compare the CLOCK signal CLOCK with the external CLOCK signal CLK _ SYNC to generate an error voltage corresponding to a phase difference between the CLOCK signal CLOCK and the external CLOCK signal CLK _ SYNC.

As shown in fig. 2, the phase detector 30 includes a D flip-flop D1, a D flip-flop D2, an AND gate AND1, an inverter INV1, a PMOS transistor P1, a PMOS transistor P2, an NMOS transistor N1, an NMOS transistor N2, a switch S1, a switch S2, AND a unity gain amplifier a 1.

Specifically, an input CK terminal of the D flip-flop D1 is connected to the mode decision circuit 20 to receive the external clock signal CLK _ SYNC, and an input D terminal of the D flip-flop D1 is connected to the power supply VDD. An input CK terminal of the D flip-flop D2 is connected to the output terminal of the oscillator 50 to receive the CLOCK signal CLOCK output from the oscillator 50, and an input D terminal of the D flip-flop D2 is connected to the power supply VDD. The output Q terminal of the D flip-flop D1 is connected to the a1 input terminal of the AND gate AND1, AND the output Q terminal of the D flip-flop D2 is connected to the a2 input terminal of the AND gate AND 1. An output end of the AND gate AND1 is connected to an input end of the inverter INV1, AND an output end of the inverter INV1 is connected to R reset ends of the D flip-flop D1 AND the D flip-flop D2. The output QN terminal of the D-flip-flop D1 is connected to the gate of the PMOS transistor P2, and the output Q terminal of the D-flip-flop D2 is connected to the gate of the NMOS transistor N1. The source of the PMOS transistor P2 is connected with the drain of the PMOS transistor P1, the source of the PMOS transistor P1 is connected with the power supply VDD, and the gate of the PMOS transistor P1 is connected with the bias voltage VB 1. The source of the NMOS transistor N1 is connected to the drain of the NMOS transistor N2, the source of the NMOS transistor N2 is grounded, and the gate of the NMOS transistor N2 is connected to a bias voltage VB 2. The source of the PMOS transistor P2 is connected to one end of the switch S1, the drain of the NMOS transistor N2 is connected to one end of the switch S2, and the other end of the switch S1 is connected to the other end of the switch S2 and to the output of the unity gain amplifier A1. The drain of the NMOS transistor N1 is connected to the drain of the PMOS transistor P2 and to the input of the unity gain amplifier a1 and the loop filter 40, thereby outputting an error voltage corresponding to the phase difference between the CLOCK signal CLOCK and the external CLOCK signal CLK _ SYNC to the loop filter 40.

In this embodiment, the loop filter 40 is configured to remove the high frequency signal and the noise signal in the error voltage and output the control voltage VCONT _ PRE for controlling the oscillator 50, so as to satisfy the performance required by the loop in the PLL mode by removing the high frequency signal and the noise signal in the error voltage, thereby increasing the stability of the system.

As shown in fig. 3, the loop filter 40 includes a resistor R1, a capacitor C1, and a capacitor C2. Specifically, one end of the capacitor C1 and one end of the capacitor C2 are both grounded, the other end of the capacitor C1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the other end of the capacitor C2 and is connected to the output terminal of the phase detector 30 to receive the error voltage, and is also connected to the input terminal of the oscillator 50 to output the control voltage VCONT _ PRE to the oscillator 50.

In this embodiment, the oscillator 50 can operate in an RT mode and/or a PLL mode, the RT mode and the PLL mode can be switched to each other, and a switching frequency of the switching power supply can be generated in the RT mode or the PLL mode.

As shown in fig. 4, the oscillator 50 includes a mode conversion circuit 51, a current mirror circuit 52, a lowest frequency circuit 53, a frequency maintenance circuit 54, a ramp voltage generation circuit 55, a comparator, a logic circuit, and a BUFFER.

The mode switching circuit 51 is configured to output a corresponding current through the current mirror circuit 52 according to a corresponding control voltage in the RT mode and/or the PLL mode.

As shown in FIG. 4, the mode switching circuit 51 includes a resistor R2, an NMOS transistor N3, a bias current source IBIAS1, an operational amplifier, a switch S3, a switch S4, a switch S5, a switch S6, a resistor R_SETResistance R_PLLAnd an NMOS transistor N4.

Specifically, the positive input terminal of the operational amplifier is connected to a reference voltage V through a switch S3_REF. One end of the resistor R2 is connected to the power supply VDD, the other end is connected to the drain of the NMOS transistor N3, the gate of the NMOS transistor N3 is connected to the control voltage VCONT _ PRE, and the source of the NMOS transistor N3 is grounded through the bias current source IBIAS 1. The source of the NMOS transistor N3 is connected to the positive input terminal of the operational amplifier through the switch S4. The negative input end of the operational amplifier passes through the switch S5 and the resistor R_SETConnection, resistance R_SETAnd the other end of the same is grounded. The negative input end of the operational amplifier passes through the switch S6 and the resistor R_PLLConnection, resistance R_PLLAnd the other end of the same is grounded. The drain of the NMOS transistor N4 is connected with the current mirror circuit 52, the gate of the NMOS transistor N4 is connected with the output end of the operational amplifier, and the source of the NMOS transistor N4 is connected with the negative input end of the operational amplifier.

In this embodiment, the operational amplifier is controlled by the enable signal EN1, and when the input signal FORCE _ FMIN is "1", the enable signal EN1 is set to "0", at which time the operational amplifier is turned off, and the oscillator 50 operates at the lowest frequency.

In the RT mode, the switches S3 and S5 are in a closed state, and the switches S4 and S6 are in an open state. The switch S3 and the switch S5 are both controlled by the control signal RT _ MODE, the control signal RT _ MODE is "1", and when the control signal PLL _ MODE is "0", the switch S3 and the switch S5 are both closed, so that the MODE switching circuit 51 enters the RT MODE.

In the PLL mode, the switch S4 and the switch S6 are in a closed state, and the switch S3 and the switch S5 are in an open state. The switch S4 and the switch S6 are both controlled by the control signal PLL _ MODE, which is "1", and the control signal RT _ MODE is "0", and both the switch S4 and the switch S6 are closed, so that the MODE conversion circuit 51 enters the PLL MODE. At this time, the source of the NMOS transistor N3 outputs the control voltage VCONT to the positive input terminal of the operational amplifier.

As shown in fig. 4, the current mirror circuit 52 includes a PMOS transistor P3 and a PMOS transistor P6. The source of the PMOS transistor P3 is connected to the power VDD, the drain and gate of the PMOS transistor P3 are shorted, and the gate of the PMOS transistor P6, the frequency maintaining circuit 54, the lowest frequency circuit 54 and the mode converting circuit 51 are connected, specifically, the drain and gate of the PMOS transistor P3 are shorted and then connected to the drain of the NMOS transistor N4. The source of the PMOS transistor P6 is connected to the power supply VDD, and the drain of the PMOS transistor P6 is connected to the ramp voltage generation circuit 55 and the positive input terminal of the comparator.

In this embodiment, the lowest frequency circuit 53 is used to cause the oscillator 50 to output the CLOCK signal CLOCK of the lowest frequency. When the operational amplifier is turned off, the oscillator 50 is adjusted to operate at the lowest frequency by the lowest frequency circuit 53.

As shown in fig. 4, the lowest frequency circuit 53 includes a PMOS transistor P7, a resistor R3, a capacitor C3, a PMOS transistor P4, and a bias current source IBIAS2_ FMIN.

The drain of the PMOS transistor P7 is grounded through a resistor R3, the gate of the PMOS transistor P7 is grounded through a bias current source IBIAS2_ FMIN and is connected to a power supply VDD through a capacitor C3, the gate of the PMOS transistor P7 is simultaneously connected to the drain of the PMOS transistor P4, the source of the PMOS transistor P7 is connected to the gate of the PMOS transistor P4, the current mirror circuit 52 and the frequency maintaining circuit 54, specifically, the source of the PMOS transistor P7 is simultaneously connected to the drain and the gate short-circuit terminal of the PMOS transistor P3, and the source of the PMOS transistor P4 is connected to the power supply VDD.

In the embodiment, in the RT mode, the frequency maintaining circuit 54 is used for maintaining the frequency corresponding to the control voltage VCONT _ PRE.

As shown in fig. 4 and fig. 1, the frequency maintaining circuit 54 includes a PMOS transistor P5, an NMOS transistor N5, a resistor R4, and a switch S7. The source of the PMOS transistor P5 is connected to the power VDD, the gate of the PMOS transistor P5 is connected to the current mirror circuit 52, and specifically, the gate of the PMOS transistor P5 is connected to the drain and the gate short terminal of the PMOS transistor P3. The drain of the PMOS transistor P5 is connected to the output terminal of the loop filter 40 and the input terminal of the oscillator 50, and specifically, the drain of the PMOS transistor P5 is connected to the drain of the PMOS transistor P2, the drain of the NMOS transistor N1, the gate of the NMOS transistor N3, the resistor R1, and the capacitor C2. The drain and the gate of the NMOS transistor N5 are shorted and connected to the drain of the PMOS transistor P5 through the switch S7, and the source of the NMOS transistor N5 is grounded through the resistor R4.

In the RT mode, the switch S7 is in a closed state. The switch S7 is controlled by the control signal RT _ MODE, and when the control signal RT _ MODE is "1", the switch S7 is closed, so that the frequency maintaining circuit 54 enters the RT MODE. At this time, the control voltage VCONT _ PRE at the input of oscillator 50 is at the same voltage as the voltage at the drain of PMOS transistor P5. Finally, it is ensured that the control voltage VCONT outputted at the source of the NMOS transistor N3 is maintained at the corresponding frequency. Therefore, when the oscillator 50 is switched from the RT mode to the PLL mode, the control voltage VCONT does not need to be gradually increased from "0", the establishment of the phase-locked loop is accelerated, and the establishment time required for synchronizing the frequency of the CLOCK signal CLOCK output by the oscillator 50 to the frequency of the external CLOCK signal CLK _ SYNC when the oscillator 50 is switched between the two modes is shortened.

In this embodiment, the ramp voltage generating circuit 55 is used for outputting the corresponding ramp voltage V according to the current outputted by the current mirror circuit 52_RAMP。

As shown in fig. 4, the ramp voltage generating circuit 55 includes an NMOS transistor N6 and a capacitor Cosc. One end of the capacitor Cosc is connected with the drain of the NMOS transistor N6 and the positive input end of the comparator, the other end of the capacitor Cosc is connected with the source of the NMOS transistor N6 and is grounded, and the gate of the NMOS transistor N6 is connected with the output end of the logic circuit.

As shown in FIG. 4, the comparator is used to ramp the voltage V_RAMPAnd a reference voltage V_{REF_OSC}After comparison, the CLOCK signal CLOCK is output through the logic circuit and the BUFFER BUFFER, the output end of the comparator is connected with the input end of the logic circuit, and the output end of the logic circuit is connected with the input end of the BUFFER BUFFER.

When oscillator 50 operates in the RT MODE, control signal RT _ MODE is "1", and the positive input terminal of the operational amplifier is connected to reference voltage V_REF. According to the characteristic of the operational amplifier, the voltage at the positive input end of the operational amplifier is equal to the voltage at the negative input end, so that the voltage is applied to the resistor R_SETThe voltage across is equal to the reference voltage V_REF. Thereby obtaining a flow resistance R_SETCurrent of equal to V_REF/R_SETThe current is equal to the current flowing through the NMOS transistor N4 and the current flowing through the PMOS transistor P3, which is mirrored by the current mirror circuit 52 so that the current flowing through the PMOS transistor P6 is equal to K (V)_REF/R_SET) Wherein, the proportionality coefficient K is the number ratio of the PMOS pipe P6 and the PMOS pipe P3. Current flowing through PMOS pipe P6 to capacitor C_OSCThe charging is performed to obtain a linearly increasing ramp voltage, and the reset signal RST generated by the logic circuit is used for charging the capacitor C in each period_OSCThe voltage at both ends is discharged, so as to obtain a slope voltage V_RAMP。V_RAMPVoltage and reference voltage V_{REF_OSC}The signal obtained by comparison outputs a CLOCK signal CLOCK through a logic circuit and a BUFFER BUFFER. Frequency f of the CLOCK signal CLOCK₁Is expressed as f₁＝K*[V_REF/(R_SET*C_OSC*V_{REF_OSC})]Wherein, K is the number ratio of the PMOS pipe P6 and the PMOS pipe P3.

When the oscillator 50 operates in the PLL MODE, the control signal PLL _ MODE is "1", and the positive input terminal of the operational amplifier is connected to the source of the NMOS transistor N3, thereby receiving the control voltage VCONT. According to the characteristics of the operational amplifier, the voltage of the positive input terminal of the operational amplifier is equal to that of the negative input terminal, so that the voltage is added to the resistor R_PLLThe voltage across is equal to the control voltage VCONT. Similarly, the frequency f of the CLOCK signal CLOCK output by the oscillator 50 at this time₂Can expressIs f₂＝K*[V_CONT/(R_PLL*C_OSC*V_{REF_OSC})]＝f_{CLK_SYNC}Wherein K is the number ratio of PMOS tubes P6 to P3, V_CONTTo control the voltage VCONT, f_{CLK_SYNC}Is the frequency of the external clock signal CLK _ SYNC. The CLOCK signal CLOCK is fed back to the input CK terminal of D flip-flop D2 in phase detector 30. At this time, the phase-locked loop circuit composed of the phase detector 30, the loop filter 40 and the oscillator 50 will convert the frequency f of the CLOCK signal CLOCK₂Gradually synchronising to the frequency f of the external clock signal CLK _ SYNC_{CLK_SYNC}Therefore, there is the frequency f of the CLOCK signal CLOCK₂Equal to the frequency f of the external clock signal CLK _ SYNC_{CLK_SYNC}. As can be seen from the above expression, the frequency f of the external clock signal CLK _ SYNC_{CLK_SYNC}At different times, the corresponding control voltage VCONT is obtained by loop regulation.

As shown in fig. 5, which characterizes the timing diagram of the switching frequency control system powering up in RT mode and PLL mode, the input signal EN _ CK and the enable signal EN are both "1".

It can be seen that if the system is powered on in the RT MODE, the control signal RT _ MODE is "1" and the control signal PLL _ MODE is "0". When the input signal FORCE _ FMIN is "1", the enable signal EN1 is "0", the system operates at the lowest frequency, and the voltage value of the control voltage VCONT is established and maintained at the voltage value corresponding to the lowest frequency; then, when the input signal FORCE _ FMIN is "0", the enable signal EN1 becomes "1", and the system switches to the resistor R_SETAnd the control voltage VCONT is established and maintained at the corresponding frequency.

If the system is powered on in the PLL MODE, the control signal RT _ MODE is "0" and the control signal PLL _ MODE is "1". When the input signal FORCE _ FMIN is "1", the enable signal EN1 is "0", and the system operates in the lowest frequency operating state; the FORCE _ FMIN signal is then "0" and the enable signal EN1 goes to "1", the system will behave abnormally upon just exiting the lowest frequency operating state. That is, in the PLL mode of fig. 5, when the input signal FORCE _ FMIN changes from "1" to "0", the frequency of the CLOCK signal CLOCK is higher than the frequency of the external CLOCK signal CLK _ SYNC at the beginning, and then gradually decreases and synchronizes to the frequency of the external CLOCK signal CLK _ SYNC. The reason for this is that, in the PLL mode, since the input signal FORCE _ FMIN is "1" at the beginning, the frequency of the CLOCK signal CLOCK output by the oscillator 50 is equal to the minimum frequency. Since the CLOCK signal CLOCK of this frequency is lower than the frequency of the external CLOCK signal CLK _ SYNC at this time, when it is fed back to one end of the phase detector 30 in the phase locked loop, that is, the input CK end of the D flip-flop D2 of the phase detector 30 in fig. 1, the adjustment by the loop filter 40 will cause the value of the control voltage VCONT to be continuously charged high, so that when the lowest frequency operating state is exited, since the voltage value of the control voltage VCONT is very high, the system will operate at a high frequency determined by the voltage value of the control voltage VCONT, and then gradually decrease and synchronize to the frequency of the external CLOCK signal by the adjustment of the phase locked loop.

Example 2

In order to solve the problem in embodiment 1 that the system may generate abnormal behavior when just exiting from the lowest frequency operating state, as shown in fig. 6, this embodiment provides another dual-mode switching frequency control system, including: a first phase-locked loop and a second phase-locked loop. The first phase locked loop includes a phase detector 100, a loop filter 200, and a first oscillator 300; the second oscillator 400 and the first oscillator 300 can form a second phase-locked loop by switching, that is, the phase detector 100 and the loop filter 200 are shared by the first phase-locked loop and the second phase-locked loop.

The dual mode switching frequency control system further comprises a first selector having an I0 input and an output connected to the first oscillator 300, and a second selector having an I1 input connected to the second oscillator 400. The I0 input of the first selector receives the PG signal and the output of the first selector outputs the PGATE signal. The switching between the first oscillator 300 and the second oscillator 400 can be achieved by the first selector and the second selector, with the input of the I0 of the second selector being connected to the output of the first oscillator 300 to receive the CLOCK signal CLOCK, the input of the I1 of the second selector being connected to the output of the second oscillator 400 to receive the CLOCK signal CLK _ OSC2, and the output of the second selector being connected to the input of the phase detector 100 to output the signal CLK _ IN to the phase detector 100.

In this embodiment, the RT mode and the PLL mode are two operation modes that can be switched to each other. The lowest frequency working state is the working state corresponding to the system when just powered on for counting.

In the RT mode and/or the PLL mode, and the first oscillator 300 operates in the lowest frequency operating state, the CLOCK signal CLOCK of the lowest frequency can be output. I.e., whether powered on in RT mode or PLL mode, the first oscillator 300 outputs only the CLOCK signal CLOCK of the lowest frequency.

In the present embodiment, when the first oscillator 300 operates in the lowest frequency operating state, the second oscillator 400 outputs the clock signal CLK _ OSC2 synchronized with the external clock signal CLK _ SYNC, and the second oscillator 400 provides a control voltage VCONT corresponding to the frequency of the external clock signal CLK _ SYNC; the CLOCK signal CLOCK output by the first oscillator 300 in the PLL mode and exiting from the lowest frequency operating state can be synchronized to the external CLOCK signal CLK _ SYNC by skipping the abnormal state by the control voltage VCONT.

After the system is started, in the RT mode, the first oscillator 300 can output a CLOCK signal CLOCK with a preset frequency. In the PLL mode, the first oscillator 300 can output a CLOCK signal CLOCK synchronized with the external CLOCK signal CLK _ SYNC.

As shown in fig. 6, the dual mode switching frequency control system further includes a mode decision circuit and an enable circuit. The MODE decision circuit has an RT/SYNC input terminal, an EN input terminal, a CLK _ SYNC output terminal, an RT _ MODE output terminal and a PLL _ MODE output terminal. The enable circuit has an EN _ CK input, a FORCE _ FMIN input, a LOCK _ OSC1 input, an EN output, an EN1 output, and an EN2 output. The EN output end of the enabling circuit is connected with the EN input end of the mode judging circuit. The enable circuit receives an input signal FORCE _ FMIN through a FORCE _ FMIN input terminal, and the input signal FORCE _ FMIN is used for indicating whether the system works in a lowest frequency output mode or not.

The enable circuit receives an input signal EN _ CK according to an EN _ CK input end and outputs an enable signal EN according to an EN output end. The enable circuit receives an input signal FORCE _ FMIN through a FORCE _ FMIN input terminal and outputs an enable signal EN1 according to an EN1 output terminal and an enable signal EN2 according to an EN2 output terminal. The enable signal EN is equal to the input signal EN _ CK, the enable signal EN is used to control the operating state of the switching frequency control system, and when the enable signal EN is "1", the switching frequency control system operates normally, and the analysis in the present embodiment assumes that the enable signal EN is "1". The enable signal EN1 and the enable signal EN2 respectively correspond to the operating states of the partial circuits in the control improved switching frequency control system, when the enable signal EN1 and the enable signal EN2 are "0", the corresponding partial circuits do not operate, and when the enable signal EN1 and the enable signal EN2 are "1", the corresponding partial circuits operate.

The MODE decision circuit determines the operation MODE of each oscillator by the state of the RT/SYNC input terminal, and outputs the external clock signal CLK _ SYNC through the CLK _ SYNC output terminal, the control signal RT _ MODE for switching the first oscillator 300 to the RT MODE through the RT _ MODE output terminal, and the control signal PLL _ MODE for switching the first oscillator 300 to the PLL MODE through the PLL _ MODE output terminal.

In this embodiment, when the RT/SYNC input terminal is connected to ground only with the resistor R_SETResistance R_SETIf the resistor is external, the MODE determination circuit outputs a control signal RT _ MODE of "1" and a control signal PLL _ MODE of "0", and at this time, the first oscillator 300 operates in the RT MODE; if the input signal FORCE _ FMIN is "0", the frequency of the CLOCK signal CLOCK outputted from the first oscillator 300 is controlled by the resistor R_SETThe value of (c) is determined. When the external clock signal CLK _ SYNC is directly connected to the RT/SYNC terminal, the MODE decision circuit outputs a control signal PLL _ MODE of "1" and a control signal RT _ MODE of "0"; at this time, the first oscillator 300 operates in the PLL mode; also, if the input signal FORCE _ FMIN is "0", the CLOCK signal CLOCK output from the first oscillator 300 is synchronized to the external CLOCK signal CLK _ SYNC through the first phase-locked loop; if both exist, the PLL MODE overrides the RT MODE by automatic detection, the MODE decision circuit outputs the control signal PLL _ MODE as "1" and the control signal RT _ MODE as "0", and the first oscillator 300 operates in the PLL MODEUnder the formula.

As shown in fig. 7, the phase detector 100 is a phase comparison module, AND the phase detector 100 includes a D flip-flop D1, a D flip-flop D2, an AND gate AND1, an inverter INV3, a PMOS transistor P1, a PMOS transistor P2, an NMOS transistor N1, an NMOS transistor N2, a switch S1, a switch S2, AND a unity gain amplifier a 1.

Specifically, an input CK terminal of the D flip-flop D1 is connected to the CLK _ SYNC output terminal of the mode decision circuit 20 to receive the external clock signal CLK _ SYNC, and an input D terminal of the D flip-flop D1 is connected to the power supply VDD. An input CK terminal of the D flip-flop D2 is connected to an output terminal of the second selector to receive the signal CLK _ IN, and an input D terminal of the D flip-flop D2 is connected to the power supply VDD. The output Q terminal of the D flip-flop D1 is connected to the a1 input terminal of the AND gate AND1, AND the output Q terminal of the D flip-flop D2 is connected to the a2 input terminal of the AND gate AND 1. An output end of the AND gate AND1 is connected to an input end of the inverter INV3, AND an output end of the inverter INV3 is connected to R reset ends of the D flip-flop D1 AND the D flip-flop D2. The output QN terminal of the D-flip-flop D1 is connected to the gate of the PMOS transistor P2, and the output Q terminal of the D-flip-flop D2 is connected to the gate of the NMOS transistor N1. The source of the PMOS transistor P2 is connected with the drain of the PMOS transistor P1, the source of the PMOS transistor P1 is connected with the power supply VDD, and the gate of the PMOS transistor P1 is connected with the bias voltage VB 1. The source of the NMOS transistor N1 is connected to the drain of the NMOS transistor N2, the source of the NMOS transistor N2 is grounded, and the gate of the NMOS transistor N2 is connected to a bias voltage VB 2. The source of the PMOS transistor P2 is connected to one end of the switch S1, the drain of the NMOS transistor N2 is connected to one end of the switch S2, and the other end of the switch S1 is connected to the other end of the switch S2 and to the output of the unity gain amplifier A1. The drain of the NMOS transistor N1 is connected to the drain of the PMOS transistor P2 and to the input of the unity gain amplifier a1 and the loop filter 200, thereby outputting an error voltage corresponding to the phase difference between the CLOCK signal CLOCK or the CLOCK signal CLK _ OSC2 and the external CLOCK signal CLK _ SYNC, respectively, to the loop filter 200.

The phase detector 100 can compare the CLOCK signal CLOCK output from the first oscillator 300 with the external CLOCK signal CLK _ SYNC in the PLL mode to generate an error voltage corresponding to a phase difference between the CLOCK signal CLOCK and the external CLOCK signal CLK _ SYNC. Meanwhile, the phase detector 100 can compare the clock signal CLK _ OSC2 output from the second oscillator 400 with the external clock signal CLK _ SYNC to generate an error voltage corresponding to the phase difference between the clock signal CLK _ OSC2 and the external clock signal CLK _ SYNC.

As shown in fig. 8, the loop filter 200 is used to remove the high frequency signal and the noise signal in the error voltage and output the control voltage VCONT _ PRE that controls the first oscillator 300 or the second oscillator 400, thereby increasing the stability of the system by removing the high frequency signal and the noise signal in the error voltage to satisfy the performance required for each phase locked loop in the PLL mode.

Specifically, the loop filter 200 includes a resistor R1, a capacitor C1, and a capacitor C2. Specifically, one end of the capacitor C1 and one end of the capacitor C2 are both grounded, the other end of the capacitor C1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the other end of the capacitor C2 and is connected to the drain of the PMOS transistor P2 and the drain of the NMOS transistor N1 to receive the error voltage, and the second oscillator 400 is also connected to output the control voltage VCONT _ PRE.

As shown in fig. 9, the first oscillator 300 can operate in an RT mode and/or a PLL mode, which can be switched to each other, and can generate a switching frequency of the switching power supply in the RT mode and/or the PLL mode.

Specifically, the first oscillator 300 includes a mode conversion circuit 310, a first current mirror circuit 320, a lowest frequency circuit 330, a frequency maintenance circuit 340, a first ramp voltage generation circuit 350, a first comparator, a first logic circuit, and a BUFFER 2. The mode conversion circuit 310, the first ramp voltage generation circuit 350 and the first comparator are all connected to the first current mirror circuit 320, and the first current mirror circuit 320, the lowest frequency circuit 330 and the frequency maintenance circuit 340 are all connected to the first selector.

As shown in fig. 9, the mode conversion circuit 310 is used to output a corresponding mirror current through the first current mirror circuit 320 in the RT mode.

Specifically, the mode converting circuit 310 includes an operational amplifier, a switch S3, and a resistor R_SETAnd an NMOS transistor N5;

wherein the positive input end of the operational amplifier is connected with a reference voltage V_REFThe negative input end of the operational amplifier is connected with a resistor R through a switch S3_SETOne terminal of (1), resistance R_SETIn addition toOne end of the operational amplifier is grounded, the negative electrode input end of the operational amplifier is simultaneously connected with the source electrode of an NMOS tube N5, the grid electrode of an NMOS tube N5 is connected with the output end of the operational amplifier, the drain electrode of an NMOS tube N5 is connected with the first current mirror circuit 320, the operational amplifier is controlled by an enable signal EN1, and when the enable signal EN1 is '1', the operational amplifier works normally; when the enable signal EN1 is "0" and EN is "1", this is equivalent to the system being powered on and the operational amplifier is not working. In the RT mode, the switch S3 is in a closed state. When the switch S3 is controlled by the control signal RT _ MODE, the control signal RT _ MODE is "1" and the control signal PLL _ MODE is "0", the switch S3 is closed, so that the MODE switching circuit 310 enters the RT MODE. When the control signal RT _ MODE is "0" and the control signal PLL _ MODE is "1", the switch S3 is turned off.

As shown in fig. 9, the first current mirror circuit 320 includes a PMOS transistor P5 and a PMOS transistor P8. The source of the PMOS transistor P5 is connected to the power VDD, the drain and gate of the PMOS transistor P5 are shorted and connected to the mode converting circuit 310 and the I0 input terminal of the first selector, and specifically, the drain and gate of the PMOS transistor P5 are shorted and connected to the drain of the NMOS transistor N5. The grid electrode of the PMOS pipe P8 is connected with the output end of the first selector, the source electrode of the PMOS pipe P8 is connected with the power supply VDD, and the drain electrode of the PMOS pipe P8 is connected with the positive electrode input end of the first comparator.

As shown in fig. 9, the lowest frequency circuit 330 is used to enable the first oscillator to output the lowest frequency CLOCK signal CLOCK.

Specifically, the lowest frequency circuit 330 includes a PMOS transistor P9, a resistor R3, a capacitor C3, a PMOS transistor P6, and a bias current source IBIAS2_ FMIN.

The drain of the PMOS transistor P9 is grounded through a resistor R3, the gate of the PMOS transistor P9 is grounded through a bias current source IBIAS2_ FMIN and connected to the power supply VDD through a capacitor C3, and the source of the PMOS transistor P9 is connected to the I0 input terminal of the first selector and the drain and gate short terminals of the PMOS transistor P5. The grid electrode of the PMOS tube P9 is connected with the drain electrode of the PMOS tube P6, the grid electrode of the PMOS tube P6 is connected with the input end of the I0 of the first selector, and the source electrode of the PMOS tube P6 is connected with the power supply VDD.

As shown in fig. 9, the frequency maintaining circuit 340 is used for maintaining the frequency corresponding to the control voltage VCONT in the RT mode. The frequency maintaining circuit 340 includes a PMOS transistor P7, a switch S4, an NMOS transistor N6, and a resistor R4.

Specifically, the source of the PMOS transistor P7 is connected to the power VDD, the gate of the PMOS transistor P7 is connected to the I0 input terminal of the first selector, the drain of the PMOS transistor P7 is connected to one end of the switch S4 and the output terminal of the loop filter 200, and specifically, the drain of the PMOS transistor P7 is connected to the connection end where the resistor R1 and the capacitor C2 are connected. The drain and the gate of the NMOS transistor N6 are shorted and connected to the other end of the switch S4, and the source of the NMOS transistor N6 is grounded through the resistor R4.

In the RT mode, the switch S4 is in a closed state. When the switch S4 is controlled by the control signal RT _ MODE, the control signal RT _ MODE is "1" and the control signal PLL _ MODE is "0", the switch S4 is closed, so that the frequency maintenance circuit 340 enters the RT MODE. At this time, the control voltage VCONT _ PRE output from the loop filter 200 is kept equal to the voltage at the drain of the PMOS transistor P7.

As shown in fig. 9, the first ramp voltage generating circuit 350 is used for outputting a corresponding ramp voltage V according to the mirror current output by the first current mirror circuit 320_RAMP1。

Specifically, the first ramp voltage generating circuit 350 includes an NMOS transistor N7 and a capacitor C_OSC1Capacitor C_OSC1One end of the first comparator is connected with the drain electrode of the NMOS transistor N7 and the positive electrode input end of the first comparator, the other end of the first comparator is connected with the source electrode of the NMOS transistor N7 and is grounded, and the grid electrode of the NMOS transistor N7 is connected with the output end of the first logic circuit.

As shown in FIG. 9, a first comparator is used to ramp the voltage V_RAMP1And a reference voltage V_{REF_OSC}After the comparison, the CLOCK signal CLOCK is output through the first logic circuit and the BUFFER BUFFER2, the output end of the first comparator is connected with the input end of the first logic circuit, and the output end of the first logic circuit is connected with the input end of the BUFFER BUFFER 2. The positive input terminal of the first comparator is connected to the first current mirror circuit 320 and the first ramp voltage generating circuit 350, and specifically, the positive input terminal of the first comparator is connected to the drain of the PMOS transistor P8 and the capacitor C_OSC1The negative input end of the first comparator is connected with a reference voltage V_{REF_OSC}. The output of the BUFFER BUFFER2 is connected to the I0 input of the second selector. The first logic circuitThere is a LOCK _ OSC1 output that outputs a control signal LOCK _ OSC 1.

As shown in fig. 9, the first selector has a control terminal receiving the control signal SEL _ PLL, AND the control terminal of the first selector is connected to the output terminal of the AND circuit AND 2. An a1 input terminal of the AND circuit AND2 is connected to an output terminal of the inverter INV1, an a2 input terminal of the AND circuit AND2 is connected to an input terminal of the first logic circuit AND simultaneously transmits the control signal PLL _ MODE, AND an input terminal of the inverter INV1 is connected to an input terminal of the first logic circuit AND simultaneously transmits the input signal FORCE _ FMIN.

As shown in fig. 10, the second oscillator 400 includes an NMOS transistor N3, a resistor R2, a PMOS transistor P3, a PMOS transistor P4, an NMOS transistor N4, and a capacitor C_OSC2A second comparator, a second logic circuit and a BUFFER 3. The PMOS transistor P3 and the PMOS transistor P4 form a second current mirror circuit. The NMOS transistor N4 and the capacitor COSC2 form a second ramp voltage generating circuit.

The gate of the NMOS transistor N3 is connected to the output terminal of the loop filter 200, and specifically, the gate of the NMOS transistor N3 is connected to the connection terminal where the resistor R1 and the capacitor C2 are connected. The source of the NMOS transistor N3 is grounded through a resistor R2, and the source of the NMOS transistor N3 is connected to the I1 input terminal of the first selector. The drain and the gate of the PMOS tube P3 are in short circuit and are connected with the drain of the NMOS tube N3 and the gate of the PMOS tube P4, the source of the PMOS tube P3 is connected with a power supply VDD, the source of the PMOS tube P4 is connected with the power supply VDD, and the drain of the PMOS tube P4 is connected with the positive input end of the second comparator. Capacitor C_OSC2One end of the second comparator is connected with the drain electrode of the NMOS tube N4 and the anode input end of the second comparator, and the capacitor C_OSC2The other end of the NMOS tube is connected with the source electrode of the NMOS tube N4 and is grounded. The gate of the NMOS transistor N4 is connected to the output terminal of the second logic circuit. The negative input end of the second comparator is connected with a reference voltage V_{REF_OSC}An output terminal of the second comparator is connected to an input terminal of the BUFFER3 through the second logic circuit, and an output terminal of the BUFFER3 is connected to an I1 input terminal of the second selector to output the clock signal CLK _ OSC 2. The second comparator is controlled by an enable signal EN2, and works normally when the enable signal EN2 is "1", and does not work when the enable signal EN2 is "0".

As shown in fig. 7 and 6, the control terminal of the second selector is connected to the output terminal of the inverter INV2, and the input terminal of the inverter INV2 is connected to the input terminal of LOCK _ OSC1 of the enable circuit and receives the control signal LOCK _ OSC 1.

In this embodiment, the first selector connects the PG signal at the I0 input terminal to the output terminal by default, and the PGATE signal output by the first selector is used as the gate input signal of the PMOS transistor P8; therefore, the frequency of the CLOCK signal CLOCK output by the first oscillator 300 at this time is determined by the resistor R in the RT mode_SETOr the lowest frequency when the input signal FORCE _ FMIN is "1". When the input signal FORCE _ FMIN is "0" and the control signal PLL _ MODE is "1", the control signal SEL _ PLL is set to "1", and the first selector connects the control voltage VCONT at the input terminal I1 to the output terminal, which outputs the signal PGATE as the gate input signal of the PMOS transistor P8. Therefore, the frequency of the CLOCK signal CLOCK output by the first oscillator 300 is synchronized to the frequency of the external CLOCK signal CLK _ SYNC by the first phase-locked loop adjustment.

The second selector connects by default the signal at the input terminal I0 (i.e. the CLOCK signal CLOCK output by the first oscillator 300) to the output terminal, which outputs the signal CLK _ IN as the input CLOCK signal to the D-flip-flop D2 IN the phase detector 100, when the first phase-locked loop synchronizes the frequency of the CLOCK signal CLOCK output by the first oscillator 300 to the frequency of the external CLOCK signal CLK _ SYNC. When the control signal LOCK _ OSC1 is "0", the second selector connects the signal at the input terminal of I1 (i.e., the clock signal CLK _ OSC2 output by the second oscillator 400) to the output terminal, and the output signal CLK _ IN is used as the input clock signal of the D-flip-flop D2 IN the phase detector 100, and the second phase-locked loop synchronizes the frequency of the clock signal CLK _ OSC2 output by the second oscillator 400 to the frequency of the external clock signal SYNC _ CLK.

In this embodiment, since the first phase-locked loop and the second phase-locked loop can be switched by switching the first oscillator 300 and the second oscillator 400, the voltage value of the control voltage VCONT can be always maintained at the value corresponding to the frequency of the external clock CLK _ SYNC, and the problem of abnormal behavior of the system when the system just exits from the lowest frequency operating state, which is similar to that in embodiment 1, does not occur. In this embodiment, when the system just exits the lowest frequency operating state, i.e. the input signal FORCE _ FMIN changes from "1" to "0", the frequency of the CLOCK signal CLOCK is immediately synchronized to the frequency of the external CLOCK signal CLK _ SYNC. The concrete implementation is as follows:

in this embodiment, in the PLL mode, if the system is operating in the lowest frequency operating state, i.e. the input signal FORCE _ FMIN is "1", the control signal LOCK _ OSC1 is set to "0", and the enable signal EN2 is set to "1". At this time, the CLOCK signal CLOCK output by the first oscillator 300 has a frequency equal to the lowest frequency, and the CLOCK signal CLK _ OSC2 output by the second oscillator 400 is fed back to the input terminal of the D-flip-flop D2 of the phase detector, so that the second phase-locked loop synchronizes the frequency of the CLOCK signal CLK _ OSC2 output by the second oscillator 400 to the frequency of the external CLOCK signal CLK _ SYNC, and the voltage value of the control voltage VCONT is established and maintained at the voltage value of the control voltage VCONT determined by the frequency of the external CLOCK signal CLK _ SYNC. Thus, when the system exits the lowest frequency operating state, i.e., the FORCE _ FMIN signal becomes "0", the control signal LOCK _ OSC1 is set to "1", and the enable signal EN2 is set to "0", when the CLOCK signal CLOCK output from the first oscillator 300 is fed back to the input terminal of the D flip-flop D2 in the phase detector, the first phase-locked loop will immediately synchronize the frequency of the CLOCK signal CLOCK output from the first oscillator 300 to the frequency of the external CLOCK signal CLK _ SYNC since the voltage value of the control voltage VCONT is already established and maintained.

As shown in fig. 11, which is a timing chart of the circuit of the present embodiment, the diagram shows timing charts of the system powering up in the RT mode and the PLL mode, respectively, where the enable signal EN _ CK and the enable signal EN are both "1". It can be seen that if the system is powered up in the RT MODE, the control signal RT _ MODE is "1", the control signal PLL _ MODE is "0", the control signal SEL _ PLL is "0", the control signal LOCK _ OSC1 is "0", and the enable signal EN2 is "0". When the input signal FORCE _ FMIN is "1", the enable signal EN1 is "0", the frequency of the CLOCK signal CLOCK is equal to the lowest frequency, and the voltage value of the control voltage VCONT is established and maintained at the voltage value corresponding to the lowest frequency. Then the input signal FORCE _ FMIN is "0"When the enable signal EN1 becomes "1", the frequency of the CLOCK signal CLOCK is controlled by the resistor R_SETThe value is set, and the voltage value of the control voltage VCONT is established and maintained at the corresponding frequency.

If the system is powered up in PLL MODE, control signal RT _ MODE is "0", control signal PLL _ MODE is "1", and enable signal EN1 is "0". When the input signal FORCE _ FMIN is "1", the control signal SEL _ PLL is "0", the control signal LOCK _ OSC1 is "0", the enable signal EN2 is "1", the frequency of the CLOCK signal CLOCK is equal to the lowest frequency, the frequency of the CLOCK signal CLOCK _ OSC2 is synchronized to the frequency of the external CLOCK signal CLK _ SYNC, and the voltage value of the control voltage VCONT is established and maintained at the voltage value of the control voltage VCONT corresponding to the frequency of the external CLOCK signal CLK _ SYNC. Then, when the input signal FORCE _ FMIN is "0", the control signal SEL _ PLL is "1", the control signal LOCK _ OSC1 is "1", and the enable signal EN2 is "0", since the voltage value of the control voltage VCONT has been established and maintained at the voltage value of the control voltage VCONT corresponding to the frequency of the external CLOCK signal CLK _ SYNC, the frequency of the CLOCK signal CLOCK is immediately synchronized to the frequency of the external CLOCK signal.

It can be seen that when the first oscillator 300 operates in the PLL mode, even if the system starts to operate in the lowest frequency operating state, i.e. the input signal FORCE _ FMIN is "1", and the frequency of the CLOCK signal CLOCK output by the first oscillator 300 is equal to the lowest frequency, because the control signal LOCK _ OSC1 is set to "0" at this time and the enable signal EN2 is set to "1", the CLOCK signal CLK _ OSC2 output by the second oscillator 400 is fed back to the input terminal of the D flip-flop D2 in the phase detector, and the second phase-locked loop synchronizes the frequency of the CLOCK signal CLK _ 2 output by the second oscillator 400 to the frequency of the external CLOCK signal CLK _ SYNC at this time, so that the voltage value of the control voltage VCONT is established and maintained at the voltage value of the control voltage VCONT determined by the frequency of the external CLOCK signal CLK _ OSC. Thus, when the lowest frequency working state is exited, the frequency of the CLOCK signal CLOCK output by the first oscillator is immediately synchronized to the frequency of the external CLOCK signal CLK _ SYNC by the first phase-locked loop.

As can be seen from fig. 11, the solution in this embodiment effectively solves the problem of the embodiment 1 that the system may behave abnormally just after exiting the lowest frequency operating state in the PLL mode. In this embodiment, when the input signal FORCE _ FMIN changes from "1" to "0", the frequency of the CLOCK signal CLOCK is synchronized to the frequency of the external CLOCK signal CLK _ SYNC.

The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims

1. A dual mode switching frequency control system, comprising:

the oscillator can output a CLOCK signal CLOCK with a preset frequency in an RT mode; in the PLL mode, the oscillator is capable of outputting a CLOCK signal CLOCK synchronized with an external CLOCK signal CLK _ SYNC; under the RT mode and/or the PLL mode, when the oscillator works in the lowest frequency working state, the CLOCK signal CLOCK with the lowest frequency can be output;

the phase detector is used for comparing the CLOCK signal CLOCK with the external CLOCK signal CLK _ SYNC in a PLL mode and generating error voltage corresponding to the phase difference between the CLOCK signal CLOCK and the external CLOCK signal CLK _ SYNC; and

and a loop filter for removing a high frequency signal and a noise signal in the error voltage and outputting a control voltage VCONT _ PRE for controlling the oscillator in a PLL mode, under the control of the control voltage VCONT _ PRE, a CLOCK signal CLOCK outputted from the oscillator can be synchronized to an external CLOCK signal CLK _ SYNC.

2. As claimed in claim 1The dual-mode switching frequency control system is characterized in that the oscillator comprises a mode conversion circuit, a current mirror circuit, a lowest frequency circuit, a frequency maintaining circuit, a ramp voltage generating circuit, a comparator, a logic circuit and a BUFFER; the mode conversion circuit is used for outputting corresponding current through the current mirror circuit according to corresponding control voltage in an RT mode and/or a PLL mode; the lowest frequency circuit is used for enabling the oscillator to output a CLOCK signal CLOCK with the lowest frequency; the frequency maintaining circuit is used for maintaining the frequency corresponding to the control voltage VCONT _ PRE in the RT mode; the ramp voltage generating circuit is used for outputting a corresponding ramp voltage V according to the current output by the current mirror circuit_RAMP(ii) a The comparator is used for converting the ramp voltage V_RAMPAnd a reference voltage V_{REF_OSC}After comparison, the CLOCK signal CLOCK is output through the logic circuit and the BUFFER.

3. The dual mode switching frequency control system of claim 2, wherein the lowest frequency circuit comprises a PMOS transistor P7, a resistor R3, a capacitor C3, a PMOS transistor P4, and a bias current source IBIAS2_ FMIN;

4. The dual mode switching frequency control system of claim 2, wherein the mode conversion circuit comprises a resistor R2, an NMOS transistor N3, a bias current source IBIAS1, an op-amp, a switch S3, a switch S4, a switch S5, a switch S6, a resistor R_SETResistance R_PLLNMOS transistor N4;

wherein the positive input end of the operational amplifier is connected with a reference voltage V through a switch S3_REFSaid electricityOne end of a resistor R2 is connected with a power supply VDD, the other end of the resistor R2 is connected with the drain electrode of an NMOS tube N3, the grid electrode of the NMOS tube N3 is connected with a control voltage VCONT _ PRE, the source electrode of the NMOS tube N3 is grounded through a bias current source IBIAS1, the source electrode of the NMOS tube N3 is simultaneously connected with the positive input end of an operational amplifier through a switch S4, and the negative input end of the operational amplifier is connected with a resistor R5 through a switch S5_SETConnection, the resistance R_SETThe other end of the operational amplifier is grounded, and the negative input end of the operational amplifier passes through a switch S6 and a resistor R_PLLConnection, the resistance R_PLLThe other end of the NMOS transistor N4 is grounded, the drain of the NMOS transistor N4 is connected with the current mirror circuit, the grid of the NMOS transistor N4 is connected with the output end of the operational amplifier, and the source of the NMOS transistor N4 is connected with the negative input end of the operational amplifier.

5. The dual-mode switching frequency control system according to claim 4, wherein the current mirror circuit comprises a PMOS transistor P3 and a PMOS transistor P6, the source of the PMOS transistor P3 is connected to the power VDD, the drain and the gate of the PMOS transistor P3 are shorted and connected to the gate of the PMOS transistor P6, the frequency maintaining circuit, the lowest frequency circuit and the mode converting circuit, the source of the PMOS transistor P6 is connected to the power VDD, and the drain of the PMOS transistor P6 is connected to the ramp voltage generating circuit and the positive input terminal of the comparator.

6. The dual mode switching frequency control system according to claim 5, wherein the frequency maintaining circuit comprises a PMOS transistor P5, an NMOS transistor N5, a resistor R4 and a switch S7, wherein a source of the PMOS transistor P5 is connected to a power VDD, a gate of the PMOS transistor P5 is connected to the current mirror circuit and the lowest frequency circuit, a drain of the PMOS transistor P5 is connected to the output terminal of the loop filter and the input terminal of the oscillator, a drain and a gate of the NMOS transistor N5 are shorted and connected to a drain of a PMOS transistor P5 through the switch S7, a source of the NMOS transistor N5 is grounded through the resistor R4, and the switch S7 is in a closed state in the RT mode.

7. The dual-mode switching frequency control system according to claim 6, wherein said ramp voltage generating circuit comprises an NMOS transistor N6 and a capacitor Cosc, said capacitor Cosc is connected to the drain of NMOS transistor N6 and the positive input terminal of said comparator at one end, and to the source of NMOS transistor N6 and ground at the other end, and the gate of NMOS transistor N6 is connected to the output terminal of the logic circuit.

8. The dual mode switching frequency control system of claim 7, wherein the frequency f of the CLOCK signal CLOCK is at RT mode₁The expression of (a) is:

f₁＝K*[V_REF/(R_SET*C_OSC*V_{REF_OSC})]；

frequency f of the CLOCK signal CLOCK in PLL mode₂The expression of (a) is:

f₂＝K*[V_CONT/(R_PLL*C_OSC*V_{REF_OSC})]＝f_{CLK_SYNC}；

9. A dual mode switching frequency control system, comprising: a first phase-locked loop including a phase discriminator, a loop filter, and a first oscillator;

10. The dual mode switching frequency control system of claim 9, wherein the first oscillator is capable of outputting a CLOCK signal CLOCK of a preset frequency in the RT mode.

11. The dual mode switching frequency control system of claim 9 further comprising a first selector and a second selector, the I0 input and the output of the first selector being connected to the first oscillator, the I1 input of the first selector being connected to the second oscillator, the I0 input of the second selector being connected to the output of the first oscillator, the I1 input of the second selector being connected to the output of the second oscillator, the output of the second selector being connected to the input of the phase detector, switching between the first oscillator and the second oscillator being enabled by the first selector and the second selector.

12. The dual mode switching frequency control system of claim 11, wherein said first oscillator includes a mode conversion circuit, a first current mirror circuit, a lowest frequency circuit, a frequency maintenance circuit, a first ramp voltage generation circuit, a first comparator, a first logic circuit, and a BUFFER2, said mode conversion circuit, said first ramp voltage generation circuit, and said first comparator are all connected to said first current mirror circuit, said lowest frequency circuit, and said frequency maintenance circuit are all connected to said first selector;

the mode conversion circuit is used for outputting corresponding mirror current through the first current mirror circuit in the RT mode; the lowest frequency circuit is used for enabling the first oscillator to output a CLOCK signal CLOCK with the lowest frequency; the frequency maintaining circuit is used for maintaining control in the RT modeA frequency corresponding to the control voltage VCONT; the first ramp voltage generating circuit is used for outputting a corresponding ramp voltage V according to the mirror current output by the first current mirror circuit_RAMP1(ii) a The first comparator is used for converting a ramp voltage V_RAMP1And a reference voltage V_{REF_OSC}The comparison is performed and then the CLOCK signal CLOCK is outputted through the first logic circuit and the BUFFER 2.

13. The dual mode switching frequency control system of claim 12, wherein said mode conversion circuit comprises an op-amp, a switch S3, a resistor R_SETAnd an NMOS transistor N5;

wherein the positive input end of the operational amplifier is connected with a control voltage V_REFThe negative electrode input end of the operational amplifier is connected with the resistor R through the switch S3_SETOne end of said resistor R_SETThe other end of the operational amplifier is grounded, the negative electrode input end of the operational amplifier is simultaneously connected with the source electrode of the NMOS tube N5, the grid electrode of the NMOS tube N5 is connected with the output end of the operational amplifier, the drain electrode of the NMOS tube N5 is connected with the first current mirror circuit, and the switch S3 is in a closed state in the RT mode.

14. The dual-mode switching frequency control system according to claim 12, wherein the first current mirror circuit comprises a PMOS transistor P5 and a PMOS transistor P8, the source of the PMOS transistor P5 is connected to the VDD, the drain and the gate of the PMOS transistor P5 are shorted and connected to the mode converting circuit and the I0 input terminal of the first selector, the gate of the PMOS transistor P8 is connected to the output terminal of the first selector, the source of the PMOS transistor P8 is connected to the VDD, and the drain of the PMOS transistor P8 is connected to the positive input terminal of the first comparator.

15. The dual mode switching frequency control system of claim 12, wherein the lowest frequency circuit comprises a PMOS transistor P9, a resistor R3, a capacitor C3, a PMOS transistor P6, and a bias current source IBIAS2_ FMIN;

16. The dual mode switching frequency control system of claim 12, wherein the frequency maintenance circuit comprises a PMOS transistor P7, a switch S4, an NMOS transistor N6, and a resistor R4;

17. The dual-mode switching frequency control system of claim 12, wherein said first ramp voltage generating circuit comprises an NMOS transistor N7 and a capacitor C_OSC1Said capacitor C_OSC1One end of the first comparator is connected with the drain electrode of the NMOS tube N7 and the positive electrode input end of the first comparator, the other end of the first comparator is connected with the source electrode of the NMOS tube N7 and is grounded, and the grid electrode of the NMOS tube N7 is connected with the output end of the first logic circuit.

18. The dual-mode switching frequency control system of claim 11, wherein the second oscillator comprises an NMOS transistor N3, a resistor R2, a PMOS transistor P3, a PMOS transistor P4, an NMOS transistor N4, a capacitor C_OSC2A second comparator, a second logic circuit and a BUFFER 3;

the gate of the NMOS transistor N3 is connected to the output terminal of the loop filter, the source of the NMOS transistor N3 is grounded via the resistor R2, and the source of the NMOS transistor N3 is connected to the I1 input terminal of the first selectorThe drain and the grid of PMOS pipe P3 short circuit and connect the drain of NMOS pipe N3 and the grid of PMOS pipe P4, the source connection power VDD of PMOS pipe P3, the source connection power VDD of PMOS pipe P4, the drain of PMOS pipe P4 is connected the positive input end of second comparator, electric capacity C_OSC2One end of the second comparator is connected with the drain electrode of the NMOS tube N4 and the positive input end of the second comparator, and the capacitor C_OSC2The other end of the first comparator is connected with the source electrode of the NMOS tube N4 and is grounded, the grid electrode of the NMOS tube N4 is connected with the output end of the second logic circuit, and the negative electrode input end of the second comparator is connected with a reference voltage V_{REF_OSC}The output terminal of the second comparator is connected to the input terminal of the BUFFER3 through the second logic circuit, and the output terminal of the BUFFER3 is connected to the I1 input terminal of the second selector.