CN113971015B - UIA2 computing circuit, data processing method, chip, electronic device and storage medium - Google Patents
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Abstract
本申请公开了一种UIA2计算电路及其数据处理方法、芯片、电子设备及存储介质,涉及信息安全技术领域,该UIA2计算电路包括64级MUL单元,以及与所述64级MUL单元分别对应连接的64级混合运算单元,其中:第i级MUL单元,用于接收64位的第一数据序列,并对所述64位的第一数据序列进行第i级MUL运算,得到第i级MUL运算结果,i为整数且i的取值从0遍历至63;第i级混合运算单元分别与第i‑1级混合运算单元和所述第i级MUL单元连接,用于接收第i‑1级运算单元的第i‑1级混合运算结果和所述第i级MUL运算结果,并基于所述第i‑1级混合运算结果和所述第i级MUL运算结果,得到第i级混合运算结果;其中,第N级混合运算结果为所述第一数据序列对应的运算结果。本申请可以实现UIA2I算法的并行计算。
This application discloses a UIA2 computing circuit and its data processing method, chip, electronic equipment and storage medium, which relates to the field of information security technology. The UIA2 computing circuit includes a 64-level MUL unit and is connected correspondingly to the 64-level MUL unit. A 64-level hybrid operation unit, wherein: the i-th level MUL unit is used to receive the 64-bit first data sequence and perform the i-th level MUL operation on the 64-bit first data sequence to obtain the i-th level MUL operation As a result, i is an integer and the value of i traverses from 0 to 63; the i-th level mixed operation unit is connected to the i-1 level mixed operation unit and the i-th level MUL unit respectively, and is used to receive the i-1 level The i-1th level mixed operation result of the operation unit and the i-th level MUL operation result, and based on the i-1th level mixed operation result and the i-th level MUL operation result, the i-th level mixed operation result is obtained ; Wherein, the Nth level mixed operation result is the operation result corresponding to the first data sequence. This application can implement parallel computing of the UIA2I algorithm.
Description
技术领域Technical Field
本申请涉及信息安全技术领域,更具体地,涉及一种UIA2计算电路及其数据处理方法、芯片、电子设备及存储介质。The present application relates to the field of information security technology, and more specifically, to a UIA2 computing circuit and a data processing method thereof, a chip, an electronic device, and a storage medium.
背景技术Background Art
随着移动通信技术的发展,基于网络协议(Internet Protocol,IP)的开放式网络架构以及无线传播的特性,安全问题成为移动通信装置的核心问题之一。目前安全性通常涉及机密性和完整性两个方面,因此网络安全架构协议中有许多标准化的加密算法与完整性保护算法。例如,在3GPP安全架构中存在一种基于SNOW-3G的UIA2消息完整性保护算法,该UIA2完整性保护算法会根据输入的消息计算一个32位的消息认证码MAC,从而可以根据该消息认证码MAC实现消息的完整性保护。With the development of mobile communication technology, based on the open network architecture of Internet Protocol (IP) and the characteristics of wireless communication, security issues have become one of the core issues of mobile communication devices. At present, security usually involves two aspects: confidentiality and integrity. Therefore, there are many standardized encryption algorithms and integrity protection algorithms in network security architecture protocols. For example, in the 3GPP security architecture, there is a UIA2 message integrity protection algorithm based on SNOW-3G. The UIA2 integrity protection algorithm calculates a 32-bit message authentication code MAC based on the input message, so that the integrity protection of the message can be achieved based on the message authentication code MAC.
然而,计算消息认证码MAC时,通常会包含MULxPOW(V,i,C)的计算,而计算公式又为MULxPOW(V,i,C)=MULx(MULxPOW(V,i-1,C),C),即第i次的计算依赖于第i-1次的结果(i为大于1的整数),从而在实现消息认证码MAC计算的硬件电路中,会包括多级组合电路,且每一级的输入都取决于上一级结果的输出,从而造成较长的组合逻辑链,对系统的时钟频率和吞吐量造成较大的影响。However, when calculating the message authentication code MAC, the calculation of MULxPOW(V, i, C) is usually included, and the calculation formula is MULxPOW(V, i, C) = MULx(MULxPOW(V, i-1, C), C), that is, the i-th calculation depends on the result of the i-1th calculation (i is an integer greater than 1). Therefore, the hardware circuit for implementing the message authentication code MAC calculation will include multiple stages of combinational circuits, and the input of each stage depends on the output of the result of the previous stage, resulting in a longer combinational logic chain, which has a greater impact on the system's clock frequency and throughput.
发明内容Summary of the invention
鉴于上述问题,本申请提出了一种UIA2计算电路及其数据处理方法、芯片、电子设备及存储介质。In view of the above problems, the present application proposes a UIA2 calculation circuit and a data processing method thereof, a chip, an electronic device and a storage medium.
第一方面,本申请实施例提供了一种UIA2计算电路,该UIA2计算电路包括64级MUL单元,以及与所述64级MUL单元分别对应连接的64级混合运算单元,其中:第i级MUL单元,用于接收64位的第一数据序列,并对所述64位的第一数据序列进行第i级MUL运算,得到第i级MUL运算结果,i为整数且i的取值从0遍历至63;第i级混合运算单元分别与第i-1级混合运算单元和所述第i级MUL单元连接,用于接收第i-1级运算单元的第i-1级混合运算结果和所述第i级MUL运算结果,并基于所述第i-1级混合运算结果和所述第i级MUL运算结果,得到第i级混合运算结果;其中,第N级混合运算结果为所述第一数据序列对应的运算结果。In a first aspect, an embodiment of the present application provides a UIA2 calculation circuit, which includes 64-level MUL units and 64-level mixed operation units respectively connected to the 64-level MUL units, wherein: the i-th level MUL unit is used to receive a 64-bit first data sequence, and perform an i-th level MUL operation on the 64-bit first data sequence to obtain an i-th level MUL operation result, where i is an integer and the value of i ranges from 0 to 63; the i-th level mixed operation unit is respectively connected to the i-1-th level mixed operation unit and the i-th level MUL unit, and is used to receive the i-1-th level mixed operation result of the i-1-level operation unit and the i-th level MUL operation result, and obtain the i-th level mixed operation result based on the i-1-th level mixed operation result and the i-th level MUL operation result; wherein the N-th level mixed operation result is the operation result corresponding to the first data sequence.
第二方面,本申请实施例提供了一种如第一方面所述的UIA2计算电路的数据处理方法,方法包括:第i级MUL单元接收64位的第一数据序列,并对所述64位的第一数据序列进行第i级MUL运算,得到第i级MUL运算结果;第i级混合运算单元接收第i-1级运算单元的第i-1级混合运算结果和所述第i级MUL运算结果,并基于所述第i-1级混合运算结果和所述第i级MUL运算结果,得到第i级混合运算结果;其中,第N级混合运算结果为所述第一数据序列对应的运算结果。In a second aspect, an embodiment of the present application provides a data processing method for the UIA2 computing circuit as described in the first aspect, the method comprising: an i-th level MUL unit receives a 64-bit first data sequence, and performs an i-th level MUL operation on the 64-bit first data sequence to obtain an i-th level MUL operation result; an i-th level mixing operation unit receives an i-1-th level mixing operation result of an i-1-th level operation unit and the i-th level MUL operation result, and obtains an i-th level mixing operation result based on the i-1-th level mixing operation result and the i-th level MUL operation result; wherein, the N-th level mixing operation result is the operation result corresponding to the first data sequence.
第三方面,本申请实施例提供了一种芯片,包括上述第一方面提供的UIA2计算电路。In a third aspect, an embodiment of the present application provides a chip, including the UIA2 calculation circuit provided in the first aspect above.
第四方面,本申请实施例提供了一种电子设备,包括:一个或多个处理器;存储器;一个或多个程序代码,其中所述一个或多个程序代码被存储在所述存储器中并被配置为由所述一个或多个处理器执行,所述一个或多个程序代码配置用于执行上述第二方面提供的数据处理方法。In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: one or more processors; a memory; and one or more program codes, wherein the one or more program codes are stored in the memory and configured to be executed by the one or more processors, and the one or more program codes are configured to execute the data processing method provided in the second aspect above.
第五方面,本申请实施例提供了一种计算机可读取存储介质,所述计算机可读取存储介质中存储有程序代码,所述程序代码可被处理器调用执行上述第二方面提供的数据处理方法,或调用执行上述第一方面提供的数据处理方法。In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, in which a program code is stored. The program code can be called by a processor to execute the data processing method provided in the second aspect, or to call and execute the data processing method provided in the first aspect.
本申请提供的方案,UIA2计算电路包括64级MUL单元,以及与所述64级MUL单元分别对应连接的64级混合运算单元,其中第i级MUL单元,用于接收64位的第一数据序列,并对所述64位的第一数据序列进行第i级MUL运算,得到第i级MUL运算结果,i为整数且i的取值从0遍历至63;第i级混合运算单元分别与第i-1级混合运算单元和所述第i级MUL单元连接,用于接收第i-1级运算单元的第i-1级混合运算结果和所述第i级MUL运算结果,并基于所述第i-1级混合运算结果和所述第i级MUL运算结果,得到第i级混合运算结果;其中,第N级混合运算结果为所述第一数据序列对应的运算结果。由此,本申请中MUL单元的每一级的计算可以只依赖于输入的64位的第一数据序列,无需依赖上一级MUL单元的输出,使得可以将原有的MUL单元的串行计算方式,改变为并行计算方式,提高了消息认证码MAC计算的硬件电路的速度的同时,也提高了时钟频率、满足吞吐量的需求。The solution provided by the present application, the UIA2 calculation circuit includes 64 levels of MUL units, and 64 levels of mixed operation units respectively connected to the 64 levels of MUL units, wherein the i-th level MUL unit is used to receive a 64-bit first data sequence, and perform an i-th level MUL operation on the 64-bit first data sequence to obtain an i-th level MUL operation result, i is an integer and the value of i ranges from 0 to 63; the i-th level mixed operation unit is respectively connected to the i-1-th level mixed operation unit and the i-th level MUL unit, and is used to receive the i-1-th level mixed operation result of the i-1-level operation unit and the i-th level MUL operation result, and obtain the i-th level mixed operation result based on the i-1-th level mixed operation result and the i-th level MUL operation result; wherein the N-th level mixed operation result is the operation result corresponding to the first data sequence. Therefore, the calculation of each level of the MUL unit in the present application can only rely on the input 64-bit first data sequence, without relying on the output of the MUL unit at the previous level, so that the original serial calculation method of the MUL unit can be changed to a parallel calculation method, which improves the speed of the hardware circuit of the message authentication code MAC calculation while also increasing the clock frequency to meet the throughput requirements.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
为了更清楚地说明本申请实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.
图1示出了一种MULxPOW(V,i,C)函数的计算电路结构示意图。FIG1 shows a schematic diagram of a calculation circuit structure of a MULxPOW(V, i, C) function.
图2示出了一种MULx(V,C)函数的计算电路结构示意图。FIG. 2 shows a schematic diagram of a calculation circuit structure of a MULx(V, C) function.
图3示出了一种MUL(V,P,C)函数的计算电路结构示意图。FIG3 shows a schematic diagram of a calculation circuit structure of a MUL (V, P, C) function.
图4示出了本申请提供的一种的按位计算电路示意图。FIG. 4 shows a method provided by the present application. Schematic diagram of the bitwise calculation circuit.
图5示出了本申请提供的一种的按位计算电路示意图。FIG. 5 shows a method provided by the present application. Schematic diagram of the bitwise calculation circuit.
图6示出了本申请提供的一种的按位计算电路示意图。FIG. 6 shows a method provided by the present application. Schematic diagram of the bitwise calculation circuit.
图7示出了本申请提供的一种的按位计算电路示意图。FIG. 7 shows a method provided by the present application. Schematic diagram of the bitwise calculation circuit.
图8示出了根据本申请一个实施例的数据处理方法的一种示意图。FIG8 shows a schematic diagram of a data processing method according to an embodiment of the present application.
图9示出了根据本申请另一个实施例的数据处理方法的一种示意图。FIG. 9 shows a schematic diagram of a data processing method according to another embodiment of the present application.
图10示出了根据本申请又一个实施例的数据处理方法的一种示意图。FIG10 shows a schematic diagram of a data processing method according to yet another embodiment of the present application.
图11示出了本申请提供的一种的按位计算电路示意图。FIG. 11 shows a method provided by the present application. Schematic diagram of the bitwise calculation circuit.
图12示出了本申请提供的一种的按位计算电路示意图。FIG. 12 shows a method provided by the present application. Schematic diagram of the bitwise calculation circuit.
图13示出了本申请提供的一种的按位计算电路示意图。FIG. 13 shows a method provided by the present application. Schematic diagram of the bitwise calculation circuit.
图14示出了根据本申请再一个实施例的数据处理电路的一种框图。FIG. 14 shows a block diagram of a data processing circuit according to yet another embodiment of the present application.
图15示出了本申请提供的一种MUL(V,P,C)函数的计算电路结构示意图。FIG15 shows a schematic diagram of a calculation circuit structure of a MUL (V, P, C) function provided by the present application.
图16是本申请实施例的用于执行根据本申请实施例的数据处理方法的电子设备的框图。FIG. 16 is a block diagram of an electronic device for executing a data processing method according to an embodiment of the present application.
图17是本申请实施例的用于保存或者携带实现根据本申请实施例的数据处理方法的程序代码的存储单元。FIG. 17 is a storage unit according to an embodiment of the present application for storing or carrying program codes for implementing a data processing method according to an embodiment of the present application.
具体实施方式DETAILED DESCRIPTION
为了使本技术领域的人员更好地理解本申请方案,下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述。In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.
相关技术中,以UIA2完整性保护算法为例,其计算消息认证码MAC的过程通常包括以下步骤:In the related art, taking the UIA2 integrity protection algorithm as an example, the process of calculating the message authentication code MAC generally includes the following steps:
第一步,设LENGTH是用于计算MAC数据的比特长度,MESSAGE是数据本身。In the first step, let LENGTH be the length in bits used to calculate the MAC data, and MESSAGE be the data itself.
第二步,设D=LENGTH/64向上取整+1,LENGTH为消息的长度,以比特为单位,即根据MESSAGE的长度,将MESSAGE划分为D个64位消息。In the second step, let D = LENGTH/64 rounded up + 1, where LENGTH is the length of the message in bits, that is, according to the length of the MESSAGE, the MESSAGE is divided into D 64-bit messages.
第三步,使用Snow-3G密钥生成器生成5个32位字构成的密钥,以此设为Z1,Z2,Z3,Z4,Z5。Z1是第一次输出的密钥,Z5是最后一次生成的密钥。The third step is to use the Snow-3G key generator to generate five 32-bit words of keys, which are set as Z1, Z2, Z3, Z4, and Z5. Z1 is the first key output, and Z5 is the last key generated.
第四步,设P=Z1并上Z2,Q=Z3并上Z4。Step 4: Assume P=Z1 plus Z2, Q=Z3 plus Z4.
第五步,令Z5=OTP[0]并上OTP[1]并上OTP[2]并上…并上OTP[31],其中OTP[0]是最高有效位,OTP[31]是最低有效位。Step 5. Set Z5 = OTP[0] plus OTP[1] plus OTP[2] plus ... plus OTP[31], where OTP[0] is the most significant bit and OTP[31] is the least significant bit.
第六步,对于i=0到D-3,设M[i]=MESSAGE[64*i]并上MESSAGE[64*i+1]并上…并上MESSAGE[64*i+32];对于i=D-2,设M[D-2]=MESSAGE[64*(D-2)]并上…并上MESSAGE[LENGTH-1]并上0并上...并上0;对于i=D-1,设M[D-1]=LENGTH[0]并上LENGTH[1]并上…并上LENGTH[63]。Step 6. For i=0 to D-3, set M[i]=MESSAGE[64*i] and MESSAGE[64*i+1] and… and MESSAGE[64*i+32]; for i=D-2, set M[D-2]=MESSAGE[64*(D-2)] and… and MESSAGE[LENGTH-1] and 0 and… and 0; for i=D-1, set M[D-1]=LENGTH[0] and LENGTH[1] and… and LENGTH[63].
第七步,令64位宽的EVAL=0,即定义估计值(EVAL)的初始值为0。Step 7: Set 64-bit wide EVAL=0, that is, define the initial value of the estimated value (EVAL) as 0.
第八步,对于i=0到D-2,EVAL=MUL(EVAL xor M[i],P,0x0000 0000 0000001B)。Step 8. For i=0 to D-2, EVAL=MUL(EVAL xor M[i], P, 0x0000 0000 0000001B).
第九步,EVAL=EVAL xor M[D-1]。Step 9, EVAL = EVAL xor M[D-1].
第十步,EVAL=MUL(EVAL,Q,0x0000 0000 0000 001B)。Step 10, EVAL=MUL(EVAL,Q,0x0000 0000 0000 001B).
第十一步,令EVAL=e[0]并上e[1]并上…并上e[63],其中e[0]是最高有效位,e[63]是最低有效位。Step 11. Let EVAL = e[0] plus e[1] plus ... plus e[63], where e[0] is the most significant bit and e[63] is the least significant bit.
第十二步,对i=0到31,MAC[i]=e[i]xor OTP[i],即截取e的前32位并与OTP进行异或,生成应用UIA2完整性保护算法的MESSAGE的消息认证码MAC。Step 12: for i=0 to 31, MAC[i]=e[i]xor OTP[i], i.e., the first 32 bits of e are intercepted and XORed with OTP to generate the message authentication code MAC of the MESSAGE using the UIA2 integrity protection algorithm.
其中,UIA2完整性保护算法计算MAC的过程中用到的函数伪代码说明如下:The pseudo code of the function used in the process of calculating MAC by the UIA2 integrity protection algorithm is as follows:
V,P,C均为64位的数据时,MUL(V,P,C)函数的伪代码可以为:When V, P, and C are all 64-bit data, the pseudo code of the MUL(V, P, C) function can be:
result=0;result = 0;
for i=0to 63inclusive;for i=0to63inclusive;
if(P>>i)&0x01 equals 0x01if(P>>i)&0x01 equals 0x01
result=result xor MULxPOW(V,i,C);result=result xor MULxPOW(V,i,C);
其中,MULxPOW(V,i,C)函数的伪代码可以为:Among them, the pseudo code of the MULxPOW(V, i, C) function can be:
if(i==0)if(i == 0)
MULxPOW(V,i,C)=V;MULxPOW(V,i,C)=V;
elseelse
MULxPOW(V,i,C)=MULx(MULxPOW(V,i-1,C),C);MULxPOW(V,i,C)=MULx(MULxPOW(V,i-1,C),C);
其中,MULx(V,C)函数的伪代码可以为:Among them, the pseudo code of the MULx(V, C) function can be:
if(V[63]==1)if(V[63] == 1)
MULx(V,C)=(V<<1)xor C;MULx(V, C) = (V<<1)xor C;
elseelse
MULx(V,C)=(V<<1);MULx(V, C) = (V<<1);
进一步地,将MUL(V,P,C)函数伪代码进行展开,可以得到:Furthermore, by expanding the pseudo code of the MUL(V, P, C) function, we can obtain:
result=0;result = 0;
result=p[0]==1?result xor MULxPOW(V,0,C):result;result=p[0]==1? result xor MULxPOW(V,0,C):result;
result=p[1]==1?result xor MULxPOW(V,1,C):result;result=p[1]==1? result xor MULxPOW(V,1,C):result;
result=p[2]==1?result xor MULxPOW(V,2,C):result;result=p[2]==1? result xor MULxPOW(V,2,C):result;
………
result=p[63]==1?result xor MULxPOW(V,63,C):result;result=p[63]==1? result xor MULxPOW(V, 63, C):result;
从MULxPOW(V,P,C)的伪代码中可见,当i=0时,MULXPOW(V,0,C)=V,相当于给定了一个计算MUL(V,P,C)函数的初始条件,从而可以得到MUL(V,P,C)函数展开伪代码中第2步的结果,即:From the pseudo code of MULxPOW(V, P, C), when i=0, MULXPOW(V, 0, C)=V, which is equivalent to giving an initial condition for calculating the MUL(V, P, C) function, so that the result of step 2 in the pseudo code of the MUL(V, P, C) function expansion can be obtained, that is:
result=p[0]==1?result xor V:result;result=p[0]==1? result xor V:result;
然后对于MULxPOW(V,P,C)伪代码中第3步,又需要得到MULxPOW(V,1,C)的结果,而从MULxPOW(V,P,C)的伪代码中可见,当i=1时,MULxPOW(V,1,C)=MULx(MULxPO W(V,0,C),C),从而将MULxPOW(V,1,C)变换为以MULxPOW(V,0,C)为变量的函数。Then, for the third step in the pseudocode of MULxPOW(V, P, C), it is necessary to get the result of MULxPOW(V, 1, C). It can be seen from the pseudocode of MULxPOW(V, P, C) that when i=1, MULxPOW(V, 1, C)=MULx(MULxPO W(V, 0, C), C), thereby transforming MULxPOW(V, 1, C) into a function with MULxPOW(V, 0, C) as the variable.
以此类推,我们可以将MULxPOW(V,i,C)变换为以MULxPOW(V,i-1,C)为变量的函数,计算过程如下所示:By analogy, we can transform MULxPOW(V, i, C) into a function with MULxPOW(V, i-1, C) as a variable. The calculation process is as follows:
MULxPOW(V,0,C)=V;MULxPOW(V,0,C)=V;
MULxPOW(V,1,C)=MULx(MULxPOW(V,0,C),C);MULxPOW(V,1,C)=MULx(MULxPOW(V,0,C),C);
MULxPOW(V,2,C)=MULx(MULxPOW(V,1,C),C);MULxPOW(V,2,C)=MULx(MULxPOW(V,1,C),C);
………
MULxPOW(V,63,C)=MULx(MULxPOW(V,62,C),C)。MULxPOW(V,63,C)=MULx(MULxPOW(V,62,C),C).
可以看出,每一行的计算依赖于上一行的结果,因此,相关技术中在进行MULxPOW(V,i,C)的硬件电路设计时,常用一种串行电路来计算MULxPOW(V,i,C)的结果。示例性地,请参阅图1,图1示出了一种MULxPOW(V,i,C)函数的计算电路结构,可以看出在该串行电路中,除了首级方框的电路是一个常数V以外,其余方框中的电路均为MULx(V,C)电路,且每一级的输入都取决于上一级MULx(V,C)结果的输出。而从MULx(V,C)的伪代码中,可以看出MULx(V,C)电路由判断、选择与异或等几个操作组成,实现比较简单。示例性地,请参阅图2,图2示出了一种MULx(V,C)函数的计算电路结构。It can be seen that the calculation of each row depends on the result of the previous row. Therefore, in the related art, when designing the hardware circuit of MULxPOW (V, i, C), a serial circuit is often used to calculate the result of MULxPOW (V, i, C). For example, please refer to Figure 1, which shows a calculation circuit structure of a MULxPOW (V, i, C) function. It can be seen that in this serial circuit, except for the circuit of the first-level box which is a constant V, the circuits in the remaining boxes are all MULx (V, C) circuits, and the input of each level depends on the output of the result of the previous level MULx (V, C). From the pseudo code of MULx (V, C), it can be seen that the MULx (V, C) circuit consists of several operations such as judgment, selection and XOR, and the implementation is relatively simple. For example, please refer to Figure 2, which shows a calculation circuit structure of a MULx (V, C) function.
而对于MUL(V,P,C)函数的硬件电路实现,从MUL(V,P,c)的伪代码中可以看出,在得到上述MULxPOW(V,i,C)计算电路后,只需要引入关于P的选择电路与MULxPOW(V,i,C)结果的异或电路即可。示例性地,请参阅图3,图3示出了一种MUL(V,P,C)函数的计算电路结构。As for the hardware circuit implementation of the MUL(V, P, C) function, it can be seen from the pseudo code of MUL(V, P, c) that after obtaining the above-mentioned MULxPOW(V, i, C) calculation circuit, it is only necessary to introduce the selection circuit for P and the XOR circuit of the MULxPOW(V, i, C) result. For example, please refer to FIG3, which shows a calculation circuit structure of the MUL(V, P, C) function.
结合图3可以发现,MUL(V,P,C)的计算是多级异或与选择的串行结果,每一级的输入都取决于上一级MULxPOW(V,i,C)结果的输出,这样的实现方法必然造成较长的组合逻辑链,在芯片综合时很难将上述电路在要求的时钟频率下由一级流水实现。即便能够实现,综合工具也会相当吃力,使用快速逻辑单元对该路径进行优化,提升了速度但同时也增加了功耗。还有一种可能性是在要求的时钟频率下,综合工具根本不能在一级流水中实现,这样就需要对计算进行打拍,将其拆分为两级组合逻辑,由两个甚至更多的时钟周期来完成一次计算,这样无疑降低了系统计算的吞吐量。Combined with Figure 3, it can be found that the calculation of MUL (V, P, C) is the serial result of multi-level XOR and selection. The input of each level depends on the output of the result of the previous level MULxPOW (V, i, C). Such an implementation method will inevitably result in a long combinational logic chain. It is difficult to implement the above circuit in a one-level pipeline at the required clock frequency during chip synthesis. Even if it can be implemented, the synthesis tool will be quite strenuous. The path is optimized using fast logic units, which increases the speed but also increases power consumption. Another possibility is that at the required clock frequency, the synthesis tool cannot be implemented in a one-level pipeline at all. In this case, the calculation needs to be beat and split into two-level combinational logic. One calculation is completed by two or even more clock cycles, which undoubtedly reduces the throughput of the system calculation.
为了改善上述问题,发明人经过长时间的研究发现,在UIA2完整性保护算法中,MUL(V,P,C)的输出结果是64位的数据,而V、P、C也都是64位的数据,因此,可该函数可以理解为将一个192位的输入(64+64+64)映射到了一个64位的输出。且结合UIA2算法计算MAC的过程,发明人还发现,需要用到MUL(V,P,C)函数的第八步“对于i=0到D-2,EVAL=MUL(EVALxor M[i],P,0x0000 0000 0000 001B)”,以及第十步“EVAL=MUL(EVAL,Q,0x0000 00000000In order to improve the above problems, the inventors have found after a long period of research that in the UIA2 integrity protection algorithm, the output result of MUL(V, P, C) is 64-bit data, and V, P, and C are also 64-bit data. Therefore, the function can be understood as mapping a 192-bit input (64+64+64) to a 64-bit output. In combination with the process of calculating MAC by the UIA2 algorithm, the inventors also found that the eighth step of the MUL(V, P, C) function "for i=0 to D-2, EVAL=MUL(EVALxor M[i], P, 0x0000 0000 0000 001B)" and the tenth step "EVAL=MUL(EVAL, Q, 0x0000 00000000
001B)”的地方,参数C都是一个常数,即C=0x0000 0000 0000 001B。001B)", the parameter C is a constant, that is, C = 0x0000 0000 0000 001B.
由于MUL(V,P,C)函数的计算过程可以先抛开P不计,只关心MULxPOW(V,i,C),因此此时可以将MUL(V,P,C)看成以V为变量的函数,由于此时MUL(V,P,C)为单一变量的函数,必然存在一个一对一的映射关系,从而可以利用该映射关系,使得每级电路的实现只依赖于输出V,无需依赖上一级的输出,进而简化了电路的实现。Since the calculation process of the MUL(V, P, C) function can ignore P and only care about MULxPOW(V, i, C), MUL(V, P, C) can be regarded as a function with V as the variable. Since MUL(V, P, C) is a function of a single variable at this time, there must be a one-to-one mapping relationship. This mapping relationship can be used to make the implementation of each level of the circuit only depend on the output V, without relying on the output of the previous level, thereby simplifying the implementation of the circuit.
具体地,发明人提出了一种数据处理方法、电路、芯片、电子设备及存储介质,可以参数C为常量的特点,来确定输入V和函数输出的映射关系,以使MULxPOW(V,i,C)函数的每一级的计算可以只依赖于输入V,无需依赖上一级的输出,从而可以将原有的MULxPOW(V,i,C)函数的串行计算方式,改变为并行计算方式,提高了消息认证码MAC计算的硬件电路的速度的同时,也提高了时钟频率、满足吞吐量的需求。Specifically, the inventors proposed a data processing method, circuit, chip, electronic device and storage medium, which can use the characteristic of parameter C as a constant to determine the mapping relationship between input V and function output, so that the calculation of each level of the MULxPOW (V, i, C) function can only depend on the input V without relying on the output of the previous level. Therefore, the original serial calculation method of the MULxPOW (V, i, C) function can be changed to a parallel calculation method, which improves the speed of the hardware circuit of the message authentication code MAC calculation while also increasing the clock frequency to meet the throughput requirements.
下面先对输入V和函数输出的映射关系的确定过程进行描述。The following first describes the process of determining the mapping relationship between the input V and the function output.
以UIA2完整性保护算法为例,MUL(V,P,C)函数中V,P,C均为64位数据,且C=0x0000 00000000 001B。由于MUL(V,P,C)函数的计算过程可以先抛开P不计,只关心MULxPOW(V,i,C),而根据图1所示的电路结构,MULxPOW(V,i,C)除了首级方框的电路是一个常数V以外,其余方框中的电路均为MULx(V,C)电路。因此,为了便于描述,可以先对MUL(V,P,C)函数进行化简:Taking the UIA2 integrity protection algorithm as an example, in the MUL(V, P, C) function, V, P, and C are all 64-bit data, and C = 0x0000 00000000 001B. Since the calculation process of the MUL(V, P, C) function can ignore P first, only MULxPOW(V, i, C) is concerned, and according to the circuit structure shown in Figure 1, except for the circuit of the first-level block of MULxPOW(V, i, C), which is a constant V, the circuits in the remaining blocks are all MULx(V, C) circuits. Therefore, for the convenience of description, the MUL(V, P, C) function can be simplified first:
令并将记作那么MULx(V,C)的n级嵌套可以写作 make and will Recorded as Then the n-level nesting of MULx(V, C) can be written as
由于MULxPOW(V,0,C)=V,因此, MULxPOW(V,2,C)=MULx(MULxPOW(V,1,C),Since MULxPOW(V, 0, C) = V, therefore, MULxPOW(V,2,C)=MULx(MULxPOW(V,1,C),
以此类推,可以得到: By analogy, we can get:
从而 thereby
基于上述定义,利用C=0x0000 0000 0000 001B(下述用0x1B)的条件对MULxPOW(V,1,C)=MULx(MULxPOW(V,0,C),C)进行简化,可以得到: Based on the above definition, using the condition of C = 0x0000 0000 0000 001B (hereinafter referred to as 0x1B) to simplify MULxPOW(V, 1, C) = MULx(MULxPOW(V, 0, C), C), we can get:
而根据MULx(V,C)函数的伪代码,可以知道,当参数V的最高位V[63]为1时,MULx(V,C)=(V<<1)xor C,当参数V的最高位V[63]不为1时,MULx(V,C)=(V<<1),其中,xor为一个逻辑运算符,意为按位异或,其数学符号为 的运算法则为:如果a、b两个值不相同,则异或结果为1;如果a、b两个值相同,异或结果为0。According to the pseudo code of the MULx(V, C) function, we can know that when the highest bit V[63] of the parameter V is 1, MULx(V, C) = (V<<1)xor C, and when the highest bit V[63] of the parameter V is not 1, MULx(V, C) = (V<<1), where xor is a logical operator, meaning bitwise exclusive OR, and its mathematical symbol is The operation rule is: if the values of a and b are different, the XOR result is 1; if the values of a and b are the same, the XOR result is 0.
因此,可以简写为:therefore, It can be shortened to:
然而,发明人经过研究发现,由于0x1B的64位的二进制数为0000 0000 0000 00000000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1011,即左半部分由59个0组成,而当某个值a与0进行异或时,异或结果均与值a相同(即),因此,当与0x1B进行按位异或计算时,左半部分59个0对应的输出,可以直接是的左半部分的59位数值,而对于值为1的比特位,由于与0x1B的异或操作,是在为1时才进行,因此,在时,为1,从而可以将0x1B的64位的二进制数中值为1的比特位,用代替1。从而,可以继续简写为:However, the inventors have found through research that since the 64-bit binary number of 0x1B is 0000 0000 0000 000000000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1011, that is, the left half consists of 59 zeros, and when a value a is XORed with 0, the XOR result is the same as the value a (i.e. ), so when When the bitwise XOR calculation is performed with 0x1B, the output corresponding to the 59 0s in the left half can be directly The 59-bit value of the left half of the value, and for the bit with value 1, due to The XOR operation with 0x1B is is 1, so hour, is 1, so the bits with a value of 1 in the 64-bit binary number 0x1B can be used Replace 1. Thus, It can be further abbreviated as:
由于所以也可以简写为V[63]}:(V<<1)。其中{0,0,…,0,V[63],V[63],0,V[63],V[63]}左半部分有59个0组成,对应64位0x1B中左半部分59个比特位的0。because So it can also be abbreviated as V[63]}: (V<<1). The left half of {0, 0, …, 0, V[63], V[63], 0, V[63], V[63]} consists of 59 zeros, corresponding to the 59 bits of zeros in the left half of the 64-bit 0x1B.
可以理解的是,当最高位V[63]不为1即为0时,其可以相当于,(V<<1)与64位均为0的数据进行异或,异或结果仍然为(V<<1)。因此当V[63]=0时,仍可以使 由于此时V[63]=0,因此可以相当于 从而可以相当于因此,最高位V[63]无论是否为1,都可以直接简写为:It can be understood that when the highest bit V[63] is not 1 but 0, This is equivalent to performing an XOR operation on (V<<1) and data with 64 bits of 0, and the XOR result is still (V<<1). Therefore, when V[63]=0, Since V[63]=0 at this time, it can be equivalent to So it is equivalent to Therefore, regardless of whether the highest bit V[63] is 1 or not, Can be directly abbreviated as:
其中,<<为左移运算符,表示按二进制形式把所有的数字向左移动对应的位数,高位移出(舍弃),低位的空位补零。从而V<<1可以理解为,将V的64位数据V[63]~V[0]向左移动1位,从而高位V[63]移出,低位的空位补上0。Among them, << is the left shift operator, which means that all the numbers are shifted to the left by the corresponding number of bits in binary form, the high bits are removed (discarded), and the low bits are filled with zeros. Therefore, V<<1 can be understood as shifting the 64-bit data V[63]~V[0] of V to the left by 1 bit, so that the high bit V[63] is removed and the low bits are filled with 0.
从而可以看出,的结果,可以是通过将输入参数V左移1位后,将移位后的结果在指定比特位与V[63]进行按位异或运算后得到,也就是说能够直接根据输入参数V得到,也即得到了与输入参数V的映射关系。Thus, it can be seen that The result can be obtained by shifting the input parameter V left by 1 bit and performing a bitwise XOR operation on the shifted result and V[63] at the specified bit position, that is, It can be directly obtained according to the input parameter V, that is, The mapping relationship with the input parameter V.
基于上述分析,进而可以实现的计算电路设计。示例性地,请参阅图4,图4示出了一种的按位计算电路示意图。其中,M的64位数据M[63]~M[0]对应的是V的64位数据V[63]~V[0]向左移动1位后的移位结果,相当于V<<1。由于M与{0,0,…,0,V[63],V[63],0,V[63],V[63]}中值为0的比特位进行异或时,异或结果仍是对应的M值,因此,可以仅对非0值的比特位进行异或电路的设计。即如图4所示,由于{0,0,…,0,V[63],V[63],0,V[63],V[63]}中仅在比特位为0、1、3、4处为非0值V[63],因此,可以仅在M[0]、M[1]、M[3]、M[4]处增加与V[63]的按位异或电路。可以看出,本申请的硬件电路实现,仅依赖于输入参数V。Based on the above analysis, we can achieve For example, please refer to FIG. 4, which shows a circuit design of a Schematic diagram of the bitwise calculation circuit. Among them, the 64-bit data M[63]~M[0] of M corresponds to the shift result of the 64-bit data V[63]~V[0] of V after being shifted 1 bit to the left, which is equivalent to V<<1. Since when M is XORed with the bit with a value of 0 in {0, 0, …, 0, V[63], V[63], 0, V[63], V[63]}, the XOR result is still the corresponding M value, therefore, the XOR circuit can be designed only for the bit with a non-zero value. That is, as shown in Figure 4, since {0, 0, …, 0, V[63], V[63], 0, V[63], V[63]} only has a non-zero value V[63] at bits 0, 1, 3, and 4, therefore, the bitwise XOR circuit with V[63] can be added only at M[0], M[1], M[3], and M[4]. It can be seen that the present application The hardware circuit implementation only depends on the input parameter V.
同理,基于上述定义,对MULxPOW(V,2,C)=MULx(MULxPOW(V,1,C),C)进行简化时,可以得到: Similarly, based on the above definition, when MULxPOW(V, 2, C) = MULx(MULxPOW(V, 1, C), C) is simplified, we can get:
而根据MULx(V,C)函数的伪代码,可以知道,当参数V的最高位V[63]为1时,MULx(V,C)=(V<<1)xor C,当参数V的最高位V[63]不为1时,MULx(V,C)=(V<<1)。由于此时参数V为则参数V的最高位V[63]为因此,可以简写为:According to the pseudo code of the MULx(V, C) function, we can know that when the highest bit V[63] of the parameter V is 1, MULx(V, C) = (V<<1)xor C, and when the highest bit V[63] of the parameter V is not 1, MULx(V, C) = (V<<1). Since the parameter V is Then the highest bit V[63] of parameter V is therefore, It can be shortened to:
首先确定的值,具体地:First determine The values of, specifically:
由于因此,because therefore,
由于C=0x1B,而C的最高位C[63]为0,因此,可以继续简写为:because C=0x1B, and the highest bit C[63] of C is 0, so, It can be further abbreviated as:
由于某个值a与0进行异或时,异或结果均与值a相同,因此(V<<1)[63]xor0的异或结果仍为(V<<1)[63]。从而可以看出,无论V[63]是否为1,均为(V<<1)[63]。所以可以直接简写为: Since when a value a is XORed with 0, the XOR result is the same as the value a, the XOR result of (V<<1)[63]xor0 is still (V<<1)[63]. It can be seen that no matter whether V[63] is 1 or not, All are (V<<1)[63]. It can be directly shortened to:
其中,(V<<1)[63]可以理解为将V左移1位后新的最高比特位的值,由于V<<1是将V的64位数据V[63]~V[0]向左移动1位,从而高位V[63]移出,新的最高比特位的值为V[62]。进而可以得到, Among them, (V<<1)[63] can be understood as the value of the new highest bit after V is shifted left by 1 bit. Since V<<1 is to shift V's 64-bit data V[63]~V[0] to the left by 1 bit, the high bit V[63] is shifted out, and the new highest bit value is V[62]. Then we can get,
基于此,可以继续简写为:Based on this, It can be further abbreviated as:
同理,由于0x1B的64位的二进制数的左半部分由59个0组成,因此,当与0x1B进行按位异或计算时,左半部分59个0对应的输出,可以直接是的左半部分的59位数值,而对于值为1的比特位,由于与0x1B的异或操作,是在V[62]为1时才进行,因此,在 时,V[62]为1,从而可以将0x1B的64位的二进制数中值为1的比特位,用V[62]代替1。从而,可以继续简写为:Similarly, since the left half of the 64-bit binary number 0x1B consists of 59 zeros, when When the bitwise XOR calculation is performed with 0x1B, the output corresponding to the 59 0s in the left half can be directly The 59-bit value of the left half of the value, and for the bit with value 1, due to The XOR operation with 0x1B is performed only when V[62] is 1. When , V[62] is 1, so the bits with a value of 1 in the 64-bit binary number 0x1B can be replaced by 1 with V[62]. Thus, It can be further abbreviated as:
基于上述公式,可以看出,当V[62]不为1即为0时,其可以相当于,与64位均为0的数据进行异或,异或结果仍然为因此当V[62]=0时,仍可以使由于此时V[62]=0,因此可以相当于从而可以相当于因此,V[62]无论是否为1,都可以直接简写为:Based on the above formula, it can be seen that when V[62] is not 1 or 0, It can be equivalent to, XOR with data where all 64 bits are 0, the XOR result is still Therefore, when V[62] = 0, Since V[62] = 0 at this time, it can be equivalent to So it is equivalent to Therefore, whether V[62] is 1 or not, Can be directly abbreviated as:
从而可以看出,的结果,可以是通过将移位1位后,将移位后的结果在指定比特位与V[62]进行按位异或运算后得到。由于前述已确定能够直接根据输入参数V得到,而除了外,也只与V[62]有关,因此实质上也能够直接根据输入参数V得到,也即得到了与输入参数V的映射关系。Thus, it can be seen that The result can be obtained by After shifting by 1 bit, the shifted result is obtained by performing a bitwise XOR operation with V[62] at the specified bit position. can be obtained directly from the input parameter V, and Apart from In addition, it is only related to V[62], so In fact, it can also be obtained directly according to the input parameter V, that is, The mapping relationship with the input parameter V.
基于上述分析,在得到前述的计算电路后,也可以实现的计算电路设计。示例性地,请参阅图5,图5示出了一种的按位计算电路示意图。如图5所示,的计算电路包含了大部分的计算电路外,还新增了4个与V[62]的按位异或电路。从图5可以看出,本申请的硬件电路实现,也仅依赖于输入参数V。Based on the above analysis, we can get the above After the calculation circuit, it can also be realized For example, please refer to FIG5 , which shows a calculation circuit design. Schematic diagram of the bit-by-bit calculation circuit. As shown in Figure 5, The calculation circuit includes In addition to most of the calculation circuits, 4 bitwise XOR circuits with V[62] are added. As can be seen from Figure 5, this application The hardware circuit implementation also only depends on the input parameter V.
具体地,M的64位数据M[63]~M[0]对应的是的64位数据向左移动1位后的移位结果,如图5所示的虚线框中所展示的的计算电路向左移动1位后的计算电路,相当于由于M与{0,0,…,0,V[62],V[62],0,V[62],V[62]}中值为0的比特位进行异或时,异或结果仍是对应的M值,因此,可以仅对非0值的比特位进行异或电路的设计。即如图5所示,由于{0,0,…,0,V[62],V[62],0,V[62],V[62]}中仅在比特位为0、1、3、4处为非0值V[62],因此,可以仅在M[0]、M[1]、M[3]、M[4]处增加与V[62]的按位异或电路。Specifically, the 64-bit data M[63] to M[0] of M corresponds to The shift result after the 64-bit data is shifted left by 1 bit is shown in the dotted box in Figure 5. The calculation circuit of the calculation circuit after shifting 1 bit to the left is equivalent to Since when M is XORed with a bit with a value of 0 in {0, 0, ..., 0, V[62], V[62], 0, V[62], V[62]}, the XOR result is still the corresponding M value, it is possible to design XOR circuits only for bits with a value other than 0. That is, as shown in FIG5 , since only bits 0, 1, 3, and 4 in {0, 0, ..., 0, V[62], V[62], 0, V[62], V[62]} are non-zero values V[62], it is possible to add bitwise XOR circuits with V[62] only at M[0], M[1], M[3], and M[4].
如此,从图5可以看出,本申请的硬件电路实现,实质上是将V的64位数据V[63]~V[0]向左移动2位后,将移位后的结果在指定比特位与V[62]、V[63]进行按位异或运算后得到。也即能够直接根据输入参数V得到,即得到了与输入参数V的映射关系。Thus, it can be seen from Figure 5 that the present application The hardware circuit implementation is essentially to shift V's 64-bit data V[63]~V[0] to the left by 2 bits, and then perform a bitwise XOR operation on the shifted result with V[62] and V[63] at the specified bit position. It can be obtained directly according to the input parameter V, that is, The mapping relationship with the input parameter V.
同理,基于上述定义,对MULxPOW(V,3,C)=MULx(MULxPOW(V,2,C),C)进行简化时,可以得到: Similarly, based on the above definition, when MULxPOW(V, 3, C) = MULx(MULxPOW(V, 2, C), C) is simplified, we can get:
同样地,可以简写为:Likewise, It can be shortened to:
首先确定的值,具体地:First determine The values of, specifically:
由于C=0x1B,而C的最高位C[63]为0,因此,同样地,可以继续简写为:Since C = 0x1B, and the highest bit C[63] of C is 0, therefore, similarly, It can be further abbreviated as:
其中,可以理解为将左移1位后新的最高比特位的值,即原始最高位移出,新的最高比特位的值为进而可以得到:in, It can be understood as The value of the new highest bit after shifting left by 1 bit, that is, the original highest bit Shift out, the new highest bit value is Then we can get:
由于C=0x1B,而C[62]为0,因此,可以继续简写为:Since C=0x1B, and C[62] is 0, It can be further abbreviated as:
其中,(V<<1)[62]可以理解为将V左移1位后新的次高位的值,即原始最高位V[63]移出,新的最高位的值为V[62],则新的次高位的值为V[61]。进而可以得到, Among them, (V<<1)[62] can be understood as the value of the new second highest bit after V is shifted left by 1 bit, that is, the original highest bit V[63] is shifted out, and the new highest bit value is V[62], then the new second highest bit value is V[61]. Then we can get,
基于此,可以继续简写为:Based on this, It can be further abbreviated as:
同理,由于0x1B的64位的二进制数中左半部分由59个0组成,因此,当与0x1B进行按位异或计算时,左半部分59个0对应的输出,可以直接是的左半部分的59位数值,而对于值为1的比特位,由于与0x1B的异或操作,是在V[61]为1时才进行,因此,在 时,V[61]为1,从而可以将0x1B的64位的二进制数中值为1的比特位,用V[61]代替1。从而,可以继续简写为:Similarly, since the left half of the 64-bit binary number 0x1B consists of 59 zeros, when When the bitwise XOR calculation is performed with 0x1B, the output corresponding to the 59 0s in the left half can be directly The 59-bit value of the left half of the value, and for the bit with value 1, due to The XOR operation with 0x1B is performed only when V[61] is 1. When , V[61] is 1, so the bits with a value of 1 in the 64-bit binary number 0x1B can be replaced by 1 with V[61]. It can be further abbreviated as:
同理,V[61]无论是否为1,都可以直接简写为:Similarly, whether V[61] is 1 or not, Can be directly abbreviated as:
从而可以看出,的结果,可以是通过将移位1位后,将移位后的结果在指定比特位与V[61]进行按位异或运算后得到。由于前述已确定能够直接根据输入参数V得到,而除了外,也只与V[61]有关,因此实质上也能够直接根据输入参数V得到,也即得到了与输入参数V的映射关系。Thus, it can be seen that The result can be obtained by After shifting by 1 bit, the shifted result is obtained by performing a bitwise XOR operation with V[61] at the specified bit position. can be obtained directly from the input parameter V, and Apart from In addition, it is only related to V[61], so In fact, it can also be obtained directly according to the input parameter V, that is, The mapping relationship with the input parameter V.
基于上述分析,在得到前述的计算电路后,也可以实现的计算电路设计。示例性地,请参阅图6,图6示出了一种的按位计算电路示意图。如图6所示,的计算电路包含了大部分的计算电路外,还新增了4个与V[61]的按位异或电路。从图5可以看出,本申请的硬件电路实现,也仅依赖于输入参数V。Based on the above analysis, we can get the above After the calculation circuit, it can also be realized For example, please refer to FIG6 , which shows a calculation circuit design. Schematic diagram of the bit-by-bit calculation circuit. As shown in Figure 6, The calculation circuit includes In addition to most of the calculation circuits, 4 bitwise XOR circuits with V[61] are added. As can be seen from Figure 5, this application The hardware circuit implementation also only depends on the input parameter V.
具体地,M的64位数据M[63]~M[0]对应的是的64位数据向左移动1位后的移位结果,如图6所示的虚线框中所展示的的计算电路向左移动1位后的计算电路,相当于由于M与{0,0,…,0,V[61],V[61],0,V[61],V[61]}中值为0的比特位进行异或时,异或结果仍是对应的M值,因此,可以仅对非0值的比特位进行异或电路的设计。即如图6所示,由于{0,0,…,0,V[61],V[61],0,V[61],V[61]}中仅在比特位为0、1、3、4处为非0值V[61],因此,可以仅在M[0]、M[1]、M[3]、M[4]处增加与V[61]的按位异或电路。Specifically, the 64-bit data M[63] to M[0] of M corresponds to The shift result after the 64-bit data is shifted left by 1 bit is shown in the dotted box in Figure 6. The calculation circuit of the calculation circuit after shifting 1 bit to the left is equivalent to Since when M is XORed with a bit with a value of 0 in {0, 0, ..., 0, V[61], V[61], 0, V[61], V[61]}, the XOR result is still the corresponding M value, it is possible to design XOR circuits only for bits with non-zero values. That is, as shown in FIG6 , since only bits 0, 1, 3, and 4 in {0, 0, ..., 0, V[61], V[61], 0, V[61], V[61]} are non-zero values V[61], it is possible to add bitwise XOR circuits with V[61] only at M[0], M[1], M[3], and M[4].
如此,从图6可以看出,本申请的硬件电路实现,实质上是将V的64位数据V[63]~V[0]向左移动3位后,将移位后的结果在指定比特位与V[61]、V[62]、V[63]进行按位异或运算后得到。也即能够直接根据输入参数V得到,即得到了与输入参数V的映射关系。Thus, it can be seen from Figure 6 that the present application The hardware circuit implementation is essentially to shift V's 64-bit data V[63]~V[0] to the left by 3 bits, and then perform a bitwise XOR operation on the shifted result with V[61], V[62], and V[63] at the specified bit position. It can be obtained directly according to the input parameter V, that is, The mapping relationship with the input parameter V.
以此类推,对MULxPOW(V,60,C)=MULx(MULxPOW(V,59,C),C)进行简化时,可以得到:By analogy, when MULxPOW(V, 60, C) = MULx(MULxPOW(V, 59, C), C) is simplified, we can get:
其中, in,
由于C=0x1B,而C[5]为0,因此,可以继续简写为:because C=0x1B, and C[5] is 0, so, It can be further abbreviated as:
所以, so,
同理,由于0x1B的64位的二进制数中左半部分由59个0组成,因此,当与0x1B进行按位异或计算时,左半部分59个0对应的输出,可以直接是的左半部分的59位数值,而对于值为1的比特位,由于与0x1B的异或操作,是在V[4]为1时才进行,因此,在 时,V[4]为1,从而可以将0x1B的64位的二进制数中值为1的比特位,用V[4]代替1。从而,可以继续简写为:Similarly, since the left half of the 64-bit binary number 0x1B consists of 59 zeros, when When the bitwise XOR calculation is performed with 0x1B, the output corresponding to the 59 0s in the left half can be directly The 59-bit value of the left half of the value, and for the bit with value 1, due to The XOR operation with 0x1B is performed only when V[4] is 1. When , V[4] is 1, so the bits with a value of 1 in the 64-bit binary number 0x1B can be replaced by 1 with V[4]. It can be further abbreviated as:
同理,V[4]无论是否为1,都可以直接简写为:Similarly, whether V[4] is 1 or not, Can be directly abbreviated as:
从而可以看出,的结果,可以是通过将移位1位后,将移位后的结果在指定比特位与V[4]进行按位异或运算后得到。由于按照前述推导,可确定能够直接根据输入参数V得到,而除了外,也只与V[4]有关,因此实质上也能够直接根据输入参数V得到,也即得到了与输入参数V的映射关系。Thus, it can be seen that The result can be obtained by After shifting by 1 bit, the shifted result is obtained by performing a bitwise XOR operation with V[4] at the specified bit position. According to the above derivation, it can be determined that can be obtained directly from the input parameter V, and Apart from In addition, it is only related to V[4], so In fact, it can also be obtained directly according to the input parameter V, that is, The mapping relationship with the input parameter V.
同理,也可以实现的计算电路设计。示例性地,请参阅图7,图7示出了一种的按位计算电路示意图。具体地,M的64位数据M[63]~M[0]对应的是的64位数据向左移动1位后的移位结果,如图7所示的虚线框中所展示的的计算电路向左移动1位后的计算电路,相当于同理由于{0,0,…,0,V[4],V[4],0,V[4],V[4]}中仅在比特位为0、1、3、4处为非0值V[4],因此,可以仅在M[0]、M[1]、M[3]、M[4]处增加与V[4]的按位异或电路。Similarly, it is also possible to achieve For example, please refer to FIG. 7 , which shows a calculation circuit design. Schematic diagram of the bit-by-bit calculation circuit. Specifically, the 64-bit data M[63]~M[0] of M corresponds to The shift result after the 64-bit data is shifted left by 1 bit is shown in the dotted box in Figure 7. The calculation circuit of the calculation circuit after shifting 1 bit to the left is equivalent to Similarly, since the value V[4] is non-zero only at bits 0, 1, 3, and 4 in {0, 0, …, 0, V[4], V[4], 0, V[4], V[4]}, we can add bitwise XOR circuits with V[4] only at M[0], M[1], M[3], and M[4].
同理,从图7可以看出,本申请的硬件电路实现,实质上也是将V的64位数据V[63]~V[0]向左移动60位后,将移位后的结果在指定比特位与V[4]…V[61]、V[62]、V[63]进行按位异或运算后得到。也即能够直接根据输入参数V得到,即得到了与输入参数V的映射关系。Similarly, it can be seen from Figure 7 that this application The hardware circuit implementation is actually to shift V's 64-bit data V[63]~V[0] to the left by 60 bits, and then perform a bitwise XOR operation on the shifted result with V[4]…V[61], V[62], and V[63] at the specified bit position. It can be obtained directly according to the input parameter V, that is, The mapping relationship with the input parameter V.
需要说明的是,由于而基于前述分析,可以看出它的计算最终依赖于C[5]=0,从而才可以继续简写为:从而 It should be noted that due to Based on the above analysis, It can be seen that its calculation ultimately depends on C[5]=0, so It can be abbreviated as: thereby
由于C[5]是参数C中左边59个0中最靠右的一个0对应的位置,即C[4]的值已经为1。因此,是最后一个可以通过上述规律计算出的嵌套函数。Since C[5] is the position corresponding to the rightmost 0 among the 59 0s on the left side of parameter C, the value of C[4] is already 1. Therefore, is the last nested function that can be calculated using the above rules.
基于上述各自与输入参数V的映射关系,发明人经过研究进一步发现,每次与移位后的结果进行异或的V值为输入参数V左移时移出的值,每个异或的V值,均与参数C=0x1B的64位的二进制数中值为1所在的比特位0、1、3、4对应。Based on the above The inventors further discovered through research that the mapping relationship between each of them and the input parameter V is that the V value that is XORed with the shifted result each time is the value shifted out when the input parameter V is shifted left, and each XORed V value corresponds to the bits 0, 1, 3, and 4 where the value is 1 in the 64-bit binary number of parameter C=0x1B.
具体地,基于前述分析并结合图4~图7可以看出:Specifically, based on the above analysis and in combination with Figures 4 to 7, it can be seen that:
进而,发明人经过研究发现,对于的结果,可以是将输入参数V左移i位后,将V移位后的结果M中的M[0+j]、M[1+j]、M[3+j]、M[4+j]与V[N-i+j]进行按位异或运算得到。其中,j为0~i-1之间的整数。其中,N为V参数的位数64,M[0+j]、M[1+j]、M[3+j]、M[4+j]中涉及到的0、1、3、4为参数C=0x1B的N位的二进制数中值为1所在的比特位。从而得到了输入V和函数输出的映射关系的确定方式。并基于此,发明人提出了一种数据处理方法、电路、芯片、电子设备及存储介质,以基于参数C为常量且其大部分比特为0的特性,来确定输入V和函数输出的映射关系。Furthermore, the inventors have found through research that The result can be obtained by shifting the input parameter V left by i bits, and then performing a bitwise XOR operation on M[0+j], M[1+j], M[3+j], M[4+j] in the result M after V is shifted, and V[N-i+j]. Wherein, j is an integer between 0 and i-1. Wherein, N is the number of bits of the V parameter, 64, and 0, 1, 3, and 4 involved in M[0+j], M[1+j], M[3+j], and M[4+j] are the bits where the value is 1 in the N-bit binary number of the parameter C=0x1B. Thus, a method for determining the mapping relationship between the input V and the function output is obtained. Based on this, the inventor proposes a data processing method, circuit, chip, electronic device, and storage medium to determine the mapping relationship between the input V and the function output based on the characteristic that the parameter C is a constant and most of its bits are 0.
因此,对于相关技术中需要先计算上一个i的输出后才能计算下一个i的输出的MULxPOW(V,i,C)函数,可以直接根据输入参数V计算得到,无需依赖上一级i的输出,从而可以改变相关技术中的串行计算方式,而是采用并行计算方式,使得可以在一个时钟周期里同时计算出MULxPOW(V,i,C)每个i对应的输出,提高了系统计算的吞吐量。Therefore, for the MULxPOW(V, i, C) function in the related art that needs to calculate the output of the previous i before calculating the output of the next i, it can be calculated directly according to the input parameter V without relying on the output of the previous level i, thereby changing the serial calculation method in the related art and adopting a parallel calculation method, so that the output corresponding to each i of MULxPOW(V, i, C) can be calculated simultaneously in one clock cycle, thereby improving the system calculation throughput.
请参阅图8,图8示出了本申请一个实施例提供的数据处理方法的流程示意图。在具体的实施例中,该数据处理方法可应用于如图13所示的数据处理装置800以及配置有所述数据处理装置800的电子设备(图15)。下面将针对图8所示的流程进行详细的阐述,所示数据处理方法具体可以包括以下步骤:Please refer to FIG8 , which shows a schematic flow chart of a data processing method provided by an embodiment of the present application. In a specific embodiment, the data processing method can be applied to a data processing device 800 as shown in FIG13 and an electronic device ( FIG15 ) equipped with the data processing device 800. The process shown in FIG8 will be described in detail below. The data processing method shown can specifically include the following steps:
步骤S110:确定第一数据序列左移i位后得到的第二数据序列。Step S110: Determine a second data sequence obtained by shifting the first data sequence left by i bits.
基于前述推理,可以知道,对于的结果,需要先将参数V左移i位后,将V移位后的结果M中的M[0+j]、M[1+j]、M[3+j]、M[4+j]与V[64-i+j]进行按位异或运算得到。因此,本申请在确定参数V和函数输出的映射关系时,需要先确定确定第一数据序列左移i位后得到的第二数据序列。Based on the above reasoning, we can know that for The result is obtained by first shifting the parameter V left by i bits, and then performing a bitwise XOR operation on M[0+j], M[1+j], M[3+j], M[4+j] and V[64-i+j]. Therefore, in determining the parameters V and When determining the mapping relationship of the function output, it is necessary to first determine the second data sequence obtained by shifting the first data sequence left by i bits.
其中,所述第一数据序列为MULxPOW(V,i,C)函数中参数V的N位二进制序列V[0]~V[N-1],所述第二数据序列为所述N位二进制序列V[0]~V[N-1]移位后得到的新的N位二进制序列M[0]~M[N-1],所述i为0~N-1之间的整数。Among them, the first data sequence is the N-bit binary sequence V[0]~V[N-1] of the parameter V in the MULxPOW(V, i, C) function, and the second data sequence is the new N-bit binary sequence M[0]~M[N-1] obtained by shifting the N-bit binary sequence V[0]~V[N-1], and i is an integer between 0 and N-1.
在一些实施例中,参数V可是以二进制数表示的值,也可以是以其他进制数表示的值,当参数V以其他进制数表示时(如十六进制),可以将其转换为N位的二进制序列,从而得到上述第一数据序列。作为一种具体实施方式,N可以是64,可以基于参数V,得到64位的二进制序列,从而第一数据序列可以是64位的以二进制值0或1分布的二进制序列V[0]~V[63]。然后可以将第一数据序列V[0]~V[63]左移i位后,得到的新的64位二进制序列M[0]~M[63],作为第二数据序列。In some embodiments, the parameter V may be a value represented by a binary number or a value represented by other bases. When the parameter V is represented by other bases (such as hexadecimal), it may be converted into an N-bit binary sequence to obtain the above-mentioned first data sequence. As a specific implementation, N may be 64, and a 64-bit binary sequence may be obtained based on the parameter V, so that the first data sequence may be a 64-bit binary sequence V[0] to V[63] distributed with binary values 0 or 1. Then, the first data sequence V[0] to V[63] may be shifted left by i bits to obtain a new 64-bit binary sequence M[0] to M[63] as the second data sequence.
步骤S120:当1≤i≤N-Z时,将所述第一数据序列中的第一数据V[N-i+j]与所述第二数据序列中的第二数据M[k+j]进行异或运算,得到所述第二数据M[k+j]对应的异或结果。Step S120: When 1≤i≤N-Z, perform an XOR operation on the first data V[N-i+j] in the first data sequence and the second data M[k+j] in the second data sequence to obtain an XOR result corresponding to the second data M[k+j].
其中,所述j为0~i-1之间的整数,所述k为所述MULxPOW(V,i,C)函数中参数C的N位二进制序列中二进制1值所在的比特位,所述k的个数为至少一个,所述Z为所述k的最高比特位。Among them, j is an integer between 0 and i-1, k is the bit where the binary 1 value is located in the N-bit binary sequence of parameter C in the MULxPOW(V, i, C) function, the number of k is at least one, and Z is the highest bit of k.
基于前述推理,可以知道,对于的结果,在将参数V左移i位后,需要将V移位后的结果M中的M[0+j]、M[1+j]、M[3+j]、M[4+j]与V[N-i+j]进行按位异或运算得到。且M[0+j]、M[1+j]、M[3+j]、M[4+j]中涉及到的0、1、3、4为参数C=0x1B的N位的二进制数中值为1所在的比特位。因此,本申请在确定第一数据序列左移i位后得到的第二数据序列后,可以确定MULxPOW(V,i,C)函数中参数C的N位二进制序列中二进制1值所在的比特位,以根据该比特位确定第二数据序列中待进行按位异或的M值。其中,MULxPOW(V,i,C)函数中的参数C为常量。Based on the above reasoning, we can know that As a result, after the parameter V is shifted left by i bits, it is necessary to perform a bitwise XOR operation on M[0+j], M[1+j], M[3+j], M[4+j] in the result M after V is shifted. And 0, 1, 3, 4 involved in M[0+j], M[1+j], M[3+j], M[4+j] are the bits where the value of the N-bit binary number of the parameter C=0x1B is 1. Therefore, after determining the second data sequence obtained after the first data sequence is shifted left by i bits, the present application can determine the bit where the binary 1 value is located in the N-bit binary sequence of the parameter C in the MULxPOW(V, i, C) function, so as to determine the M value to be bitwise XORed in the second data sequence according to the bit. Among them, the parameter C in the MULxPOW(V, i, C) function is a constant.
在一些实施例中,MULxPOW(V,i,C)函数中参数C可是以二进制数表示的值,从而可以直接根据参数C,确定其N位二进制序列中二进制1值所在的比特位k。参数C也可以是以其他进制数表示的值,当参数C以其他进制数表示时(如十六进制),可以将其转换为N位的二进制序列后,再确定该N位二进制序列中二进制1值所在的比特位k。其中,k的个数为至少一个。In some embodiments, the parameter C in the MULxPOW(V, i, C) function may be a value represented by a binary number, so that the bit k where the binary 1 value is located in the N-bit binary sequence can be directly determined based on the parameter C. The parameter C may also be a value represented by other bases. When the parameter C is represented by other bases (such as hexadecimal), it can be converted into an N-bit binary sequence, and then the bit k where the binary 1 value is located in the N-bit binary sequence can be determined. The number of k is at least one.
需要说明的是,基于前述分析,之所以是最后一个可以通过前述规律计算出的嵌套函数,是因为C[5]是参数C=0x1B中左边59个0中最靠右的一个0对应的位置,即C[4]的值已经为1。因此,在本申请实施例中,可以先确定MULxPOW(V,i,C)函数中参数C的N位二进制序列中二进制1值所在的最高比特位Z,从而可以确定通过前述规律所实现的最大嵌套函数MULxPOW(V,i,C)即其中,i=N-Z。在一些实施例中,由于已经确定参数C的N位二进制序列中二进制1值所在的比特位k,因此,可以直接从比特位k中确定最高比特位Z,从而可以确定通过前述规律所实现的最大嵌套函数MULxPOW(V,i,C)即其中,i=N-Z。也就是说,当1≤i≤N-Z时,可以按照前述规律,将所述第一数据序列中的第一数据V[N-i+j]与所述第二数据序列中的第二数据M[k+j]进行异或运算,得到所述第二数据M[k+j]对应的异或结果。It should be noted that based on the above analysis, The reason why it is the last nested function that can be calculated by the above rules is that C[5] is the position corresponding to the rightmost 0 among the 59 0s on the left of parameter C=0x1B, that is, the value of C[4] is already 1. Therefore, in the embodiment of the present application, the highest bit Z of the binary 1 value in the N-bit binary sequence of parameter C in the MULxPOW(V, i, C) function can be determined first, so as to determine the maximum nested function MULxPOW(V, i, C) implemented by the above rules, that is, In some embodiments, since the bit k where the binary 1 value is located in the N-bit binary sequence of the parameter C has been determined, the highest bit Z can be directly determined from the bit k, so that the maximum nested function MULxPOW(V, i, C) implemented by the above rule can be determined, that is, That is, when 1≤i≤NZ, the first data V[N-i+j] in the first data sequence and the second data M[k+j] in the second data sequence can be XORed according to the above rule to obtain the XOR result corresponding to the second data M[k+j].
作为一种具体实施方式,N可以是64,参数C可以是常量0x1B,由于0x1B的64位的二进制数为0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00000001 1011,因此,可以确定其中二进制1值所在的比特位为第0比特位、第1比特位、第3比特位、第4比特位。也即上述比特位k为0、1、3、4。其中,最高比特位Z为4。从而当1≤i≤N-Z时,上述将所述第一数据序列中的第一数据V[N-i+j]与所述第二数据序列中的第二数据M[k+j]进行异或运算,得到所述第二数据M[k+j]对应的异或结果,可以是当1≤i≤60时,将所述第一数据序列中的第一数据V[N-i+j]与所述第二数据序列中的第二数据M[0+j]、M[1+j]、M[3+j]、M[4+j]进行异或运算,得到所述第二数据M[0+j]、M[1+j]、M[3+j]、M[4+j]各自对应的异或结果。As a specific implementation, N may be 64, and parameter C may be a constant 0x1B. Since the 64-bit binary number of 0x1B is 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00000001 1011, it can be determined that the bits where the binary 1 value is located are the 0th bit, the 1st bit, the 3rd bit, and the 4th bit. That is, the bit k is 0, 1, 3, and 4. Among them, the highest bit Z is 4. Thus, when 1≤i≤N-Z, the above-mentioned XOR operation is performed on the first data V[N-i+j] in the first data sequence and the second data M[k+j] in the second data sequence to obtain the XOR result corresponding to the second data M[k+j]. It can be that when 1≤i≤60, the first data V[N-i+j] in the first data sequence and the second data M[0+j], M[1+j], M[3+j], M[4+j] in the second data sequence are XORed to obtain the XOR results corresponding to the second data M[0+j], M[1+j], M[3+j], M[4+j] respectively.
步骤S130:根据所述第二数据M[k+j]对应的异或结果,对所述第二数据序列中的所述第二数据M[k+j]进行对应更新,得到N位的第三数据序列作为第i输出结果。Step S130: According to the XOR result corresponding to the second data M[k+j], the second data M[k+j] in the second data sequence is correspondingly updated to obtain an N-bit third data sequence as the i-th output result.
其中,所述第i输出结果用于表征所述MULxPOW(V,i,C)函数即函数的输出结果。Among them, the i-th output result is used to characterize the MULxPOW (V, i, C) function, that is, The output of the function.
可以理解的是,由于第二数据序列中的第二数据M[k+j]需要与第一数据V[N-i+j]进行异或运算,因此,可以获取每个第二数据与第一数据异或运算后的最终异或结果,并与第二数据序列中的其他未参与异或运算的数据重新拼接,得到新的N位的第三数据序列,该结果即为MULxPOW(V,i,C)函数即函数的输出结果。从而MULxPOW(V,i,C)函数可以仅根据输入参数V计算得到,无需依赖上一级i的输出。It can be understood that, since the second data M[k+j] in the second data sequence needs to be XORed with the first data V[N-i+j], the final XOR result after the XOR operation of each second data with the first data can be obtained, and re-joined with other data in the second data sequence that do not participate in the XOR operation to obtain a new N-bit third data sequence, and the result is the MULxPOW(V, i, C) function, that is, The output result of the function. Therefore, the MULxPOW(V, i, C) function can be calculated only based on the input parameter V, without relying on the output of the previous level i.
步骤S140:基于所述第i输出结果,生成信息认证码,所述信息认证码用于校验信息的完整性。Step S140: Generate an information authentication code based on the i-th output result, where the information authentication code is used to verify the integrity of the information.
在本申请实施例中,在得到MULxPOW(V,i,C)函数的第i输出结果后,可以根据MULxPOW函数的各个第i输出结果,生成信息认证码,所述信息认证码用于校验信息的完整性。In an embodiment of the present application, after obtaining the i-th output result of the MULxPOW(V, i, C) function, an information authentication code can be generated according to each i-th output result of the MULxPOW function, and the information authentication code is used to verify the integrity of the information.
在一些实施例中,当信息认证码是根据UIA2完整性保护算法生成时,可以是具体将MULxPOW函数的各个第i输出结果带入到MUL(V,P,C)函数中,以基于MUL(V,P,C)函数,确定EVAL值,然后基于EVAL值,生成信息认证码MAC。例如,前述UIA2完整性保护算法计算消息认证码MAC的过程中的第十步~第十二步。In some embodiments, when the message authentication code is generated according to the UIA2 integrity protection algorithm, each i-th output result of the MULxPOW function may be specifically brought into the MUL(V, P, C) function to determine the EVAL value based on the MUL(V, P, C) function, and then generate the message authentication code MAC based on the EVAL value. For example, the tenth to twelfth steps in the process of calculating the message authentication code MAC by the aforementioned UIA2 integrity protection algorithm.
可以理解的是,V,P,C均为N位(如64位)的数据时,根据前述MUL(V,P,C)函数展开后伪代码,可以看出需要计算MULxPOW(V,i,C),i分别取0~N-1(如0~63)之间的整数时各自对应的结果。而相关技术由于是串行计算方式,即需要先计算上一个i的输出后才能计算下一个i的输出,导致需要比较多的时钟周期来计算,降低了系统计算的吞吐量。因此,在本申请实施例中,对于MULxPOW(V,i,C)中1≤i≤N-Z的每个i对应的输出,可以直接根据输入参数V计算得到,无需依赖上一级i的输出,从而可以改变相关技术中的串行计算方式,而是采用并行计算方式,使得可以在一个时钟周期里同时计算出MULxPOW(V,i,C)中1≤i≤N-Z的每个i对应的输出,提高了系统计算的吞吐量。It can be understood that when V, P, and C are all N-bit (such as 64-bit) data, according to the pseudo code after the aforementioned MUL (V, P, C) function is expanded, it can be seen that it is necessary to calculate MULxPOW (V, i, C), and the corresponding results when i is an integer between 0 and N-1 (such as 0 to 63). However, since the related art is a serial calculation method, that is, it is necessary to calculate the output of the previous i before calculating the output of the next i, it requires more clock cycles to calculate, which reduces the throughput of the system calculation. Therefore, in the embodiment of the present application, the output corresponding to each i of 1≤i≤N-Z in MULxPOW (V, i, C) can be directly calculated according to the input parameter V, without relying on the output of the previous i, so that the serial calculation method in the related art can be changed, and a parallel calculation method is adopted, so that the output corresponding to each i of 1≤i≤N-Z in MULxPOW (V, i, C) can be calculated simultaneously in one clock cycle, thereby improving the throughput of the system calculation.
在一些实施例中,由于MULxPOW(V,0,C)的输出结果直接就是参数V,因此,对于i=0的情况下,MULxPOW(V,0,C)实质上也能仅根据参数V直接计算得到。从而对应0≤i≤N-Z时,MULxPOW(V,i,C)的硬件电路实现可以是并行计算的方式,而当i>N-Z时,可以采用原有的串行计算方式。具体地,可以直接根据第i=N-Z输出结果,采用相关技术中的串行计算方式,计算下一级的第i=N-Z+1输出结果,然后依次计算到第i=N-1输出结果。从而实现将相关技术中的整体串行计算方式改进为局部串行计算,其余都采用并行计算方式,进而提高了消息认证码MAC计算的硬件电路的速度的同时,也提高了时钟频率、满足吞吐量的需求。In some embodiments, since the output result of MULxPOW (V, 0, C) is directly the parameter V, for the case of i = 0, MULxPOW (V, 0, C) can actually be directly calculated based on the parameter V alone. Therefore, when 0≤i≤N-Z, the hardware circuit implementation of MULxPOW (V, i, C) can be a parallel calculation method, and when i>N-Z, the original serial calculation method can be used. Specifically, the i=N-Z+1 output result of the next level can be calculated directly based on the i=N-Z output result, and then the i=N-1 output result can be calculated in sequence. Thereby, the overall serial calculation method in the related technology is improved to a local serial calculation, and the rest are all parallel calculation methods, thereby improving the speed of the hardware circuit of the message authentication code MAC calculation while also improving the clock frequency and meeting the throughput requirements.
本申请实施例提供的数据处理方法,通过确定第一数据序列左移i位后得到的第二数据序列,其中,第一数据序列为MULxPOW(V,i,C)函数中参数V的N位二进制序列V[0]~V[N-1],第二数据序列为N位二进制序列V[0]~V[N-1]移位后得到的新的N位二进制序列M[0]~M[N-1],i为0~N-1之间的整数,以在1≤i≤N-Z时,将第一数据序列中的第一数据V[N-i+j]与第二数据序列中的第二数据M[k+j]进行异或运算,得到第二数据M[k+j]对应的异或结果,其中,j为0~i-1之间的整数,k为MULxPOW(V,i,C)函数中参数C的N位二进制序列中二进制1值所在的比特位,k的个数为至少一个,Z为所述k的最高比特位,从而根据第二数据M[k+j]对应的异或结果,对第二数据序列中的第二数据M[k+j]进行对应更新,得到N位的第三数据序列作为第i输出结果,该第i输出结果用于表征MULxPOW(V,i,C)函数的输出结果,然而基于第i输出结果,生成信息认证码,所述信息认证码用于校验信息的完整性。由此,本申请中MULxPOW(V,i,C)函数的每一级的计算可以只依赖于输入V,无需依赖上一级的输出,使得可以将原有的MULxPOW(V,i,C)函数的串行计算方式,改变为并行计算方式,提高了消息认证码MAC计算的硬件电路的速度的同时,也提高了时钟频率、满足吞吐量的需求。The data processing method provided by the embodiment of the present application determines a second data sequence obtained by shifting a first data sequence left by i bits, wherein the first data sequence is an N-bit binary sequence V[0] to V[N-1] of the parameter V in the MULxPOW(V, i, C) function, and the second data sequence is a new N-bit binary sequence M[0] to M[N-1] obtained by shifting the N-bit binary sequence V[0] to V[N-1], i is an integer between 0 and N-1, so that when 1≤i≤N-Z, the first data V[N-i+j] in the first data sequence and the second data M[k+j] in the second data sequence are XORed to obtain the second data M[k+j] The corresponding XOR result, wherein j is an integer between 0 and i-1, k is the bit where the binary 1 value is located in the N-bit binary sequence of the parameter C in the MULxPOW (V, i, C) function, the number of k is at least one, and Z is the highest bit of the k, so that according to the XOR result corresponding to the second data M[k+j], the second data M[k+j] in the second data sequence is correspondingly updated to obtain the N-bit third data sequence as the i-th output result, and the i-th output result is used to characterize the output result of the MULxPOW (V, i, C) function, but based on the i-th output result, an information authentication code is generated, and the information authentication code is used to verify the integrity of the information. Therefore, the calculation of each level of the MULxPOW (V, i, C) function in the present application can only rely on the input V, without relying on the output of the previous level, so that the original serial calculation method of the MULxPOW (V, i, C) function can be changed to a parallel calculation method, which improves the speed of the hardware circuit of the message authentication code MAC calculation while also improving the clock frequency and meeting the throughput requirements.
请参阅图9,图9示出了本申请另一个实施例提供的数据处理方法的流程示意图。下面将针对图9所示的流程进行详细的阐述,具体是对前述实施例中的N和C进行限定:所述N=64,所述i为0~63之间的整数,所述参数C=0x0000 0000 0000 001B。所示数据处理方法具体可以包括以下步骤:Please refer to FIG9 , which shows a flow chart of a data processing method provided by another embodiment of the present application. The following will describe the flow chart shown in FIG9 in detail, specifically defining N and C in the aforementioned embodiment: N=64, i is an integer between 0 and 63, and parameter C=0x0000 0000 0000 001B. The data processing method shown may specifically include the following steps:
步骤S210:确定第一数据序列左移i位后得到的第二数据序列。Step S210: Determine a second data sequence obtained by shifting the first data sequence left by i bits.
在本申请实施例中,步骤S210可以参阅前述实施例的描述,此处不再赘述。In the embodiment of the present application, step S210 can refer to the description of the aforementioned embodiment and will not be repeated here.
步骤S220:当1≤i≤60时,将所述第一数据序列中的第一数据V[N-i+j]与所述第二数据序列中的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j]进行异或运算,得到所述第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j]各自对应的异或结果。Step S220: When 1≤i≤60, perform an XOR operation on the first data V[N-i+j] in the first data sequence and the second data M[j], second data M[1+j], second data M[3+j], and second data M[4+j] in the second data sequence to obtain the XOR results corresponding to the second data M[j], second data M[1+j], second data M[3+j], and second data M[4+j] respectively.
可以理解的是,当N为64,参数C为常量0x1B时,由于0x1B的64位的二进制数为00000000 00000000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1011,因此,前述的二进制1值所在的比特位k为0、1、3、4。其中,最高比特位Z为4。从而第二数据序列中的需要进行异或运算的第二数据M[k+j]为第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j]。It can be understood that when N is 64 and the parameter C is the constant 0x1B, since the 64-bit binary number of 0x1B is 00000000 00000000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1011, the bit k where the aforementioned binary 1 value is located is 0, 1, 3, and 4. Among them, the highest bit Z is 4. Therefore, the second data M[k+j] that need to be XOR-operated in the second data sequence are the second data M[j], the second data M[1+j], the second data M[3+j], and the second data M[4+j].
在一些实施例中,当i=1时,j=0,此时相当于获取MULxPOW(V,1,C)函数即的输出结果,从而第一数据序列中需要进行异或运算的第一数据V[N-i+j]只有一个,即第一数据V[63],第二数据序列中的需要进行异或运算的第二数据M[k+j]为第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4]。此时,步骤S220可以具体包括:In some embodiments, when i=1, j=0, this is equivalent to obtaining the MULxPOW(V, 1, C) function, that is, The output result of , so that there is only one first data V[N-i+j] that needs to be XOR-operated in the first data sequence, that is, the first data V[63], and the second data M[k+j] that need to be XOR-operated in the second data sequence are the second data M[0], the second data M[1], the second data M[3], and the second data M[4]. At this time, step S220 may specifically include:
将所述第一数据V[63]分别与所述第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4]进行异或运算,得到所述第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4]各自对应的异或结果。Perform XOR operations on the first data V[63] and the second data M[0], second data M[1], second data M[3], and second data M[4] respectively to obtain XOR results corresponding to the second data M[0], second data M[1], second data M[3], and second data M[4] respectively.
在一些实施例中,第一数据序列中需要进行异或运算的第一数据V[N-i+j]可以为多个,此时,步骤S220可以具体包括:In some embodiments, there may be multiple first data V[N-i+j] to be XOR-operated in the first data sequence. In this case, step S220 may specifically include:
根据每个所述第一数据V[N-i+j]对应的所述第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j],将同一第二数据对应的所有第一数据与所述同一第二数据进行异或运算,得到每个第二数据对应的异或结果。According to the second data M[j], second data M[1+j], second data M[3+j], and second data M[4+j] corresponding to each of the first data V[N-i+j], all first data corresponding to the same second data are XOR-ed with the same second data to obtain the XOR result corresponding to each second data.
可以理解的是,由于每个所述第一数据V[N-i+j],都有其需要对应异或运算的所述第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j],而不同第一数据可能会与相同的第二数据进行异或运算,因此,可以先根据每个所述第一数据V[N-i+j]对应的所述第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j],确定与同一第二数据进行异或运算的所有第一数据,从而可以将同一第二数据对应的所有第一数据与所述同一第二数据进行多项的异或运算,得到每个第二数据对应的异或结果。It can be understood that, since each of the first data V[N-i+j] has its corresponding second data M[j], second data M[1+j], second data M[3+j], second data M[4+j] that needs to be XOR-operated, and different first data may be XOR-operated with the same second data, therefore, all the first data that are XOR-operated with the same second data can be determined based on the second data M[j], second data M[1+j], second data M[3+j], second data M[4+j] corresponding to each of the first data V[N-i+j], so that all the first data corresponding to the same second data can be XOR-operated with the same second data for multiple times to obtain the XOR results corresponding to each second data.
作为一种实施方式,当i=2时,j为0~1之间的整数,此时相当于获取MULxPOW(V,2,C)函数即的输出结果,从而第一数据序列中需要进行异或运算的第一数据V[N-i+j]包括第一数据V[62]、第一数据V[63],第二数据序列中的需要进行异或运算的所述第二数据M[k+j]包括与所述第一数据V[62]对应的第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4],以及与所述第一数据V[63]对应的第二数据M[1]、第二数据M[2]、第二数据M[4]、第二数据M[5]。As an implementation method, when i=2, j is an integer between 0 and 1, which is equivalent to obtaining the MULxPOW(V, 2, C) function, that is, The output result of , so that the first data V[N-i+j] that needs to be XOR-operated in the first data sequence includes the first data V[62] and the first data V[63], and the second data M[k+j] that needs to be XOR-operated in the second data sequence includes the second data M[0], second data M[1], second data M[3], second data M[4] corresponding to the first data V[62], and the second data M[1], second data M[2], second data M[4], second data M[5] corresponding to the first data V[63].
可以看出,与第二数据M[0]进行异或的第一数据仅有V[62],与第二数据M[1]进行异或的第一数据有V[62]和V[63],与第二数据M[2]进行异或的第一数据仅有V[63],与第二数据M[3]进行异或的第一数据仅有V[62],与第二数据M[4]进行异或的第一数据有V[62]和V[63],与第二数据M[5]进行异或的第一数据仅有V[63],因此结合图5,步骤S220可以具体包括:It can be seen that the first data XORed with the second data M[0] only has V[62], the first data XORed with the second data M[1] has V[62] and V[63], the first data XORed with the second data M[2] has only V[63], the first data XORed with the second data M[3] has only V[62], the first data XORed with the second data M[4] has V[62] and V[63], and the first data XORed with the second data M[5] has only V[63]. Therefore, in conjunction with FIG. 5, step S220 may specifically include:
将所述第二数据M[0]对应的所述第一数据V[62],与所述第二数据M[0]进行异或运算,得到所述第二数据M[0]对应的异或结果;Perform an XOR operation on the first data V[62] corresponding to the second data M[0] and the second data M[0] to obtain an XOR result corresponding to the second data M[0];
将所述第二数据M[1]对应的所述第一数据V[62]和所述第一数据V[63],与所述第二数据M[1]进行异或运算,得到所述第二数据M[1]对应的异或结果;Perform an XOR operation on the first data V[62] and the first data V[63] corresponding to the second data M[1] and the second data M[1] to obtain an XOR result corresponding to the second data M[1];
将所述第二数据M[2]对应的所述第一数据V[63],与所述第二数据M[2]进行异或运算,得到所述第二数据M[2]对应的异或结果;Perform an XOR operation on the first data V[63] corresponding to the second data M[2] and the second data M[2] to obtain an XOR result corresponding to the second data M[2];
将所述第二数据M[3]对应的所述第一数据V[62],与所述第二数据M[3]进行异或运算,得到所述第二数据M[3]对应的异或结果;Perform an XOR operation on the first data V[62] corresponding to the second data M[3] and the second data M[3] to obtain an XOR result corresponding to the second data M[3];
将所述第二数据M[4]对应的所述第一数据V[62]和所述第一数据V[63],与所述第二数据M[4]进行异或运算,得到所述第二数据M[4]对应的异或结果;Perform an XOR operation on the first data V[62] and the first data V[63] corresponding to the second data M[4] and the second data M[4] to obtain an XOR result corresponding to the second data M[4];
将所述第二数据M[5]对应的所述第一数据V[63],与所述第二数据M[5]进行异或运算,得到所述第二数据M[5]对应的异或结果。An XOR operation is performed on the first data V[63] corresponding to the second data M[5] and the second data M[5] to obtain an XOR result corresponding to the second data M[5].
步骤S230:根据所述第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j]各自对应的异或结果,对所述第二数据序列中的所述第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j]进行对应更新,得到64位的第三数据序列作为第i输出结果。Step S230: According to the XOR results corresponding to the second data M[j], the second data M[1+j], the second data M[3+j], and the second data M[4+j], the second data M[j], the second data M[1+j], the second data M[3+j], and the second data M[4+j] in the second data sequence are correspondingly updated to obtain a 64-bit third data sequence as the i-th output result.
所述第i输出结果用于表征所述MULxPOW(V,i,C)函数的输出结果。The i-th output result is used to characterize the output result of the MULxPOW(V, i, C) function.
可以理解的是,当N为64,参数C为常量0x1B时,由于第二数据序列中的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j]需要与第一数据V[N-i+j]进行异或运算,因此,可以获取每个第二数据与第一数据异或运算后的最终异或结果,并与第二数据序列中的其他未参与异或运算的数据重新拼接,得到新的N位的第三数据序列,该结果即为MULxPOW(V,i,C)函数即函数的输出结果。从而MULxPOW(V,i,C)函数可以仅根据输入参数V计算得到,无需依赖上一级i的输出。It can be understood that when N is 64 and the parameter C is the constant 0x1B, since the second data M[j], the second data M[1+j], the second data M[3+j], and the second data M[4+j] in the second data sequence need to be XORed with the first data V[N-i+j], the final XOR result after the XOR operation of each second data with the first data can be obtained, and re-spliced with other data in the second data sequence that do not participate in the XOR operation to obtain a new N-bit third data sequence, and the result is the MULxPOW(V, i, C) function, that is, The output result of the function. Therefore, the MULxPOW(V, i, C) function can be calculated only based on the input parameter V, without relying on the output of the previous level i.
步骤S240:基于所述第i输出结果,生成信息认证码,所述信息认证码用于校验信息的完整性。Step S240: Generate an information authentication code based on the i-th output result, where the information authentication code is used to verify the integrity of the information.
可以理解的是,V,P,C均为64位的数据时,根据前述MUL(V,P,C)函数展开后伪代码,可以看出需要计算MULxPOW(V,i,C),i分别取0~63之间的整数时各自对应的结果。而相关技术由于是串行计算方式,即需要先计算上一个i的输出后才能计算下一个i的输出,导致需要比较多的时钟周期来计算,降低了系统计算的吞吐量。因此,在本申请实施例中,对于MULxPOW(V,i,C)中1≤i≤60的每个i对应的输出,可以直接根据输入参数V计算得到,无需依赖上一级i的输出,从而可以改变相关技术中的串行计算方式,而是采用并行计算方式,使得可以在一个时钟周期里同时计算出MULxPOW(V,i,C)中1≤i≤60的每个i对应的输出,提高了系统计算的吞吐量。It can be understood that when V, P, and C are all 64-bit data, according to the pseudo code after the aforementioned MUL(V, P, C) function is expanded, it can be seen that it is necessary to calculate MULxPOW(V, i, C), and the corresponding results when i is an integer between 0 and 63. However, since the related art is a serial calculation method, that is, it is necessary to calculate the output of the previous i before calculating the output of the next i, it requires more clock cycles to calculate, which reduces the throughput of the system calculation. Therefore, in an embodiment of the present application, the output corresponding to each i of 1≤i≤60 in MULxPOW(V, i, C) can be directly calculated according to the input parameter V, without relying on the output of the previous i, so that the serial calculation method in the related art can be changed, and a parallel calculation method is adopted, so that the output corresponding to each i of 1≤i≤60 in MULxPOW(V, i, C) can be calculated simultaneously in one clock cycle, thereby improving the throughput of the system calculation.
在一些实施例中,由于MULxPOW(V,0,C)的输出结果直接就是参数V,因此,对于i=0的情况下,MULxPOW(V,0,C)实质上也能仅根据参数V直接计算得到。从而对应0≤i≤60时,MULxPOW(V,i,C)的硬件电路实现可以是并行计算的方式,而当i>60时,可以采用原有的串行计算方式。具体地,可以直接根据第i=60输出结果,采用相关技术中的串行计算方式,计算下一级的第i=61输出结果,然后依次计算到第i=63输出结果。从而实现将相关技术中的整体串行计算方式改进为局部串行计算,其余都采用并行计算方式,进而提高了消息认证码MAC计算的硬件电路的速度的同时,也提高了时钟频率、满足吞吐量的需求。In some embodiments, since the output result of MULxPOW (V, 0, C) is directly the parameter V, for the case of i=0, MULxPOW (V, 0, C) can actually be directly calculated based on the parameter V alone. Therefore, when 0≤i≤60, the hardware circuit implementation of MULxPOW (V, i, C) can be a parallel calculation method, and when i>60, the original serial calculation method can be used. Specifically, the i=61 output result of the next level can be calculated directly based on the i=60 output result, and then the i=63 output result can be calculated in sequence. Thereby, the overall serial calculation method in the related technology is improved to a local serial calculation, and the rest are all calculated in parallel, thereby improving the speed of the hardware circuit of the message authentication code MAC calculation while also improving the clock frequency and meeting the throughput requirements.
本申请实施例提供的数据处理方法,N=64,MULxPOW(V,i,C)函数中参数C=0x0000 00000000 001B,k为0、1、3、4,Z为4,从而可以通过确定第一数据序列左移i位后得到的第二数据序列,其中,第一数据序列为MULxPOW(V,i,C)函数中参数V的64位二进制序列V[0]~V[63],第二数据序列为64位二进制序列V[0]~V[63]移位后得到的新的64位二进制序列M[0]~M[63],i为0~63之间的整数,以在1≤i≤60时,将第一数据序列中的第一数据V[64-i+j]与第二数据序列中的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j]进行异或运算,得到第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j]各自对应的异或结果,其中,j为0~i-1之间的整数,从而根据第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j]各自对应的异或结果,对第二数据序列中的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j]进行对应更新,得到64位的第三数据序列作为第i输出结果,该第i输出结果用于表征MULxPOW(V,i,C)函数的输出结果,然而基于第i输出结果,生成信息认证码,所述信息认证码用于校验信息的完整性。由此,本申请中MULxPOW(V,i,C)函数的每一级的计算可以只依赖于输入V,无需依赖上一级的输出,使得可以将原有的MULxPOW(V,i,C)函数的串行计算方式,改变为并行计算方式,提高了消息认证码MAC计算的硬件电路的速度的同时,也提高了时钟频率、满足吞吐量的需求。In the data processing method provided by the embodiment of the present application, N=64, parameter C=0x0000 00000000 001B in the MULxPOW(V, i, C) function, k is 0, 1, 3, 4, and Z is 4, so that a second data sequence obtained by shifting the first data sequence left by i bits can be determined, wherein the first data sequence is a 64-bit binary sequence V[0]~V[63] of the parameter V in the MULxPOW(V, i, C) function, and the second data sequence is a new 64-bit binary sequence M[0]~M[63] obtained by shifting the 64-bit binary sequence V[0]~V[63], i is an integer between 0 and 63, so that when 1≤i≤60, the first data V[64-i+j] in the first data sequence is XOR-ed with the second data M[j], the second data M[1+j], the second data M[3+j], and the second data M[4+j] in the second data sequence to obtain the second data M[j] , the second data M[1+j], the second data M[3+j], and the second data M[4+j] respectively correspond to the XOR results, wherein j is an integer between 0 and i-1, so that according to the XOR results corresponding to the second data M[j], the second data M[1+j], the second data M[3+j], and the second data M[4+j] respectively correspond to the second data sequence, and a 64-bit third data sequence is obtained as the i-th output result, and the i-th output result is used to characterize the output result of the MULxPOW(V, i, C) function. However, based on the i-th output result, an information authentication code is generated, and the information authentication code is used to verify the integrity of the information. Therefore, the calculation of each level of the MULxPOW (V, i, C) function in the present application can only depend on the input V, without relying on the output of the previous level, so that the original serial calculation method of the MULxPOW (V, i, C) function can be changed to a parallel calculation method, which improves the speed of the hardware circuit of the message authentication code MAC calculation while also increasing the clock frequency and meeting the throughput requirements.
请参阅图10,图10示出了本申请又一个实施例提供的数据处理方法的流程示意图。下面将针对图10所示的流程进行详细的阐述,在基于前述实施例的基础上,也能实现i=61~64的并行计算。所示数据处理方法具体可以包括以下步骤:Please refer to FIG10, which shows a flow chart of a data processing method provided by another embodiment of the present application. The flow chart shown in FIG10 will be described in detail below. Based on the above embodiment, parallel computing of i=61-64 can also be realized. The data processing method shown may specifically include the following steps:
步骤S310:确定第一数据序列左移i位后得到的第二数据序列。Step S310: Determine a second data sequence obtained by shifting the first data sequence left by i bits.
步骤S320:当1≤i≤60时,将所述第一数据序列中的第一数据V[N-i+j]与所述第二数据序列中的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j]进行异或运算,得到所述第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j]各自对应的异或结果。Step S320: When 1≤i≤60, perform an XOR operation on the first data V[N-i+j] in the first data sequence and the second data M[j], second data M[1+j], second data M[3+j], and second data M[4+j] in the second data sequence to obtain the XOR results corresponding to the second data M[j], second data M[1+j], second data M[3+j], and second data M[4+j] respectively.
步骤S330:根据所述第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j]各自对应的异或结果,对所述第二数据序列中的所述第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j]进行对应更新,得到64位的第三数据序列作为第i输出结果。Step S330: According to the XOR results corresponding to the second data M[j], the second data M[1+j], the second data M[3+j], and the second data M[4+j], the second data M[j], the second data M[1+j], the second data M[3+j], and the second data M[4+j] in the second data sequence are correspondingly updated to obtain a 64-bit third data sequence as the i-th output result.
步骤S340:当i=61时,将所述第一数据序列中的第一数据V[3+j]分别与所述第二数据序列中的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j],以及所述第一数据序列中的第一数据V[63]分别与所述第二数据序列中的第二数据M[60]、第二数据M[61]、第二数据M[63]、第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4]进行异或运算,得到每个第二数据对应的异或结果。Step S340: When i=61, perform XOR operations on the first data V[3+j] in the first data sequence and the second data M[j], second data M[1+j], second data M[3+j], and second data M[4+j] in the second data sequence, and perform XOR operations on the first data V[63] in the first data sequence and the second data M[60], second data M[61], second data M[63], second data M[0], second data M[1], second data M[3], and second data M[4] in the second data sequence, to obtain the XOR results corresponding to each second data.
需要说明的是,当N为64,参数C为常量0x1B时,基于前述分析,之所以是最后一个可以通过前述规律计算出的嵌套函数,是因为它的计算最终依赖于C[5],而C[5]是参数C=0x1B中左边59个0中最靠右的一个0对应的位置,即C[4]的值已经为1。而发明人经过研究进一步发现,在之后的嵌套函数的计算,依赖于C[i](2≤i<5),虽然计算比较复杂,但仍可以确定出输入V和函数输出的映射关系。It should be noted that when N is 64 and parameter C is a constant 0x1B, based on the above analysis, The reason why it is the last nested function that can be calculated by the above rules is that its calculation ultimately depends on C[5], and C[5] is the position corresponding to the rightmost 0 among the 59 0s on the left of parameter C=0x1B, that is, the value of C[4] is already 1. The inventors further discovered that The calculation of the nested function is as follows: Depends on C[i](2≤i<5), although the calculation is more complicated, the mapping relationship between input V and function output can still be determined.
下面先对的输入V和函数输出的映射关系的确定过程进行描述。Next, The process of determining the mapping relationship between the input V and the function output is described.
具体地,对MULxPOW(V,61,C)=MULx(MULxPOW(V,60,C),C)进行简化时,可以得到:Specifically, when MULxPOW(V, 61, C)=MULx(MULxPOW(V, 60, C), C) is simplified, we can get:
其中, in,
由于C=0x1B,而C[4]为1,因此,可以继续简写为:because C=0x1B, and C[4] is 1, so It can be further abbreviated as:
基于上述公式,可以看出,由于(V<<1)[4]与1的异或操作,是在V[63]为1时才进行,因此,在(V<<1)[4]xor 1时,V[63]为1,从而可以用V[63]代替1与(V<<1)[4]进行异或。从而可以继续简写为:Based on the above formula, it can be seen that the XOR operation of (V<<1)[4] and 1 is performed only when V[63] is 1. Therefore, when (V<<1)[4]xor 1, V[63] is 1, so V[63] can be used instead of 1 to perform XOR with (V<<1)[4]. It can be further abbreviated as:
又由于V[63]不为1即为0时,其可以相当于,(V<<1)[4]与0进行异或,异或结果仍然为(V<<1)[4]。因此当V[63]=0时,仍可以使由于此时V[63]=0,因此可以相当于从而可以相当于因此,V[63]无论是否为1,都可以直接简写为:Since V[63] is not 1 but 0, This is equivalent to performing an XOR operation on (V<<1)[4] and 0, and the XOR result is still (V<<1)[4]. Therefore, when V[63]=0, Since V[63]=0 at this time, it can be equivalent to So it is equivalent to Therefore, whether V[63] is 1 or not, Can be directly abbreviated as:
所以, so,
同理,由于0x1B的64位的二进制数中左半部分由59个0组成,因此,当与0x1B进行按位异或计算时,左半部分59个0对应的输出,可以直接是的左半部分的59位数值,而对于值为1的比特位,由于与0x1B的异或操作,是在V[3]xor V[63]为1时才进行,因此,在时,V[3]xor V[63]为1,从而可以将0x1B的64位的二进制数中值为1的比特位,用V[3]xor V[63]代替1。从而,可以继续简写为:Similarly, since the left half of the 64-bit binary number 0x1B consists of 59 zeros, when When the bitwise XOR calculation is performed with 0x1B, the output corresponding to the 59 0s in the left half can be directly The 59-bit value of the left half of the value, and for the bit with value 1, due to The XOR operation with 0x1B is performed only when V[3]xor V[63] is 1. When V[3]xor V[63] is 1, the bit with the value of 1 in the 64-bit binary number 0x1B can be replaced by 1 with V[3]xor V[63]. Thus, It can be further abbreviated as:
同理,基于上述公式,可以看出,V[3]xor V[63]无论是否为1,都可以直接简写为:Similarly, based on the above formula, it can be seen that whether V[3]xor V[63] is 1 or not, Can be directly abbreviated as:
从而可以看出,的结果,可以是通过将移位1位后,将移位后的结果在指定比特位与V[3]和V[63]进行按位异或运算后得到。由于按照前述推导,可确定能够直接根据输入参数V得到,而除了外,也只与V[3]和V[63]有关,因此实质上也能够直接根据输入参数V得到,也即得到了与输入参数V的映射关系。Thus, it can be seen that The result can be obtained by After shifting by 1 bit, the shifted result is obtained by performing a bitwise XOR operation with V[3] and V[63] at the specified bit position. According to the above derivation, it can be determined that can be obtained directly from the input parameter V, and Apart from In addition, it is only related to V[3] and V[63], so In fact, it can also be obtained directly according to the input parameter V, that is, The mapping relationship with the input parameter V.
同理,也可以实现的计算电路设计。示例性地,请参阅图11,图11示出了一种的按位计算电路示意图。具体地,M的64位数据M[63]~M[0]对应的是的64位数据向左移动1位后的移位结果,如图11所示的虚线框中所展示的的计算电路向左移动1位后的计算电路,相当于Similarly, it is also possible to achieve For example, please refer to FIG. 11, which shows a circuit design of a Schematic diagram of the bit-by-bit calculation circuit. Specifically, the 64-bit data M[63]~M[0] of M corresponds to The shift result after the 64-bit data is shifted left by 1 bit is shown in the dotted box in Figure 11. The calculation circuit of the calculation circuit after shifting 1 bit to the left is equivalent to
同理由于{0,0,…,0,V[3]xor V[63],V[3]xor V[63],0,V[3]xor V[63],V[3]xor V[63]}中仅在比特位为0、1、3、4处为非0值V[3]xor V[63],因此,可以仅在M[0]、M[1]、M[3]、M[4]处增加与V[3]和V[63]的按位异或电路。 Similarly, since {0, 0, …, 0, V[3]xor V[63], V[3]xor V[63], 0, V[3]xor V[63], V[3]xor V[63]} has a non-zero value V[3]xor V[63] only at bits 0, 1, 3, and 4, we can add bitwise XOR circuits with V[3] and V[63] only at M[0], M[1], M[3], and M[4].
同理,从图11可以看出,本申请的硬件电路实现,实质上也是将V的64位数据V[63]~V[0]向左移动61位后,将移位后的结果在指定比特位与V[3]、V[4]…V[61]、V[62]、V[63]进行按位异或运算后得到。也即能够直接根据输入参数V得到,即得到了与输入参数V的映射关系。Similarly, it can be seen from Figure 11 that this application The hardware circuit implementation is actually to shift V's 64-bit data V[63]~V[0] to the left by 61 bits, and then perform a bitwise XOR operation on the shifted result with V[3], V[4]...V[61], V[62], V[63] at the specified bit position. It can be obtained directly according to the input parameter V, that is, The mapping relationship with the input parameter V.
发明人经过研究进一步发现,对于的结果,大部分是遵循前述的映射规律,仅有小部分是特殊规律,因此,可以仅针对这部分特殊规律部分的映射进行确定。具体地,基于前述分析并结合图11可以看出:The inventor further discovered through research that The results are mostly in accordance with the above Among the mapping rules, only a small part is a special rule, so only the mapping of this special rule part can be determined. Specifically, based on the above analysis and combined with Figure 11, it can be seen that:
也即,对于的结果,V[3]~V[62]与移位后的结果M中进行异或的M值的规律,是遵循前述的映射规律,即将输入参数V左移i位后,将V移位后的结果M中的M[0+j]、M[1+j]、M[3+j]、M[4+j]与V[N-i+j]即V[3+j]进行按位异或运算。仅有V[63]比较特殊,其需与移位后的结果M中的M[0]、M[1]、M[3]、M[4]、M[60]、M[61]、M[63]与进行异或。That is, for The result of the XOR operation of V[3]~V[62] with the shifted result M follows the rule of the M value mentioned above. The mapping rule is that after the input parameter V is shifted left by i bits, M[0+j], M[1+j], M[3+j], M[4+j] in the shifted result M of V are XORed with V[N-i+j], i.e. V[3+j]. Only V[63] is special, and it needs to be XORed with M[0], M[1], M[3], M[4], M[60], M[61], M[63] in the shifted result M.
基于前述分析,可以得到,当i=61时,此时相当于获取MULxPOW(V,61,C)函数即的输出结果,第一数据序列中需要进行异或运算的第一数据包括第一数据V[3+j]和第一数据V[63],第二数据序列中的需要进行异或运算的所述第二数据包括与所述第一数据V[3+j]对应的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j],以及与所述第一数据V[63]对应的第二数据M[60]、第二数据M[61]、第二数据M[63]、第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4]。其中,j为0~59之间的整数。Based on the above analysis, it can be obtained that when i=61, it is equivalent to obtaining the MULxPOW(V, 61, C) function, that is, The output result of , the first data to be XOR-operated in the first data sequence includes the first data V[3+j] and the first data V[63], the second data to be XOR-operated in the second data sequence includes the second data M[j], the second data M[1+j], the second data M[3+j], the second data M[4+j] corresponding to the first data V[3+j], and the second data M[60], the second data M[61], the second data M[63], the second data M[0], the second data M[1], the second data M[3], the second data M[4] corresponding to the first data V[63]. Wherein, j is an integer between 0 and 59.
因此,在本申请实施例中,当i=61时,在确定输入V和函数输出的映射关系时,可以将所述第一数据序列中的第一数据V[3+j]分别与所述第二数据序列中的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j],以及所述第一数据序列中的第一数据V[63]分别与所述第二数据序列中的第二数据M[60]、第二数据M[61]、第二数据M[63]、第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4]进行异或运算,得到每个第二数据对应的异或结果。Therefore, in an embodiment of the present application, when i=61, when determining the mapping relationship between the input V and the function output, the first data V[3+j] in the first data sequence can be XORed with the second data M[j], second data M[1+j], second data M[3+j], and second data M[4+j] in the second data sequence, and the first data V[63] in the first data sequence can be XORed with the second data M[60], second data M[61], second data M[63], second data M[0], second data M[1], second data M[3], and second data M[4] in the second data sequence, to obtain the XOR result corresponding to each second data.
步骤S350:根据所述每个第二数据对应的异或结果,对所述第二数据序列中的所述每个第二数据进行对应更新,得到N位的第三数据序列作为第61输出结果,所述第61输出结果用于表征所述MULxPOW(V,61,C)函数的输出结果。Step S350: According to the XOR result corresponding to each second data, each second data in the second data sequence is updated accordingly to obtain an N-bit third data sequence as the 61st output result, and the 61st output result is used to characterize the output result of the MULxPOW(V, 61, C) function.
可以理解的是,当N为64,参数C为常量0x1B时,对于i=61的情况,由于第二数据序列中的部分第二数据需要与第一数据进行异或运算,因此,可以获取每个第二数据与第一数据异或运算后的最终异或结果,并与第二数据序列中的其他未参与异或运算的数据重新拼接,得到新的N位的第三数据序列,该结果即为MULxPOW(V,61,C)函数即函数的输出结果。从而MULxPOW(V,61,C)函数也可以仅根据输入参数V计算得到,无需依赖上一级i=60的输出。It can be understood that when N is 64 and the parameter C is a constant 0x1B, for the case of i=61, since part of the second data in the second data sequence needs to be XORed with the first data, the final XOR result after the XOR operation of each second data with the first data can be obtained, and re-joined with other data in the second data sequence that do not participate in the XOR operation to obtain a new N-bit third data sequence, and the result is the MULxPOW(V, 61, C) function, that is, The output result of the function. Therefore, the MULxPOW (V, 61, C) function can also be calculated based on the input parameter V only, without relying on the output of the previous level i = 60.
步骤S360:当i=62时,将所述第一数据序列中的第一数据V[2+j]分别与所述第二数据序列中的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j],所述第一数据序列中的第一数据V[62]分别与所述第二数据序列中的第二数据M[60]、第二数据M[61]、第二数据M[63]、第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4],以及所述第一数据序列中的第一数据V[63]分别与所述第二数据序列中的第二数据M[61]、第二数据M[62]、第二数据M[0]、第二数据M[1]、第二数据M[2]、第二数据M[3]、第二数据M[4]、第二数据M[5]进行异或运算,得到每个第二数据对应的异或结果。Step S360: When i=62, perform XOR operations on the first data V[2+j] in the first data sequence and the second data M[j], second data M[1+j], second data M[3+j], and second data M[4+j] in the second data sequence, respectively; perform XOR operations on the first data V[62] in the first data sequence and the second data M[60], second data M[61], second data M[63], second data M[0], second data M[1], second data M[3], and second data M[4] in the second data sequence, respectively; and perform XOR operations on the first data V[63] in the first data sequence and the second data M[61], second data M[62], second data M[0], second data M[1], second data M[2], second data M[3], second data M[4], and second data M[5] in the second data sequence, respectively, to obtain XOR results corresponding to each second data.
同理,也可以确认的输入V和函数输出的映射关系。下面先对的输入V和函数输出的映射关系的确定过程进行描述。Similarly, we can confirm The mapping relationship between the input V and the function output. The process of determining the mapping relationship between the input V and the function output is described.
具体地,对MULxPOW(V,62,C)=MULx(MULxPOW(V,61,C),C)进行简化时,可以得到:Specifically, when MULxPOW(V, 62, C)=MULx(MULxPOW(V, 61, C), C) is simplified, we can get:
其中, in,
所以,可以简写为:so, It can be shortened to:
从而可以看出,的结果,可以是通过将移位1位后,将移位后的结果在指定比特位与V[2]、V[62]和V[63]进行按位异或运算后得到。由于按照前述推导,可确定能够直接根据输入参数V得到,而除了外,也只与V[3]、V[62]和V[63]有关,因此实质上也能够直接根据输入参数V得到,也即得到了与输入参数V的映射关系。Thus, it can be seen that The result can be obtained by After shifting by 1 bit, the shifted result is obtained by performing a bitwise XOR operation with V[2], V[62], and V[63] at the specified bit position. According to the above derivation, it can be determined that can be obtained directly from the input parameter V, and Apart from In addition, it is only related to V[3], V[62] and V[63], so In fact, it can also be obtained directly according to the input parameter V, that is, The mapping relationship with the input parameter V.
同理,也可以实现的计算电路设计。示例性地,请参阅图12,图12示出了一种的按位计算电路示意图。具体地,M的64位数据M[63]~M[0]对应的是的64位数据向左移动1位后的移位结果,如图12所示的虚线框中所展示的的计算电路向左移动1位后的计算电路,相当于由于{0,0,…,0,V[2]xorV[63]xorV[62],V[2]xorV[63]xorV[62],0,V[2]xorV[63]xorV[62],V[2]xorV[63]xorV[62]}中仅在比特位为0、1、3、4处为非0值V[2]xorV[63]xorV[62],因此,可仅在M[0]、M[1]、M[3]、M[4]处增加与V[2]、V[62]和V[63]的按位异或电路。Similarly, it is also possible to achieve For example, please refer to FIG. 12 , which shows a circuit design of a Schematic diagram of the bit-by-bit calculation circuit. Specifically, the 64-bit data M[63]~M[0] of M corresponds to The shift result after the 64-bit data is shifted left by 1 bit is shown in the dotted box in Figure 12. The calculation circuit of the calculation circuit after shifting 1 bit to the left is equivalent to Since the only non-zero values V[2]xorV[63]xorV[62] in {0, 0, …, 0, V[2]xorV[63]xorV[62], V[2]xorV[63]xorV[62], 0, V[2]xorV[63]xorV[62], V[2]xorV[63]xorV[62]} are at bits 0, 1, 3, and 4, bitwise XOR circuits with V[2], V[62], and V[63] can be added only at M[0], M[1], M[3], and M[4].
同理,从图12可以看出,本申请的硬件电路实现,实质上也是将V的64位数据V[63]~V[0]向左移动62位后,将移位后的结果在指定比特位与V[2]、V[3]…V[61]、V[62]、V[63]进行按位异或运算后得到。也即能够直接根据输入参数V得到,即得到了与输入参数V的映射关系。Similarly, it can be seen from Figure 12 that this application The hardware circuit implementation is actually to shift V's 64-bit data V[63]~V[0] to the left by 62 bits, and then perform a bitwise XOR operation on the shifted result with V[2], V[3]...V[61], V[62], V[63] at the specified bit position. It can be obtained directly according to the input parameter V, that is, The mapping relationship with the input parameter V.
同理,结合图12可以看出,对于的结果,V[2]~V[61]与移位后的结果M中进行异或的M值的规律,是遵循前述的映射规律,即将输入参数V左移i位后,将V移位后的结果M中的M[0+j]、M[1+j]、M[3+j]、M[4+j]与V[N-i+j]即V[2+j]进行按位异或运算。只有V[62]、V[63]比较特殊,V[62]需与移位后的结果M中的M[0]、M[1]、M[3]、M[4]、M[60]、M[61]、M[63]与进行异或,V[63]需与移位后的结果M中的M[0]、M[1]、M[2]、M[3]、M[4]、M[5]、M[61]、M[62]与进行异或。且M[1]和M[4]均需与V[63]异或两次。Similarly, combined with Figure 12, it can be seen that for The result of the XOR operation of V[2]~V[61] with the shifted result M follows the rule of the M value mentioned above. The mapping rule is that after the input parameter V is shifted left by i bits, M[0+j], M[1+j], M[3+j], M[4+j] in the shifted result M of V are XORed with V[N-i+j], i.e. V[2+j]. Only V[62] and V[63] are special. V[62] needs to be XORed with M[0], M[1], M[3], M[4], M[60], M[61], M[63] in the shifted result M, and V[63] needs to be XORed with M[0], M[1], M[2], M[3], M[4], M[5], M[61], M[62] in the shifted result M. And M[1] and M[4] need to be XORed with V[63] twice.
基于前述分析,可以得到,当i=62时,此时相当于获取MULxPOW(V,62,C)函数即的输出结果,第一数据序列中需要进行异或运算的第一数据包括第一数据V[2+j]、第一数据V[62]和第一数据V[63],第二数据序列中的需要进行异或运算的所述第二数据包括与所述第一数据V[2+j]对应的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j],以及与所述第一数据V[62]对应的第二数据M[60]、第二数据M[61]、第二数据M[63]、第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4],以及与所述第一数据V[63]对应的第二数据M[61]、第二数据M[62]、第二数据M[0]、第二数据M[1]、第二数据M[2]、第二数据M[3]、第二数据M[4]、第二数据M[5]。其中,第二数据M[1]和第二数据M[4]均需与第一数据V[63]异或两次,j为0~59之间的整数。Based on the above analysis, it can be obtained that when i=62, it is equivalent to obtaining the MULxPOW(V, 62, C) function, that is, The output result of the operation is as follows: the first data in the first data sequence that need to be XOR-operated include the first data V[2+j], the first data V[62] and the first data V[63]; the second data in the second data sequence that need to be XOR-operated include the second data M[j], the second data M[1+j], the second data M[3+j] and the second data M[4+j] corresponding to the first data V[2+j], and the second data M[60], the second data M[61], the second data M[63], the second data M[0], the second data M[1], the second data M[3] and the second data M[4] corresponding to the first data V[62], and the second data M[61], the second data M[62], the second data M[0], the second data M[1], the second data M[2], the second data M[3], the second data M[4] and the second data M[5] corresponding to the first data V[63]. The second data M[1] and the second data M[4] both need to be XORed with the first data V[63] twice, and j is an integer between 0 and 59.
因此,在本申请实施例中,当i=62时,在确定输入V和函数输出的映射关系时,可以将所述第一数据序列中的第一数据V[2+j]分别与所述第二数据序列中的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j],以及所述第一数据序列中的第一数据V[62]分别与所述第二数据序列中的第二数据M[60]、第二数据M[61]、第二数据M[63]、第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4],以及所述第一数据序列中的第一数据V[63]分别与所述第二数据序列中的第二数据M[61]、第二数据M[62]、第二数据M[0]、第二数据M[1]、第二数据M[2]、第二数据M[3]、第二数据M[4]、第二数据M[5]进行异或运算,得到每个第二数据对应的异或结果。其中,第二数据M[1]和第二数据M[4]均需与第一数据V[63]进行两次异或运算,j为0~59之间的整数。Therefore, in an embodiment of the present application, when i=62, when determining the mapping relationship between the input V and the function output, the first data V[2+j] in the first data sequence can be respectively XORed with the second data M[j], second data M[1+j], second data M[3+j], and second data M[4+j] in the second data sequence, and the first data V[62] in the first data sequence can be respectively XORed with the second data M[60], second data M[61], second data M[63], second data M[0], second data M[1], second data M[3], and second data M[4] in the second data sequence, and the first data V[63] in the first data sequence can be respectively XORed with the second data M[61], second data M[62], second data M[0], second data M[1], second data M[2], second data M[3], second data M[4], and second data M[5] in the second data sequence to obtain the XOR result corresponding to each second data. The second data M[1] and the second data M[4] both need to be XORed twice with the first data V[63], and j is an integer between 0 and 59.
步骤S370:根据所述每个第二数据对应的异或结果,对所述第二数据序列中的所述每个第二数据进行对应更新,得到N位的第三数据序列作为第62输出结果,所述第62输出结果用于表征所述MULxPOW(V,62,C)函数的输出结果。Step S370: According to the XOR result corresponding to each second data, each second data in the second data sequence is updated accordingly to obtain an N-bit third data sequence as the 62nd output result, and the 62nd output result is used to characterize the output result of the MULxPOW(V, 62, C) function.
步骤S380:当i=63时,将所述第一数据序列中的第一数据V[1+j]分别与所述第二数据序列中的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j],所述第一数据序列中的第一数据V[61]分别与所述第二数据序列中的第二数据M[60]、第二数据M[61]、第二数据M[63]、第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4],所述第一数据序列中的第一数据V[62]分别与所述第二数据序列中的第二数据M[61]、第二数据M[62]、第二数据M[0]、第二数据M[1]、第二数据M[2]、第二数据M[3]、第二数据M[4]、第二数据M[5],以及所述第一数据序列中的第一数据V[63]分别与所述第二数据序列中的第二数据M[62]、第二数据M[63]、第二数据M[1]、第二数据M[2]、第二数据M[3]、第二数据M[4]、第二数据M[5]、第二数据M[6]进行异或运算,得到每个第二数据对应的异或结果。Step S380: When i=63, the first data V[1+j] in the first data sequence is respectively combined with the second data M[j], second data M[1+j], second data M[3+j], and second data M[4+j] in the second data sequence; the first data V[61] in the first data sequence is respectively combined with the second data M[60], second data M[61], second data M[63], second data M[0], second data M[1], second data M[3], and second data M[4] in the second data sequence; the first data V[62] in the first data sequence is respectively combined with the second data M[63], second data M[0], second data M[1], second data M[3], and second data M[4] in the second data sequence. The second data M[61], second data M[62], second data M[0], second data M[1], second data M[2], second data M[3], second data M[4], second data M[5] in the second data sequence, and the first data V[63] in the first data sequence are respectively XOR-ed with the second data M[62], second data M[63], second data M[1], second data M[2], second data M[3], second data M[4], second data M[5], second data M[6] in the second data sequence to obtain the XOR result corresponding to each second data.
同理,也可以确认的输入V和函数输出的映射关系。下面先对的输入V和函数输出的映射关系的确定过程进行描述。Similarly, we can confirm The mapping relationship between the input V and the function output. The process of determining the mapping relationship between the input V and the function output is described.
具体地,对MULxPOW(V,63,C)=MULx(MULxPOW(V,62,C),C)进行简化时,可以得到:Specifically, when MULxPOW(V, 63, C)=MULx(MULxPOW(V, 62, C), C) is simplified, we can obtain:
其中, in,
所以,可以简写为:so, It can be shortened to:
从而可以看出,的结果,可以是通过将移位1位后,将移位后的结果在指定比特位与V[1]、V[61]和V[62]进行按位异或运算后得到。由于按照前述推导,可确定能够直接根据输入参数V得到,而除了外,也只与V[1]、V[61]和V[62]有关,因此实质上也能够直接根据输入参数V得到,也即得到了与输入参数V的映射关系。Thus, it can be seen that The result can be obtained by After shifting by 1 bit, the shifted result is obtained by performing a bitwise XOR operation with V[1], V[61], and V[62] at the specified bit position. According to the above derivation, it can be determined that can be obtained directly from the input parameter V, and Apart from In addition, it is only related to V[1], V[61] and V[62], so In fact, it can also be obtained directly according to the input parameter V, that is, The mapping relationship with the input parameter V.
同理,也可以实现的计算电路设计。示例性地,请参阅图13,图13示出了一种的按位计算电路示意图。具体地,M的64位数据M[63]~M[0]对应的是的64位数据向左移动1位后的移位结果,如图13所示的虚线框中所展示的的计算电路向左移动1位后的计算电路,相当于由于{0,0,…,0,V[1]xorV[62]xorV[61],V[1]xorV[62]xorV[61],0,V[1]xorV[62]xorV[61],V[1]xorV[62]xorV[61]}中仅在比特位为0、1、3、4处为非0值V[1]xorV[62]xorV[61],因此,可仅在M[0]、M[1]、M[3]、M[4]处增加与V[1]、V[61]和V[62]的按位异或电路。Similarly, it is also possible to achieve For example, please refer to FIG. 13 , which shows a calculation circuit design. Schematic diagram of the bit-by-bit calculation circuit. Specifically, the 64-bit data M[63]~M[0] of M corresponds to The shift result after the 64-bit data is shifted left by 1 bit is shown in the dotted box in Figure 13. The calculation circuit of the calculation circuit after shifting 1 bit to the left is equivalent to Since the only non-zero values V[1]xorV[62]xorV[61] in {0, 0, …, 0, V[1]xorV[62]xorV[61], V[1]xorV[62]xorV[61], 0, V[1]xorV[62]xorV[61], V[1]xorV[62]xorV[61]} are at bits 0, 1, 3, and 4, bitwise XOR circuits with V[1], V[61], and V[62] can be added only at M[0], M[1], M[3], and M[4].
同理,从图13可以看出,本申请的硬件电路实现,实质上也是将V的64位数据V[63]~V[0]向左移动63位后,将移位后的结果在指定比特位与V[1]、V[2]…V[61]、V[62]、V[63]进行按位异或运算后得到。也即能够直接根据输入参数V得到,即得到了与输入参数V的映射关系。Similarly, it can be seen from Figure 13 that this application The hardware circuit implementation is actually to shift V's 64-bit data V[63]~V[0] to the left by 63 bits, and then perform a bitwise XOR operation on the shifted result with V[1], V[2]...V[61], V[62], V[63] at the specified bit position. It can be obtained directly according to the input parameter V, that is, The mapping relationship with the input parameter V.
同理,结合图13可以看出,对于的结果,V[1]~V[60]与移位后的结果M中进行异或的M值的规律,是遵循前述的映射规律,即将输入参数V左移i位后,将V移位后的结果M中的M[0+j]、M[1+j]、M[3+j]、M[4+j]与V[N-i+j]即V[1+j]进行按位异或运算。只有V[61]、V[62]、V[63]比较特殊,V[61]需与移位后的结果M中的M[0]、M[1]、M[3]、M[4]、M[60]、M[61]、M[63]与进行异或,V[62]需与移位后的结果M中的M[0]、M[1]、M[2]、M[3]、M[4]、M[5]、M[61]、M[62]与进行异或,V[63]需与移位后的结果M中的M[1]、M[2]、M[3]、M[4]、M[5]、M[6]、M[62]、M[63]与进行异或。且M[2]和M[5]均需与V[63]异或两次,M[1]和M[4]均需与V[62]异或两次。Similarly, combined with Figure 13, it can be seen that for The result of the XOR operation of V[1]~V[60] with the shifted result M follows the rule of the M value mentioned above. The mapping rule is that after the input parameter V is shifted left by i bits, M[0+j], M[1+j], M[3+j], M[4+j] in the shifted result M of V are bitwise XORed with V[N-i+j], i.e. V[1+j]. Only V[61], V[62], and V[63] are special. V[61] needs to be XORed with M[0], M[1], M[3], M[4], M[60], M[61], and M[63] in the shifted result M. V[62] needs to be XORed with M[0], M[1], M[2], M[3], M[4], M[5], M[61], and M[62] in the shifted result M. V[63] needs to be XORed with M[1], M[2], M[3], M[4], M[5], M[6], M[62], and M[63] in the shifted result M. M[2] and M[5] both need to be XORed with V[63] twice, and M[1] and M[4] both need to be XORed with V[62] twice.
基于前述分析,可以得到,当i=63时,此时相当于获取MULxPOW(V,63,C)函数即的输出结果,第一数据序列中需要进行异或运算的第一数据包括第一数据V[1+j]、第一数据V[61]、第一数据V[62]和第一数据V[63],第二数据序列中的需要进行异或运算的所述第二数据包括与所述第一数据V[1+j]对应的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j],以及与所述第一数据V[61]对应的第二数据M[60]、第二数据M[61]、第二数据M[63]、第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4],以及与所述第一数据V[62]对应的第二数据M[61]、第二数据M[62]、第二数据M[0]、第二数据M[1]、第二数据M[2]、第二数据M[3]、第二数据M[4]、第二数据M[5],以及与所述第一数据V[63]对应的第二数据M[62]、第二数据M[63]、第二数据M[1]、第二数据M[2]、第二数据M[3]、第二数据M[4]、第二数据M[5]、第二数据M[6]。其中,第二数据M[1]和第二数据M[4]均需与第一数据V[62]异或两次,第二数据M[2]和第二数据M[5]均需与第一数据V[63]异或两次,j为0~59之间的整数。Based on the above analysis, it can be obtained that when i=63, it is equivalent to obtaining the MULxPOW(V, 63, C) function, that is, The output result of the first data sequence that needs to be XOR-operated includes first data V[1+j], first data V[61], first data V[62] and first data V[63], and the second data sequence that needs to be XOR-operated includes second data M[j], second data M[1+j], second data M[3+j], second data M[4+j] corresponding to the first data V[1+j], and second data M[60], second data M[61], second data M[63], second data M[0], The second data M[1], the second data M[3], the second data M[4], and the second data M[61], the second data M[62], the second data M[0], the second data M[1], the second data M[2], the second data M[3], the second data M[4], the second data M[5] corresponding to the first data V[62], and the second data M[62], the second data M[63], the second data M[1], the second data M[2], the second data M[3], the second data M[4], the second data M[5], the second data M[6] corresponding to the first data V[63]. The second data M[1] and the second data M[4] both need to be XORed with the first data V[62] twice, and the second data M[2] and the second data M[5] both need to be XORed with the first data V[63] twice, and j is an integer between 0 and 59.
因此,在本申请实施例中,当i=63时,在确定输入V和函数输出的映射关系时,可以将所述第一数据序列中的第一数据V[1+j]分别与所述第二数据序列中的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j],所述第一数据序列中的第一数据V[61]分别与所述第二数据序列中的第二数据M[60]、第二数据M[61]、第二数据M[63]、第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4],所述第一数据序列中的第一数据V[62]分别与所述第二数据序列中的第二数据M[61]、第二数据M[62]、第二数据M[0]、第二数据M[1]、第二数据M[2]、第二数据M[3]、第二数据M[4]、第二数据M[5],以及所述第一数据序列中的第一数据V[63]分别与所述第二数据序列中的第二数据M[62]、第二数据M[63]、第二数据M[1]、第二数据M[2]、第二数据M[3]、第二数据M[4]、第二数据M[5]、第二数据M[6]进行异或运算,得到每个第二数据对应的异或结果。其中,第二数据M[1]和第二数据M[4]均需与第一数据V[62]进行两次异或运算,第二数据M[2]和第二数据M[5]均需与第一数据V[63]进行两次异或运算,j为0~59之间的整数。Therefore, in this embodiment of the present application, when i=63, when determining the mapping relationship between the input V and the function output, the first data V[1+j] in the first data sequence can be respectively mapped to the second data M[j], second data M[1+j], second data M[3+j], and second data M[4+j] in the second data sequence; the first data V[61] in the first data sequence can be respectively mapped to the second data M[60], second data M[61], second data M[63], second data M[0], second data M[1], second data M[3], and second data M[4] in the second data sequence; the first data V[61] in the first data sequence can be respectively mapped to the second data M[60], second data M[61], second data M[63], second data M[0], second data M[1], second data M[3], and second data M[4] in the second data sequence; A data V[62] is XORed with the second data M[61], the second data M[62], the second data M[0], the second data M[1], the second data M[2], the second data M[3], the second data M[4], and the second data M[5] in the second data sequence, and the first data V[63] in the first data sequence is XORed with the second data M[62], the second data M[63], the second data M[1], the second data M[2], the second data M[3], the second data M[4], the second data M[5], and the second data M[6] in the second data sequence, to obtain an XOR result corresponding to each second data. The second data M[1] and the second data M[4] both need to be XORed with the first data V[62] twice, and the second data M[2] and the second data M[5] both need to be XORed with the first data V[63] twice, and j is an integer between 0 and 59.
步骤S390:根据所述每个第二数据对应的异或结果,对所述第二数据序列中的所述每个第二数据进行对应更新,得到N位的第三数据序列作为第63输出结果,所述第63输出结果用于表征所述MULxPOW(V,63,C)函数的输出结果。Step S390: According to the XOR result corresponding to each second data, each second data in the second data sequence is updated accordingly to obtain an N-bit third data sequence as the 63rd output result, and the 63rd output result is used to characterize the output result of the MULxPOW (V, 63, C) function.
步骤S400:基于所述第i输出结果,生成信息认证码,所述信息认证码用于校验信息的完整性。所述i为0~N-1之间的整数。Step S400: Based on the i-th output result, generate a message authentication code, the message authentication code is used to verify the integrity of the message, wherein i is an integer between 0 and N-1.
在本申请实施例中,均可以确定各自与输入参数V的映射关系,从而可以直接根据输入参数V计算得到,无需依赖上一级i的输出,从而可以改变相关技术中的串行计算方式,而是采用并行计算方式,使得可以在一个时钟周期里同时计算出MULxPOW(V,i,C)每个i对应的输出,提高了系统计算的吞吐量。In the embodiments of the present application, Each of them can determine the mapping relationship with the input parameter V, so that it can be calculated directly according to the input parameter V without relying on the output of the previous level i, thereby changing the serial calculation method in the relevant technology and adopting a parallel calculation method. In this way, the output corresponding to each i of MULxPOW (V, i, C) can be calculated simultaneously in one clock cycle, thereby improving the throughput of system calculation.
在一些实施例中,可以具体是先根据接收到的N位的密钥序列,从所述第i输出结果中确定目标输出结果,其中,所述i为0~N-1之间的整数。然后将所述目标输出结果与预设初始值进行异或运算,得到目标异或结果,最后基于所述目标异或结果,生成信息认证码,所述信息认证码用于校验信息的完整性。In some embodiments, the target output result can be determined from the i-th output result according to the received N-bit key sequence, where i is an integer between 0 and N-1. Then, the target output result is XORed with a preset initial value to obtain a target XOR result, and finally, based on the target XOR result, an information authentication code is generated, and the information authentication code is used to verify the integrity of the information.
其中,N位的密钥序列可以是MUL(V,P,C)中参数P的N位的二进制序列。可以根据该N位的密钥序列中每一位密钥的0或1值,对应选择是否将第i输出结果作为加入到后续的异或过程的目标输出结果。示例性地,请参阅图3,可以根据参数P的N位的二进制序列中每一位二进制0或1值,选择是将对应级的MULxPOW(V,i,C)函数的输出结果与其他级输出结果进行异或,还是选择不将对应级的MULxPOW(V,i,C)函数的输出结果加入到后续的异或过程。Among them, the N-bit key sequence can be the N-bit binary sequence of the parameter P in MUL (V, P, C). According to the 0 or 1 value of each key in the N-bit key sequence, it can be selected whether to use the i-th output result as the target output result added to the subsequent XOR process. Exemplarily, referring to Figure 3, according to the 0 or 1 value of each binary bit in the N-bit binary sequence of the parameter P, it can be selected whether to XOR the output result of the MULxPOW (V, i, C) function of the corresponding level with the output results of other levels, or to choose not to add the output result of the MULxPOW (V, i, C) function of the corresponding level to the subsequent XOR process.
其中,预设初始值可以是用户自定值,在UIA2完整性保护算法中其被设为0。示例性地,请参阅图3中的result=0即为预设初始值。The preset initial value may be a user-defined value, which is set to 0 in the UIA2 integrity protection algorithm. For example, please refer to FIG. 3 where result=0 is the preset initial value.
可以理解的是,在根据接收到的N位的密钥序列,从所述第i输出结果中确定目标输出结果后,可以得到被选择为用于进行异或运算的MULxPOW(V,i,C)函数的输出结果,从而可以将目标输出结果与预设初始值进行异或运算,得到目标异或结果,该目标异或结果可以理解为MUL(V,P,C)函数的最终输出结果。It can be understood that after determining the target output result from the i-th output result based on the received N-bit key sequence, the output result of the MULxPOW(V, i, C) function selected for the XOR operation can be obtained, so that the target output result can be XORed with the preset initial value to obtain the target XOR result, which can be understood as the final output result of the MUL(V, P, C) function.
在本申请实施例中,在得到目标异或结果即MUL(V,P,C)函数的最终输出结果后,可以基于目标异或结果,生成信息认证码,所述信息认证码用于校验信息的完整性。例如,前述UIA2完整性保护算法计算消息认证码MAC的过程中的第十步~第十二步。In the embodiment of the present application, after obtaining the target XOR result, i.e., the final output result of the MUL(V, P, C) function, a message authentication code can be generated based on the target XOR result, and the message authentication code is used to verify the integrity of the information. For example, the tenth to twelfth steps in the process of calculating the message authentication code MAC in the aforementioned UIA2 integrity protection algorithm.
本申请实施例提供的数据处理方法,N=64,MULxPOW(V,i,C)函数中参数C=0x0000 00000000 001B,k为0、1、3、4,Z为4,通过确定64级中每一级的计算与输出V的映射关系,可以使得本申请中MULxPOW(V,i,C)函数的每一级的计算可以只依赖于输入V,无需依赖上一级的输出,使得可以将原有的MULxPOW(V,i,C)函数的串行计算方式,改变为并行计算方式,提高了消息认证码MAC计算的硬件电路的速度的同时,也提高了时钟频率、满足吞吐量的需求。In the data processing method provided in the embodiment of the present application, N=64, parameter C=0x0000 00000000 001B in the MULxPOW(V, i, C) function, k is 0, 1, 3, 4, and Z is 4. By determining the mapping relationship between the calculation of each level in the 64 levels and the output V, the calculation of each level of the MULxPOW(V, i, C) function in the present application can only depend on the input V without relying on the output of the previous level, so that the original serial calculation mode of the MULxPOW(V, i, C) function can be changed to a parallel calculation mode, which improves the speed of the hardware circuit of the message authentication code MAC calculation while also improving the clock frequency and meeting the throughput requirements.
基于前述的数据处理方法得到的每一级的按位计算电路,可以重新设计UIA2计算电路,以将其中MULxPOW(V,i,C)函数的并行计算电路更改为串行计算电路。具体地,请参阅图14,图14示出了本申请再一个实施例提供的UIA2计算电路的示意图。用于实现MULxPOW(V,i,C)函数的计算输出。该UIA2计算电路500包括64级MUL单元510以及与所述64级MUL单元分别对应连接的64级混合运算单元520,其中:所述64级MUL单元510的各级MUL单元独立运行。具体地,对于所述64级MUL单元510中的第i级MUL单元,用于接收N64位的第一数据序列,并对所述64N位的第一数据序列进行第i级MUL运算,得到第i级MUL运算结果,i为整数且i的取值从0遍历至63i和N皆为大于1的整数,且i的取值从1遍历至N;Based on the bitwise calculation circuit of each level obtained by the aforementioned data processing method, the UIA2 calculation circuit can be redesigned to change the parallel calculation circuit of the MULxPOW (V, i, C) function into a serial calculation circuit. Specifically, please refer to FIG. 14, which shows a schematic diagram of the UIA2 calculation circuit provided by another embodiment of the present application. It is used to realize the calculation output of the MULxPOW (V, i, C) function. The UIA2 calculation circuit 500 includes 64-level MUL units 510 and 64-level mixed operation units 520 respectively connected to the 64-level MUL units, wherein: each level of the MUL units of the 64-level MUL units 510 operates independently. Specifically, the i-th level MUL unit in the 64-level MUL unit 510 is used to receive the N64-bit first data sequence, and perform the i-th level MUL operation on the 64N-bit first data sequence to obtain the i-th level MUL operation result, where i is an integer and the value of i ranges from 0 to 63i and N are both integers greater than 1, and the value of i ranges from 1 to N;
对于所述64级混合运算单元520中的第i级混合运算单元,分别与第i-1级混合运算单元和所述第i级MUL单元连接,用于接收第i-1级运算单元的第i-1级混合运算结果和所述第i级MUL运算结果,并基于所述第i-1级混合运算结果和所述第i级MUL运算结果,得到第i级混合运算结果;其中,第N级混合运算结果为所述第一数据序列对应的运算结果。The i-th level mixing operation unit in the 64-level mixing operation unit 520 is respectively connected to the i-1-th level mixing operation unit and the i-th level MUL unit, and is used to receive the i-1-th level mixing operation result and the i-th level MUL operation result of the i-1-th level operation unit, and obtain the i-th level mixing operation result based on the i-1-th level mixing operation result and the i-th level MUL operation result; wherein the N-th level mixing operation result is the operation result corresponding to the first data sequence.
从而,基于前述UIA2计算电路,第i级MUL单元可以接收64位的第一数据序列,并对所述64位的第一数据序列进行第i级MUL运算,得到第i级MUL运算结果;第i级混合运算单元可以接收第i-1级运算单元的第i-1级混合运算结果和所述第i级MUL运算结果,并基于所述第i-1级混合运算结果和所述第i级MUL运算结果,得到第i级混合运算结果;其中,第N级混合运算结果为所述第一数据序列对应的运算结果。Thus, based on the aforementioned UIA2 calculation circuit, the i-th level MUL unit can receive a 64-bit first data sequence, and perform an i-th level MUL operation on the 64-bit first data sequence to obtain an i-th level MUL operation result; the i-th level mixing operation unit can receive the i-1th level mixing operation result of the i-1th level operation unit and the i-th level MUL operation result, and obtain the i-th level mixing operation result based on the i-1th level mixing operation result and the i-th level MUL operation result; wherein, the N-th level mixing operation result is the operation result corresponding to the first data sequence.
在一些实施例中,i大于0时,所述第i级MUL单元包括第i移位电路,以及与所述第i移位电路连接的第i异或电路。其中:所述第i移位电路,用于接收所述64位的第一数据序列,并对所述64位的第一数据序列进行第i级移位运算,得到第i级移位结果;所述第i异或电路,用于接收所述第i级移位结果和所述64位的第一数据序列,并基于所述第i级移位结果和所述64位的第一数据序列进行第i级异或运算,得到第i级MUL运算结果。In some embodiments, when i is greater than 0, the i-th MUL unit includes an i-th shift circuit and an i-th XOR circuit connected to the i-th shift circuit. The i-th shift circuit is used to receive the 64-bit first data sequence and perform an i-th shift operation on the 64-bit first data sequence to obtain an i-th shift result; the i-th XOR circuit is used to receive the i-th shift result and the 64-bit first data sequence, and perform an i-th XOR operation based on the i-th shift result and the 64-bit first data sequence to obtain an i-th MUL operation result.
在一些实施例中,所述第i移位电路,用于对所述64位的第一数据序列V[0]~V[63]左移位i位,得到移位后的64位的第二数据序列M[0]~M[63]作为第i级移位结果。所述第i异或电路,用于输出所述64位的第一数据序列中的第一数据V[64-i+j]与所述64位的第二数据序列中的第二数据M[k+j]的异或结果,并基于该异或结果对所述第二数据序列中的所述第二数据M[k+j]进行对应更新,得到64位的第三数据序列作为第i级MUL运算结果,其中,j为整数且j的取值从0遍历至i-1,所述k为指定比特位,所述k的个数为至少一个。In some embodiments, the i-th shift circuit is used to shift the 64-bit first data sequence V[0]~V[63] left by i bits to obtain the shifted 64-bit second data sequence M[0]~M[63] as the i-th shift result. The i-th XOR circuit is used to output the XOR result of the first data V[64-i+j] in the 64-bit first data sequence and the second data M[k+j] in the 64-bit second data sequence, and update the second data M[k+j] in the second data sequence accordingly based on the XOR result to obtain a 64-bit third data sequence as the i-th MUL operation result, wherein j is an integer and the value of j ranges from 0 to i-1, and the k is a specified bit, and the number of k is at least one.
基于此,当i大于0时,所述第i移位电路可以接收所述64位的第一数据序列,并对所述64位的第一数据序列V[0]~V[63]左移位i位,得到移位后的64位的第二数据序列M[0]~M[63]作为第i级移位结果,并可以向所述第i异或电路输入所述第i级移位结果。然后所述第i异或电路可以接收所述64位的第一数据序列和所述第i移位电路输入的所述第i移位电路,并对所述64位的第一数据序列中的第一数据V[64-i+j]与所述64位的第二数据序列中的第二数据M[k+j]进行异或运算,得到异或结果,然后基于所述异或结果对所述第二数据序列中的所述第二数据M[k+j]进行对应更新,得到64位的第三数据序列作为第i级MUL运算结果,其中,j为整数且j的取值从0遍历至i-1,所述k为指定比特位,所述k的个数为至少一个。Based on this, when i is greater than 0, the i-th shift circuit can receive the 64-bit first data sequence, and left-shift the 64-bit first data sequence V[0]~V[63] by i bits to obtain the shifted 64-bit second data sequence M[0]~M[63] as the i-th stage shift result, and the i-th stage shift result can be input into the i-th XOR circuit. Then the i-th XOR circuit can receive the 64-bit first data sequence and the i-th shift circuit input by the i-th shift circuit, and perform an XOR operation on the first data V[64-i+j] in the 64-bit first data sequence and the second data M[k+j] in the 64-bit second data sequence to obtain an XOR result, and then based on the XOR result, the second data M[k+j] in the second data sequence is correspondingly updated to obtain a 64-bit third data sequence as the i-th level MUL operation result, wherein j is an integer and the value of j traverses from 0 to i-1, the k is a specified bit, and the number of k is at least one.
在一些实施例中,所述k可以为0、1、3、4,i的取值从1遍历至60时,所述第二数据M[k+j]为第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j],其中:所述第i异或电路包括4i个异或门,所述4i个异或门用于输出所述第一数据V[64-i+j]与所述第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j]的异或结果。In some embodiments, k can be 0, 1, 3, or 4, and when the value of i ranges from 1 to 60, the second data M[k+j] is the second data M[j], the second data M[1+j], the second data M[3+j], and the second data M[4+j], wherein: the i-th XOR circuit includes 4i XOR gates, and the 4i XOR gates are used to output the XOR results of the first data V[64-i+j] and the second data M[j], the second data M[1+j], the second data M[3+j], and the second data M[4+j].
也就是说,第1级MUL单元至第60级MUL单元中各级的异或电路,都是通过对应将所述第一数据V[64-i+j]与所述第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j]进行异或运算,得到异或结果。然后基于所述异或结果对所述第二数据序列中的所述第二数据M[k+j]进行对应更新,得到64位的第三数据序列作为各级MUL运算结果,其中,j为整数且j的取值从0遍历至i-1,所述k为指定比特位,所述k的个数为至少一个。That is to say, the XOR circuits of each level in the 1st-level MUL unit to the 60th-level MUL unit perform XOR operations on the first data V[64-i+j] and the second data M[j], the second data M[1+j], the second data M[3+j], and the second data M[4+j] to obtain XOR results. Then, based on the XOR results, the second data M[k+j] in the second data sequence is correspondingly updated to obtain a 64-bit third data sequence as the MUL operation results of each level, wherein j is an integer and the value of j ranges from 0 to i-1, and the k is a specified bit, and the number of k is at least one.
示例性地,在一些实施例中,当i=1时,j=0,所述第一数据V[64-i+j]为第一数据V[63],所述第二数据M[k+j]为第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4],其中:For example, in some embodiments, when i=1, j=0, the first data V[64-i+j] is the first data V[63], and the second data M[k+j] is the second data M[0], the second data M[1], the second data M[3], and the second data M[4], wherein:
第1级子逻辑电路对应的第1异或电路包括4个异或门,所述4个异或门用于输出所述第一数据V[63]分别与所述第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4]的异或结果。The first XOR circuit corresponding to the first-level sub-logic circuit includes four XOR gates, and the four XOR gates are used to output the XOR results of the first data V[63] and the second data M[0], second data M[1], second data M[3], and second data M[4] respectively.
示例性地,请参阅图4,第1级子逻辑电路中包括第一数据V[63]与所述第二数据M[0]进行异或的第一异或门、第一数据V[63]与所述第二数据M[1]进行异或的第二异或门、第一数据V[63]与所述第二数据M[3]进行异或的第三异或门以及第一数据V[63]与所述第二数据M[4]进行异或的第四异或门。从而可以得到MULxPOW(V,1,C)函数的输出结果。For example, referring to FIG4 , the first-level sub-logic circuit includes a first XOR gate for performing XOR on the first data V[63] and the second data M[0], a second XOR gate for performing XOR on the first data V[63] and the second data M[1], a third XOR gate for performing XOR on the first data V[63] and the second data M[3], and a fourth XOR gate for performing XOR on the first data V[63] and the second data M[4]. Thus, the output result of the MULxPOW(V, 1, C) function can be obtained.
也就是说,对于第1级MUL单元中的第1异或电路,可以实现所述第一数据V[63]分别与所述第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4]的异或运算,得到异或结果。然后基于所述异或结果,更新替换至所述第二数据序列中的所述第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4],得到新的64位的第三数据序列作为第1级MUL单元的MUL运算结果。That is to say, for the first XOR circuit in the first-level MUL unit, the first data V[63] can be XORed with the second data M[0], the second data M[1], the second data M[3], and the second data M[4] to obtain an XOR result. Then, based on the XOR result, the second data M[0], the second data M[1], the second data M[3], and the second data M[4] in the second data sequence are updated and replaced to obtain a new 64-bit third data sequence as the MUL operation result of the first-level MUL unit.
在一些实施例中,当i=2时,j的取值从0遍历至1,所述第一数据V[N-i+j]包括第一数据V[62]、第一数据V[63],所述第二数据M[k+j]包括与所述第一数据V[62]对应的第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4],以及与所述第一数据V[63]对应的第二数据M[1]、第二数据M[2]、第二数据M[4]、第二数据M[5],其中:In some embodiments, when i=2, the value of j ranges from 0 to 1, the first data V[N-i+j] includes first data V[62] and first data V[63], the second data M[k+j] includes second data M[0], second data M[1], second data M[3], and second data M[4] corresponding to the first data V[62], and second data M[1], second data M[2], second data M[4], and second data M[5] corresponding to the first data V[63], wherein:
所述第2异或电路包括8个异或门,所述8个异或门用于输出所述第二数据M[0]与第一数据V[62]、第二数据M[1]与第一数据V[62]和第一数据V[63]、第二数据M[2]与第一数据V[63]、第二数据M[3]与第一数据V[62]、第二数据M[4]与第一数据V[62]和第一数据V[63]、第二数据M[5]与第一数据V[63]的异或结果。示例性地,如图5所示。The second XOR circuit includes 8 XOR gates, and the 8 XOR gates are used to output the XOR results of the second data M[0] and the first data V[62], the second data M[1] and the first data V[62] and the first data V[63], the second data M[2] and the first data V[63], the second data M[3] and the first data V[62], the second data M[4] and the first data V[62] and the first data V[63], and the second data M[5] and the first data V[63]. For example, as shown in FIG5.
也就是说,对于第2级MUL单元中的第2异或电路,可以实现对所述第二数据M[0]与第一数据V[62]、第二数据M[1]与第一数据V[62]和第一数据V[63]、第二数据M[2]与第一数据V[63]、第二数据M[3]与第一数据V[62]、第二数据M[4]与第一数据V[62]和第一数据V[63]、第二数据M[5]与第一数据V[63]分别进行异或运算,得到异或结果。然后基于所述异或结果,更新替换至所述第二数据序列中的所述第二数据M[0]~M[5],得到新的64位的第三数据序列作为第2级MUL单元的MUL运算结果。That is to say, for the second XOR circuit in the second-level MUL unit, the second data M[0] and the first data V[62], the second data M[1] and the first data V[62] and the first data V[63], the second data M[2] and the first data V[63], the second data M[3] and the first data V[62], the second data M[4] and the first data V[62] and the first data V[63], and the second data M[5] and the first data V[63] can be XORed to obtain an XOR result. Then, based on the XOR result, the second data M[0] to M[5] in the second data sequence are updated and replaced to obtain a new 64-bit third data sequence as the MUL operation result of the second-level MUL unit.
同理可以得到第3~60级MUL单元中各级异或电路的实现。Similarly, the implementation of each XOR circuit in the 3rd to 60th level MUL units can be obtained.
在一些实施例中,i的取值为61时,j的取值从0遍历至59,所述第61异或电路包括247个异或门,所述247个异或门用于输出所述第一数据序列中的第一数据V[3+j]与所述第二数据序列中的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j],以及所述第一数据序列中的第一数据V[63]分别与所述第二数据序列中的第二数据M[60]、第二数据M[61]、第二数据M[63]、第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4]的异或结果,该异或结果用于对所述新的N位的数据序列M[0]~M[N-1]中对应的第二数据进行更新,更新后的N位的数据序列作为第61输出结果,其中,j为0~59之间的整数。示例性地,如图11所示。In some embodiments, when the value of i is 61, the value of j ranges from 0 to 59, and the 61st XOR circuit includes 247 XOR gates, and the 247 XOR gates are used to output the XOR results of the first data V[3+j] in the first data sequence and the second data M[j], second data M[1+j], second data M[3+j], and second data M[4+j] in the second data sequence, and the first data V[63] in the first data sequence and the second data M[60], second data M[61], second data M[63], second data M[0], second data M[1], second data M[3], and second data M[4] in the second data sequence, respectively, and the XOR results are used to update the corresponding second data in the new N-bit data sequence M[0] to M[N-1], and the updated N-bit data sequence is used as the 61st output result, wherein j is an integer between 0 and 59. For example, as shown in FIG. 11.
也就是说,对于第61级MUL单元中的第61异或电路,其可以实现所述第一数据序列中的第一数据V[3+j]分别与所述第二数据序列中的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j]的异或运算,其中,j的取值从0遍历至59,以及所述第一数据序列中的第一数据V[63]分别与所述第二数据序列中的第二数据M[60]、第二数据M[61]、第二数据M[63]、第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4]的异或运算,得到异或结果。然后基于所述异或结果,对应更新替换至所述第二数据序列中的所述第二数据,得到新的64位的第三数据序列作为第61级MUL单元的MUL运算结果。That is to say, for the 61st XOR circuit in the 61st MUL unit, it can realize the XOR operation of the first data V[3+j] in the first data sequence with the second data M[j], second data M[1+j], second data M[3+j], and second data M[4+j] in the second data sequence, respectively, where the value of j ranges from 0 to 59, and the first data V[63] in the first data sequence with the second data M[60], second data M[61], second data M[63], second data M[0], second data M[1], second data M[3], and second data M[4] in the second data sequence, respectively, to obtain the XOR result. Then, based on the XOR result, the second data in the second data sequence is correspondingly updated and replaced to obtain a new 64-bit third data sequence as the MUL operation result of the 61st MUL unit.
在一些实施例中,i的取值为62时,j的取值从0遍历至59,所述第62异或电路包括257个异或门,所述257个异或门用于输出所述第一数据序列中的第一数据V[2+j]分别与所述第二数据序列中的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j],所述第一数据序列中的第一数据V[62]分别与所述第二数据序列中的第二数据M[60]、第二数据M[61]、第二数据M[63]、第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4],以及所述第一数据序列中的第一数据V[63]分别与所述第二数据序列中的第二数据M[61]、第二数据M[62]、第二数据M[0]、第二数据M[1]、第二数据M[2]、第二数据M[3]、第二数据M[4]、第二数据M[5]的异或结果,该异或结果用于对所述新的N位的数据序列M[0]~M[N-1]中对应的第二数据进行更新,更新后的N位的数据序列作为第62输出结果,其中,j为0~59之间的整数。示例性地,如图12所示。需注意的是,第二数据M[1]和第二数据M[4]均需与第一数据V[63]进行两次异或运算。In some embodiments, when the value of i is 62, the value of j ranges from 0 to 59, and the 62nd XOR circuit includes 257 XOR gates, and the 257 XOR gates are used to output the first data V[2+j] in the first data sequence and the second data M[j], second data M[1+j], second data M[3+j], and second data M[4+j] in the second data sequence, respectively, and the first data V[62] in the first data sequence and the second data M[60], second data M[61], second data M[63], second data M[0], second data M[ 1], second data M[3], second data M[4], and the first data V[63] in the first data sequence are respectively XORed with the second data M[61], second data M[62], second data M[0], second data M[1], second data M[2], second data M[3], second data M[4], and second data M[5] in the second data sequence, and the XOR result is used to update the corresponding second data in the new N-bit data sequence M[0]~M[N-1], and the updated N-bit data sequence is used as the 62nd output result, wherein j is an integer between 0 and 59. For example, as shown in Figure 12. It should be noted that the second data M[1] and the second data M[4] need to be XORed twice with the first data V[63].
也就是说,对于第62级MUL单元中的第62异或电路,其可以实现所述第一数据序列中的第一数据V[2+j]分别与所述第二数据序列中的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j],其中,j的取值从0遍历至59,所述第一数据序列中的第一数据V[62]分别与所述第二数据序列中的第二数据M[60]、第二数据M[61]、第二数据M[63]、第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4],以及所述第一数据序列中的第一数据V[63]分别与所述第二数据序列中的第二数据M[61]、第二数据M[62]、第二数据M[0]、第二数据M[1]、第二数据M[2]、第二数据M[3]、第二数据M[4]、第二数据M[5]进行异或运算,其中,第二数据M[1]和第二数据M[4]均需与第一数据V[63]进行两次异或运算,得到异或结果。然后基于所述异或结果,对应更新替换至所述第二数据序列中的所述第二数据,得到新的64位的第三数据序列作为第62级MUL单元的MUL运算结果。That is to say, for the 62nd XOR circuit in the 62nd-level MUL unit, it can realize that the first data V[2+j] in the first data sequence is respectively associated with the second data M[j], the second data M[1+j], the second data M[3+j], and the second data M[4+j] in the second data sequence, wherein the value of j ranges from 0 to 59, and the first data V[62] in the first data sequence is respectively associated with the second data M[60], the second data M[61], the second data M[63], and the second data M[0 ], second data M[1], second data M[3], second data M[4], and first data V[63] in the first data sequence are respectively XORed with second data M[61], second data M[62], second data M[0], second data M[1], second data M[2], second data M[3], second data M[4], and second data M[5] in the second data sequence, wherein the second data M[1] and the second data M[4] are both XORed twice with the first data V[63] to obtain an XOR result. Then, based on the XOR result, the corresponding second data in the second data sequence is updated and replaced to obtain a new 64-bit third data sequence as the MUL operation result of the 62nd-level MUL unit.
在一些实施例中,i的取值为63时,j的取值从0遍历至59,所述第63异或电路包括267个异或门,所述267个异或门用于输出所述第一数据序列中的第一数据V[1+j]与所述第二数据序列中的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j],所述第一数据序列中的第一数据V[61]分别与所述第二数据序列中的第二数据M[60]、第二数据M[61]、第二数据M[63]、第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4],所述第一数据序列中的第一数据V[62]分别与所述第二数据序列中的第二数据M[61]、第二数据M[62]、第二数据M[0]、第二数据M[1]、第二数据M[2]、第二数据M[3]、第二数据M[4]、第二数据M[5],以及所述第一数据序列中的第一数据V[63]分别与所述第二数据序列中的第二数据M[62]、第二数据M[63]、第二数据M[1]、第二数据M[2]、第二数据M[3]、第二数据M[4]、第二数据M[5]、第二数据M[6]的异或结果,该异或结果用于对所述新的N位的数据序列M[0]~M[N-1]中对应的第二数据进行更新,更新后的N位的数据序列作为第63输出结果,其中,j为0~59之间的整数。示例性地,如图13所示。需注意的是,第二数据M[1]和第二数据M[4]均需与第一数据V[62]异或两次,第二数据M[2]和第二数据M[5]均需与第一数据V[63]异或两次。In some embodiments, when the value of i is 63, the value of j ranges from 0 to 59, and the 63rd XOR circuit includes 267 XOR gates, and the 267 XOR gates are used to output the first data V[1+j] in the first data sequence and the second data M[j], second data M[1+j], second data M[3+j], and second data M[4+j] in the second data sequence, the first data V[61] in the first data sequence is respectively correlated with the second data M[60], second data M[61], second data M[63], second data M[0], second data M[1], second data M[3], and second data M[4] in the second data sequence, and the first data V[62] in the first data sequence is respectively correlated with the second data M[63], second data M[0], second data M[1], second data M[3], and second data M[4] in the second data sequence. The XOR result of the first data M[61], the second data M[62], the second data M[0], the second data M[1], the second data M[2], the second data M[3], the second data M[4], the second data M[5], and the first data V[63] in the first data sequence and the second data M[62], the second data M[63], the second data M[1], the second data M[2], the second data M[3], the second data M[4], the second data M[5], the second data M[6] in the second data sequence, respectively, is used to update the corresponding second data in the new N-bit data sequence M[0] to M[N-1], and the updated N-bit data sequence is used as the 63rd output result, wherein j is an integer between 0 and 59. For example, as shown in FIG. 13. It should be noted that the second data M[1] and the second data M[4] need to be XORed with the first data V[62] twice, and the second data M[2] and the second data M[5] need to be XORed with the first data V[63] twice.
也就是说,对于第63级MUL单元中的第63异或电路,其可以实现将所述第一数据序列中的第一数据V[1+j]与所述第二数据序列中的第二数据M[j]、第二数据M[1+j]、第二数据M[3+j]、第二数据M[4+j],其中,j的取值从0遍历至59,所述第一数据序列中的第一数据V[61]分别与所述第二数据序列中的第二数据M[60]、第二数据M[61]、第二数据M[63]、第二数据M[0]、第二数据M[1]、第二数据M[3]、第二数据M[4],所述第一数据序列中的第一数据V[62]分别与所述第二数据序列中的第二数据M[61]、第二数据M[62]、第二数据M[0]、第二数据M[1]、第二数据M[2]、第二数据M[3]、第二数据M[4]、第二数据M[5],以及所述第一数据序列中的第一数据V[63]分别与所述第二数据序列中的第二数据M[62]、第二数据M[63]、第二数据M[1]、第二数据M[2]、第二数据M[3]、第二数据M[4]、第二数据M[5]、第二数据M[6]进行异或运算,得到异或结果。其中,第二数据M[1]和第二数据M[4]均需与第一数据V[62]异或两次,第二数据M[2]和第二数据M[5]均需与第一数据V[63]异或两次。然后基于所述异或结果,对应更新替换至所述第二数据序列中的所述第二数据,得到新的64位的第三数据序列作为第63级MUL单元的MUL运算结果。That is to say, for the 63rd XOR circuit in the 63rd level MUL unit, it can realize the first data V[1+j] in the first data sequence and the second data M[j], second data M[1+j], second data M[3+j], second data M[4+j] in the second data sequence, where the value of j ranges from 0 to 59, the first data V[61] in the first data sequence and the second data M[60], second data M[61], second data M[63], second data M[0], second data M[1], second data M[3], second data M[4] in the second data sequence, respectively, the first The first data V[62] in the data sequence is XORed with the second data M[61], the second data M[62], the second data M[0], the second data M[1], the second data M[2], the second data M[3], the second data M[4], and the second data M[5] in the second data sequence, and the first data V[63] in the first data sequence is XORed with the second data M[62], the second data M[63], the second data M[1], the second data M[2], the second data M[3], the second data M[4], the second data M[5], and the second data M[6] in the second data sequence, to obtain an XOR result. Among them, the second data M[1] and the second data M[4] need to be XORed with the first data V[62] twice, and the second data M[2] and the second data M[5] need to be XORed with the first data V[63] twice. Then, based on the XOR result, the second data in the second data sequence is correspondingly updated and replaced to obtain a new 64-bit third data sequence as the MUL operation result of the 63rd-level MUL unit.
在一些实施例中,所述第i级混合运算单元还用于接收64位的密钥序列中的第i位密钥,并基于所述第i位密钥,输出所述第i-1级混合运算结果和所述第i级MUL运算结果的异或结果,或者输出所述第i-1级混合运算结果作为第i级混合运算结果。In some embodiments, the i-th level mixing operation unit is also used to receive the i-th key in a 64-bit key sequence, and based on the i-th key, output the XOR result of the i-1-th level mixing operation result and the i-th level MUL operation result, or output the i-1-th level mixing operation result as the i-th level mixing operation result.
示例性地,请参阅图15,图15示出了本申请提供的一种MUL(V,P,C)函数的计算电路结构。可以看出,本申请相对于相关技术方案,将MULxPOW(V,i,C)的串行计算改变成了并行计算,也即本申请中MULxPOW(V,i,C)每一级的计算只依赖于输入V,从而对MULxPOW(V,i,C)的计算进行了大幅度的时序化简,使得MULxPOW(V,i,C)可以使用并行的方式进行计算,从而提高了MUL(V,P,C)函数计算电路的速度,提高了UIA2运算吞吐量。For example, please refer to FIG. 15 , which shows a calculation circuit structure of a MUL(V, P, C) function provided by the present application. It can be seen that, relative to the related technical solution, the present application changes the serial calculation of MULxPOW(V, i, C) into parallel calculation, that is, the calculation of each level of MULxPOW(V, i, C) in the present application only depends on the input V, thereby greatly simplifying the calculation of MULxPOW(V, i, C), so that MULxPOW(V, i, C) can be calculated in parallel, thereby improving the speed of the MUL(V, P, C) function calculation circuit and improving the UIA2 operation throughput.
可以理解的是,UIA2在3G通信协议中使用,在4G和5G协议改算法改名为128-EIA1与128-NIA1,因此本申请的方案也可以在3G、4G与5G通信协议的硬件实现中共用。It can be understood that UIA2 is used in the 3G communication protocol, and the algorithm is renamed 128-EIA1 and 128-NIA1 in the 4G and 5G protocols. Therefore, the solution of the present application can also be shared in the hardware implementation of 3G, 4G and 5G communication protocols.
本申请实施例提供一种芯片,包括上述数据处理电路。具有与前述一种数据处理电路相同的解释。说明和有益效果,在此不再赘述。The embodiment of the present application provides a chip, including the above-mentioned data processing circuit, and has the same explanation, description and beneficial effects as the above-mentioned data processing circuit, which will not be repeated here.
请参考图16,其示出了本申请实施例提供的一种电子设备的结构框图。该电子设备100可以是智能手机等能够运行应用程序的电子设备。本申请中的电子设备100可以包括一个或多个如下部件:处理器110、存储器120、以及一个或多个程序代码,其中,一个或多个程序代码可以被存储在存储器120中并被配置为由一个或多个处理器110执行,一个或多个程序代码配置用于执行如前述方法实施例所描述的数据处理方法。Please refer to Figure 16, which shows a structural block diagram of an electronic device provided in an embodiment of the present application. The electronic device 100 can be an electronic device such as a smart phone that can run an application. The electronic device 100 in the present application may include one or more of the following components: a processor 110, a memory 120, and one or more program codes, wherein the one or more program codes may be stored in the memory 120 and configured to be executed by one or more processors 110, and the one or more program codes are configured to execute the data processing method described in the aforementioned method embodiment.
处理器110可以包括一个或者多个处理核。处理器110利用各种接口和线路连接整个电子标签100内的各个部分,通过运行或执行存储在存储器120内的指令、程序、代码集或指令集,以及调用存储在存储器120内的数据,执行电子标签100的各种功能和处理数据。可选地,处理器110可以采用数字数据处理(Digital Signal Processing,DSP)、现场可编程门阵列(Field-Programmable Gate Array,FPGA)、可编程逻辑阵列(Programmable LogicArray,PLA)中的至少一种硬件形式来实现。处理器110可集成中央处理器(CentralProcessing Unit,CPU)、数据处理器(Graphics Processing Unit,GPU)和调制解调器等中的一种或几种的组合。其中,CPU主要处理操作系统、用户界面和应用程序等;GPU用于负责显示内容的渲染和绘制;调制解调器用于处理数据处理。可以理解的是,上述调制解调器也可以不集成到处理器110中,单独通过一块通信芯片进行实现。The processor 110 may include one or more processing cores. The processor 110 uses various interfaces and lines to connect the various parts of the entire electronic tag 100, and executes various functions and processes data of the electronic tag 100 by running or executing instructions, programs, code sets or instruction sets stored in the memory 120, and calling data stored in the memory 120. Optionally, the processor 110 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 110 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing display content; and the modem is used to process data. It can be understood that the above-mentioned modem may not be integrated into the processor 110, but may be implemented separately through a communication chip.
存储器120可以包括随机存储器(Random Access Memory,RAM),也可以包括只读存储器(Read-Only Memory)。存储器120可用于存储指令、程序、代码、代码集或指令集。存储器120可包括存储程序区和存储数据区,其中,存储程序区可存储用于实现操作系统的指令、用于实现至少一个功能的指令(比如触控功能、声音播放功能、图像播放功能等)、用于实现下述各个方法实施例的指令等。存储数据区还可以存储电子标签100在使用中所创建的数据(比如电话本、音视频数据、聊天记录数据)等。The memory 120 may include a random access memory (RAM) or a read-only memory (ROM). The memory 120 may be used to store instructions, programs, codes, code sets or instruction sets. The memory 120 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the following various method embodiments, etc. The data storage area may also store data (such as a phone book, audio and video data, chat record data) created by the electronic tag 100 during use.
可以理解,图16所示结构仅为示例,电子设备100还可以包括比图16所示更多或更少的组件,或是具有与图16所示完全不同的配置。本申请实施例对此没有限制。It is understood that the structure shown in FIG16 is only an example, and the electronic device 100 may also include more or fewer components than those shown in FIG16, or have a configuration completely different from that shown in FIG16. The embodiments of the present application are not limited to this.
请参考图17,其示出了本申请实施例提供的一种计算机可读存储介质的结构框图。该计算机可读介质800中存储有程序代码,所述程序代码可被处理器调用执行上述方法实施例中所描述的方法。Please refer to Figure 17, which shows a block diagram of a computer-readable storage medium provided in an embodiment of the present application. The computer-readable medium 800 stores program codes, which can be called by a processor to execute the method described in the above method embodiment.
计算机可读存储介质800可以是诸如闪存、EEPROM(电可擦除可编程只读存储器)、EPROM、硬盘或者ROM之类的电子存储器。可选地,计算机可读存储介质800包括非易失性计算机可读介质(non-transitory computer-readable storage medium)。计算机可读存储介质800具有执行上述方法中的任何方法步骤的程序代码810的存储空间。这些程序代码可以从一个或者多个计算机程序产品中读出或者写入到这一个或者多个计算机程序产品中。程序代码810可以例如以适当形式进行压缩。The computer readable storage medium 800 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk, or a ROM. Optionally, the computer readable storage medium 800 includes a non-transitory computer-readable storage medium. The computer readable storage medium 800 has storage space for program code 810 that performs any method steps in the above method. These program codes can be read from or written to one or more computer program products. The program code 810 can be compressed, for example, in an appropriate form.
最后应说明的是:以上实施例仅用以说明本申请的技术方案,而非对其限制;尽管参照前述实施例对本申请进行了详细的说明,本领域的普通技术人员当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不驱使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
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