CN116483313A - Information processing method, information processing device, electronic equipment and computer readable storage medium - Google Patents
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Abstract
The disclosure provides an information processing method, an information processing device, electronic equipment and a computer readable storage medium, and target information to be processed is obtained; processing the target information based on a target elliptic curve algorithm to obtain a target processing result; the modular operation in the target elliptic curve algorithm comprises the following steps: acquiring first data and second data to be operated; determining a target number value based on a target word length parameter and a target bit value, wherein the target word length parameter comprises a parameter smaller than the word length of a processor, and the target bit value comprises a bit value of a prime field in a target elliptic curve algorithm; converting the first data into a first redundant base representation of the target value; converting the second data into a second redundant base representation of the target value; and performing modular operation on the first redundant base representation and the second redundant base representation to obtain modular operation results of the first data and the second data. In the modular operation process, the method and the device support parallel operation on the redundant base representation, and can improve the modular operation efficiency and the information processing efficiency.
Description
Technical Field
The present disclosure relates to the field of information security technologies, and more particularly, to an information processing method, an apparatus, an electronic device, and a computer readable storage medium.
Background
Currently, in the process of processing information, an elliptic curve cryptography algorithm can be applied to perform corresponding processing on the information, and in the process, a large number of modulo operations in a prime domain are performed, however, the modulo operations in the prime domain consume a large amount of time, and the efficiency of the modulo operations directly determines the information processing efficiency of the elliptic curve cryptography algorithm, so that the information processing efficiency is eventually reduced.
In view of the above, how to improve the information processing efficiency is a problem to be solved by those skilled in the art.
Disclosure of Invention
An object of the present disclosure is to provide an information processing method that can solve the technical problem of how to improve the information processing efficiency to a certain extent. The present disclosure also provides an information processing apparatus, an electronic device, and a computer-readable storage medium.
According to a first aspect of an embodiment of the present disclosure, there is provided an information processing method including:
acquiring target information to be processed;
processing the target information based on a target elliptic curve algorithm to obtain a target processing result;
wherein the modulo operation in the target elliptic curve algorithm comprises:
acquiring first data and second data to be operated;
determining a target numerical value based on a target word length parameter and a target bit value, wherein the target word length parameter comprises a parameter smaller than the word length of a processor, and the target bit value comprises a bit value of a prime field in the target elliptic curve algorithm;
converting the first data into a first redundant base representation of the target value;
converting the second data into a second redundant base representation of the target value;
and performing modular operation on the first redundant base representation and the second redundant base representation to obtain modular operation results of the first data and the second data.
Preferably, the determining the target number value based on the target word length parameter and the target bit value includes:
determining the target number value based on the target word length parameter and the target bit value through a first operation formula;
the first operation formula includes:
wherein l represents the target number value; n represents the target bit value; ρ represents the target word length parameter;representing an upward rounding.
Preferably, the performing a modulo operation on the first redundancy group representation and the second redundancy group representation to obtain a modulo operation result of the first data and the second data includes:
performing modulo addition operation on the first redundant base representation and the second redundant base representation through a second operation formula to obtain modulo addition operation results of the first data and the second data;
the second operation formula includes:
r i ＝a i +b i ；0≤i≤l；
wherein R is 1 Representing the modulo addition result; a represents the first redundancy group representation; b represents the second redundancy group representation; a, a i Representing an ith component of the first redundancy base representation; b i Representing an ith component of the second redundancy base representation; p represents a prime number in the pixel domain; mod represents the remainder operation.
Preferably, the performing a modulo operation on the first redundancy group representation and the second redundancy group representation to obtain a modulo operation result of the first data and the second data includes:
converting prime numbers in the prime domain to a third redundant base representation of the target number value;
performing modular subtraction operation on the first redundant base representation, the second redundant base representation and the third redundant base representation through a third operation formula to obtain modular subtraction operation results of the first data and the second data;
the third operation formula includes:
r i ＝2 k p i +a i -b i ,；0≤i≤l；
wherein R is 2 Representing the modular subtraction result; a represents the first redundancy group representation; b represents the second redundancy group representation; a, a i Representing an ith component of the first redundancy base representation; b i Representing an ith component of the second redundancy base representation; p is p i Representing an ith component of the third redundancy base representation; p represents the prime number; mod represents the remainder operation.
Preferably, the performing a modulo operation on the first redundancy group representation and the second redundancy group representation to obtain a modulo operation result of the first data and the second data includes:
performing modular multiplication operation on the first redundant base representation and the second redundant base representation through a fourth operation formula to obtain modular multiplication operation results of the first data and the second data;
the fourth operation formula includes:
r 0 ＝a 0 b 0 ；
r 2m-2 ＝a m-1 b m-1 ；
wherein R is 3 Representing the modular multiplication operation result; a represents the first redundancy group representation; b represents the second redundancy group representation; a, a i Representing an ith component of the first redundancy base representation; b i Representing the second redundancy group representationi components.
Preferably, the target elliptic curve algorithm comprises an SM2 algorithm.
Preferably, the processing the target information based on the target elliptic curve algorithm to obtain a target processing result includes:
and encrypting, decrypting or signing the target information based on a target elliptic curve algorithm to obtain the target processing result.
According to a second aspect of the embodiments of the present disclosure, there is provided an information processing apparatus including:
the first acquisition module is used for acquiring target information to be processed;
the first processing module is used for processing the target information based on a target elliptic curve algorithm to obtain a target processing result;
the first processing module executes a modular operation process in the target elliptic curve algorithm, which comprises the following steps: acquiring first data and second data to be operated; determining a target numerical value based on a target word length parameter and a target bit value, wherein the target word length parameter comprises a parameter smaller than the word length of a processor, and the target bit value comprises a bit value of a prime field in the target elliptic curve algorithm; converting the first data into a first redundant base representation of the target value; converting the second data into a second redundant base representation of the target value; and performing modular operation on the first redundant base representation and the second redundant base representation to obtain modular operation results of the first data and the second data.
According to a third aspect of embodiments of the present disclosure, there is provided an electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program in the memory to implement the steps of any of the methods as described above.
According to a fourth aspect of embodiments of the present disclosure, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of any of the methods described above.
The information processing method comprises the steps of obtaining target information to be processed; processing the target information based on a target elliptic curve algorithm to obtain a target processing result; the modular operation in the target elliptic curve algorithm comprises the following steps: acquiring first data and second data to be operated; determining a target number value based on a target word length parameter and a target bit value, wherein the target word length parameter comprises a parameter smaller than the word length of a processor, and the target bit value comprises a bit value of a prime field in a target elliptic curve algorithm; converting the first data into a first redundant base representation of the target value; converting the second data into a second redundant base representation of the target value; and performing modular operation on the first redundant base representation and the second redundant base representation to obtain modular operation results of the first data and the second data. In the method, in the modular arithmetic process, the first data and the second data can be correspondingly converted into the first redundant base representation and the second redundant base representation with corresponding numbers based on the target numerical values, modular arithmetic is carried out on the first redundant base representation and the second redundant base representation to obtain modular arithmetic results of the first data and the second data, parallel operation on the redundant base representation is supported, modular arithmetic efficiency can be improved, and information processing efficiency can be improved. The present disclosure also solves the corresponding technical problems with an information processing apparatus, an electronic device, and a computer-readable storage medium.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
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In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present disclosure, and other drawings may be obtained according to the provided drawings without inventive effort to those of ordinary skill in the art.
FIG. 1 is a flow chart of a method of information processing according to an exemplary embodiment;
fig. 2 is a schematic diagram showing a structure of an information processing apparatus according to an exemplary embodiment;
fig. 3 is a block diagram of an electronic device 900, shown in accordance with an exemplary embodiment.
Detailed Description
The following description of the technical solutions in the embodiments of the present disclosure will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.
Referring to fig. 1, fig. 1 is a flowchart illustrating an information processing method according to an exemplary embodiment.
An information processing method according to the present disclosure may include the steps of:
step S101: and obtaining target information to be processed.
It is understood that the type of the target information may be determined according to an application scenario, for example, the target information may be voice information, video information, image information, or the like.
Step S102: processing the target information based on a target elliptic curve algorithm to obtain a target processing result; the modular operation in the target elliptic curve algorithm comprises the following steps: acquiring first data and second data to be operated; determining a target number value based on a target word length parameter and a target bit value, wherein the target word length parameter comprises a parameter smaller than the word length of a processor, and the target bit value comprises a bit value of a prime field in a target elliptic curve algorithm; converting the first data into a first redundant base representation of the target value; converting the second data into a second redundant base representation of the target value; and performing modular operation on the first redundant base representation and the second redundant base representation to obtain modular operation results of the first data and the second data.
It can be understood that after the target information to be processed is acquired, the target information can be processed based on the target elliptic curve algorithm, so as to obtain a target processing result. For example, the target information is encrypted, decrypted or signed based on an SM2 algorithm and the like, so that a target processing result is obtained.
It should be noted that, during modulo operation in the objective elliptic curve algorithm of the present disclosure, because the redundant base representation is used to represent the first data and the second data, and the redundant base representation is smaller than the word length of the processor, the carry can be preserved during modulo operation on the first redundant base representation and the second redundant base representation, while performing operations on all branches, delaying carry propagation.
It may be appreciated that in determining the target number based on the target word length parameter and the target bit value, the target number may be determined based on the target word length parameter and the target bit value by the first operation formula;
the first operation formula includes:
wherein l represents a target number; n represents a target bit value; ρ represents a target word length parameter;representing an upward rounding.
For ease of understanding, the SM2 algorithm is taken as an example, and the elliptic curve parameter recommended for the SM2 algorithm is 256-bit prime field F p If ρ=29 is selected for element a above, l=9 redundancy base branches (a 0 ,a 1 ,a 2 ,a 3 ,a 4 ,a 5 ,a 6 ,a 7 ,a 8 ) The representation is:
A＝a 0 +2 29 a 1 +2 58 a 2 +2 87 a 3 +2 116 a 4 +2 145 a 5 +2 174 a 6 +2 203 a 7 +2 232 a 8 ；
i.e. the0≤a i ＜2 (i+1)ρ-iρ The method comprises the steps of carrying out a first treatment on the surface of the p represents a prime number in the pixel domain; mod represents the remainder operation;
and under the application scene, each redundant base branch can be put into a 64-bit register, and all operations on a prime field are respectively executed for each branch.
It can be understood that in the process of performing modulo operation on the first redundancy base representation and the second redundancy base representation to obtain the modulo operation result of the first data and the second data, when the modulo operation is required, the modulo operation can be performed on the first redundancy base representation and the second redundancy base representation through the second operation formula to obtain the modulo operation result of the first data and the second data;
the second operation formula includes:
r i ＝a i +b i ；0≤i≤l；
wherein R is 1 Representing the modulo addition result; a represents a first redundancy group; b represents a second redundancy group; a, a i Representing an ith component of the first redundancy base representation; b i Representing an ith component of the second redundancy base representation; p represents a prime number in the pixel domain; mod represents the remainder operation.
It can be understood that, in the process of performing modular operation on the first redundant base representation and the second redundant base representation to obtain the modular operation result of the first data and the second data, when the modular subtraction operation is required, and when the positive modular subtraction operation result is required, the prime number in the pixel domain can be converted into the third redundant base representation of the target number; performing modular subtraction operation on the first redundant base representation, the second redundant base representation and the third redundant base representation through a third operation formula to obtain modular subtraction operation results of the first data and the second data;
the third operational formula includes:
r i ＝2 k p i +a i -b i ,；0≤i≤l；
wherein R is 2 Representing the modular subtraction result; a represents a first redundancy group; b represents a second redundancy group; a, a i Representing an ith component of the first redundancy base representation; b i Representing an ith component of the second redundancy base representation; p is p i Representing an ith component of the third redundancy base representation; p represents a prime number; mod represents the remainder operation.
It can be understood that in the process of performing modular operation on the first redundancy base representation and the second redundancy base representation to obtain modular operation results of the first data and the second data, when modular multiplication operation is required, large-number multiplication of a two-layer recursive structure can be designed, wherein each layer adopts expanded multiple-term Karatsuba multiplication to reduce the time complexity of multiplication operation, simplify the multiplication structure, reduce the time complexity of addition operation, and through verification, when the modular operation efficiency is applied to the prime field operation on the SM2 algorithm, the modular operation efficiency is superior to that of the existing large-number operation library, parallel implementation is supported, so that the modular operation is beneficial to the realization of pure software acceleration, assembly and hardware acceleration, and modular multiplication operation can be performed on the first redundancy base representation and the second redundancy base representation through a fourth operation formula to obtain the modular multiplication operation results of the first data and the second data;
the fourth operational formula includes:
r 0 ＝a 0 b 0 ；
r 2m-2 ＝a m-1 b m-1 ；
wherein R is 3 Representing the modular multiplication operation result; a represents a first redundancy group; b represents a second redundancy group; a, a i Representing an ith component of the first redundancy base representation; b i Representing the ith component of the second redundancy base representation.
For ease of understanding, assuming the target number is 3, the extended 3-term Karatsuba multiplication may include the steps of:
calculating r 0 ＝a 0 b 0 ；
Calculating r 1 ＝(a 0 +a 1 )(b 0 +b 1 )-a 0 b 0 -a 1 b 1 ；
Calculating r 2 ＝(a 0 +a 2 )(b 0 +b 2 )+a 1 b 1 -a 0 b 0 -a 2 b 2 ；
Calculating r 3 ＝(a 1 +a 2 )(b 1 +b 2 )-a 1 b 1 -a 2 b 2 ；
Calculating r 4 ＝a 2 b 2 ；
For the SM2 algorithm, when the target number is 9, the 9 branches may be divided into 3 groups, each group includes 3 branches, and the modular multiplication operation between the data a and the data B may include the following steps:
calculation (c) 0 ,c 1 ,c 2 )＝(a 0 +a 3 ,a 1 +a 4 ,a 2 +a 5 )；
Calculation (d) 0 ,d 1 ,d 2 )＝(b 0 +b 3 ,b 1 +b 4 ,b 2 +b 5 )；
Calculation (c) 3 ,c 4 ,c 5 )＝(a 0 +a 6 ,a 1 +a 7 ,a 2 +a 8 )；
Calculation (d) 3 ,d 4 ,d 5 )＝(b 0 +b 6 ,b 1 +b 7 ,b 2 +b 8 )；
Calculation (c) 6 ,c 7 ,c 8 )＝(a 3 +a 6 ,a 4 +a 7 ,a 5 +a 8 )；
Calculation (d) 6 ,d 7 ,d 8 )＝(b 3 +b 6 ,b 4 +b 7 ,b 5 +b 8 )；
Calculation (x) 0 ,x 1 ,x 2 ,x 3 ,x 4 )＝Karatsuba 3 ((a 0 ,a 1 ,a 2 ),(b 0 ,b 1 ,b 2 ))；
Calculation (y) 0 ,y 1 ,y 2 ,y 3 ,y 4 )＝Karatsuba 3 ((a 3 ,a 4 ,a 5 ),(b 3 ,b 4 ,b 5 ))；
Calculation (z) 0 ,z 1 ,z 2 ,z 3 ,z 4 )＝Karatsuba 3 ((a 6 ,a 7 ,a 8 ),(b 6 ,b 7 ,b 8 ))；
Calculation (u) 0 ,u 1 ,u 2 ,u 3 ,u 4 )＝Karatsuba 3 ((c 0 ,c 1 ,c 2 ),(d 0 ,d 1 ,d 2 ))；
Calculation (v) 0 ,v 1 ,v 2 ,v 3 ,v 4 )＝Karatsuba 3 ((c 3 ,c 4 ,c 5 ),(d 3 ,d 4 ,d 5 ))；
Calculation (w) 0 ,w 1 ,w 2 ,w 3 ,w 4 )＝Karatsuba 3 ((c 6 ,c 7 ,c 8 ),(d 6 ,d 7 ,d 8 ))；
for i＝0 to 4
u i ＝u i -x i -y i ；
v i ＝v i -x i -z i +y i ；
w i ＝w i -y i -z i ；
for i＝0 to 1
u i ＝u i +x i+3 ；
v i ＝v i +u i+3 ；
w i ＝w i +v i+3 ；
z i ＝z i +w i+3 ；
After the 3-item Karatsuba multiplication of the extension is completed by two layers of recursion, the obtained multiplication result is subjected to a mode of using SM2 modulus p=2 256 -2 224 -2 96 +2 64 1 is a sparse prime number, the higher 8 of the 17 branches (weight coefficient greater than 261) (w 0 ,w 1 ,w 2 ,z 0 ,z 1 ,z 2 ,z 3 ,z 4 ) The shift and add-subtract operation is utilized to quickly reduce the length of each branch to within 29 bits by using the shift and add-subtract operation to the lower 9 branches (the weight coefficient is smaller than 261), and then the modular reduction operation is completed.
The information processing method comprises the steps of obtaining target information to be processed; processing the target information based on a target elliptic curve algorithm to obtain a target processing result; the modular operation in the target elliptic curve algorithm comprises the following steps: acquiring first data and second data to be operated; determining a target number value based on a target word length parameter and a target bit value, wherein the target word length parameter comprises a parameter smaller than the word length of a processor, and the target bit value comprises a bit value of a prime field in a target elliptic curve algorithm; converting the first data into a first redundant base representation of the target value; converting the second data into a second redundant base representation of the target value; and performing modular operation on the first redundant base representation and the second redundant base representation to obtain modular operation results of the first data and the second data. In the method, in the modular arithmetic process, the first data and the second data can be correspondingly converted into the first redundant base representation and the second redundant base representation with corresponding numbers based on the target numerical values, modular arithmetic is carried out on the first redundant base representation and the second redundant base representation to obtain modular arithmetic results of the first data and the second data, parallel operation on the redundant base representation is supported, modular arithmetic efficiency can be improved, and information processing efficiency can be improved.
Referring to fig. 2, fig. 2 is a schematic diagram showing a structure of an information processing apparatus according to an exemplary embodiment.
An information processing apparatus 200 according to the present disclosure may include:
a first obtaining module 210, configured to obtain target information to be processed;
the first processing module 220 is configured to process the target information based on a target elliptic curve algorithm to obtain a target processing result;
the first processing module executes a modular operation process in a target elliptic curve algorithm, which comprises the following steps: acquiring first data and second data to be operated; determining a target number value based on a target word length parameter and a target bit value, wherein the target word length parameter comprises a parameter smaller than the word length of a processor, and the target bit value comprises a bit value of a prime field in a target elliptic curve algorithm; converting the first data into a first redundant base representation of the target value; converting the second data into a second redundant base representation of the target value; and performing modular operation on the first redundant base representation and the second redundant base representation to obtain modular operation results of the first data and the second data.
An information processing apparatus 200 according to the present disclosure, a first processing module may be configured to: determining a target numerical value based on the target word length parameter and the target bit value through a first operation formula;
the first operation formula includes:
wherein l represents a target number; n represents a target bit value; ρ represents a target word length parameter;representing an upward rounding.
An information processing apparatus 200 according to the present disclosure, a first processing module may be configured to: performing modular addition operation on the first redundant base representation and the second redundant base representation through a second operation formula to obtain a modular addition operation result of the first data and the second data;
the second operation formula includes:
r i ＝a i +b i ；0≤i≤l；
wherein R is 1 Representing the modulo addition result; a represents a first redundancy group; b represents a second redundancy group; a, a i Representing an ith component of the first redundancy base representation; b i Representing an ith component of the second redundancy base representation; p represents a prime number in the pixel domain; mod represents the remainder operation.
An information processing apparatus 200 according to the present disclosure, a first processing module may be configured to: converting prime numbers in the prime domain to a third redundant base representation of the target number; performing modular subtraction operation on the first redundant base representation, the second redundant base representation and the third redundant base representation through a third operation formula to obtain modular subtraction operation results of the first data and the second data;
the third operational formula includes:
r i ＝2 k p i +a i -b i ,；0≤i≤l；
wherein R is 2 Representing the modular subtraction result; a represents a first redundancy group; b represents a second redundancy group; a, a i Representing an ith component of the first redundancy base representation; b i Representing an ith component of the second redundancy base representation; p is p i Representing an ith component of the third redundancy base representation; p represents a prime number; mod represents the remainder operation.
An information processing apparatus 200 according to the present disclosure, a first processing module may be configured to: performing modular multiplication operation on the first redundant base representation and the second redundant base representation through a fourth operation formula to obtain modular multiplication operation results of the first data and the second data;
the fourth operational formula includes:
r 0 ＝a 0 b 0 ；
r 2m-2 ＝a m-1 b m-1 ；
wherein R is 3 Representing the modular multiplication operation result; a represents a first redundancy group; b represents a second redundancy group; a, a i Representing an ith component of the first redundancy base representation; b i Representing the ith component of the second redundancy base representation.
An information processing apparatus 200 to which the present disclosure relates may include an SM2 algorithm.
An information processing apparatus 200 according to the present disclosure, a first processing module may be configured to: and encrypting, decrypting or signing the target information based on the target elliptic curve algorithm to obtain a target processing result.
Fig. 3 is a block diagram of an electronic device 900, shown in accordance with an exemplary embodiment. As shown in fig. 3, the electronic device 900 may include: processor 901, memory 902. The electronic device 900 may also include one or more of a multimedia component 903, an input/output (I/O) interface 904, and a communication component 905.
The processor 901 is configured to control the overall operation of the electronic device 900, so as to complete all or part of the steps in the information processing method described above. The memory 902 is used to store various types of data to support operations at the electronic device 900, which may include, for example, instructions for any application or method operating on the electronic device 900, as well as application-related data, such as contact data, transceived messages, pictures, audio, video, and so forth. The Memory 902 may be implemented by any type or combination of volatile or nonvolatile Memory devices, such as static random access Memory (Static Random Access Memory, SRAM for short), electrically erasable programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM for short), erasable programmable Read-Only Memory (Erasable Programmable Read-Only Memory, EPROM for short), programmable Read-Only Memory (Programmable Read-Only Memory, PROM for short), read-Only Memory (ROM for short), magnetic Memory, flash Memory, magnetic disk, or optical disk. The multimedia component 903 may include a screen and audio components. Wherein the screen may be, for example, a touch screen, the audio component being for outputting and/or inputting audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signal may be further stored in the memory 902 or transmitted through the communication component 905. The audio assembly further comprises at least one speaker for outputting audio signals. The I/O interface 904 provides an interface between the processor 901 and other interface modules, which may be a keyboard, mouse, buttons, etc. These buttons may be virtual buttons or physical buttons. The communication component 905 is used for wired or wireless communication between the electronic device 900 and other devices. Wireless communication, such as Wi-Fi, bluetooth, near field communication (Near Field Communication, NFC for short), 2G, 3G or 4G, or a combination of one or more thereof, the corresponding communication component 905 may thus comprise: wi-Fi module, bluetooth module, NFC module.
In an exemplary embodiment, the electronic device 900 may be implemented by one or more application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASIC), digital signal processors (Digital Signal Processor, abbreviated as DSP), digital signal processing devices (Digital Signal Processing Device, abbreviated as DSPD), programmable logic devices (Programmable Logic Device, abbreviated as PLD), field programmable gate arrays (Field Programmable Gate Array, abbreviated as FPGA), controllers, microcontrollers, microprocessors, or other electronic components for performing the information processing methods described above.
In another exemplary embodiment, a computer readable storage medium is also provided, which includes program instructions that, when executed by a processor, implement the steps of the information processing method described above. For example, the computer readable storage medium may be the memory 902 including program instructions described above, which are executable by the processor 901 of the electronic device 900 to perform the information processing method described above.
It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An information processing method, characterized by comprising:
acquiring target information to be processed;
processing the target information based on a target elliptic curve algorithm to obtain a target processing result;
wherein the modulo operation in the target elliptic curve algorithm comprises:
acquiring first data and second data to be operated;
determining a target numerical value based on a target word length parameter and a target bit value, wherein the target word length parameter comprises a parameter smaller than the word length of a processor, and the target bit value comprises a bit value of a prime field in the target elliptic curve algorithm;
converting the first data into a first redundant base representation of the target value;
converting the second data into a second redundant base representation of the target value;
and performing modular operation on the first redundant base representation and the second redundant base representation to obtain modular operation results of the first data and the second data.
2. The method of claim 1, wherein the determining the target number value based on the target word length parameter, the target bit value, comprises:
determining the target number value based on the target word length parameter and the target bit value through a first operation formula;
the first operation formula includes:
wherein l represents the target number value; n represents the target bit value; ρ represents the target word length parameter;representing an upward rounding.
3. The method of claim 2, wherein the performing a modulo operation on the first redundancy base representation and the second redundancy base representation to obtain a modulo operation result of the first data and the second data comprises:
performing modulo addition operation on the first redundant base representation and the second redundant base representation through a second operation formula to obtain modulo addition operation results of the first data and the second data;
the second operation formula includes:
r i ＝a i +b i ；0≤i≤l；
wherein R is 1 Representing the modulo addition result; a represents the first redundancy group representation; b represents the second redundancy group representation; a, a i Representing an ith component of the first redundancy base representation; b i Representing an ith component of the second redundancy base representation; p represents a prime number in the pixel domain; mod represents the remainder operation.
4. The method of claim 2, wherein the performing a modulo operation on the first redundancy base representation and the second redundancy base representation to obtain a modulo operation result of the first data and the second data comprises:
converting prime numbers in the prime domain to a third redundant base representation of the target number value;
performing modular subtraction operation on the first redundant base representation, the second redundant base representation and the third redundant base representation through a third operation formula to obtain modular subtraction operation results of the first data and the second data;
the third operation formula includes:
r i ＝2 k p i +a i -b i ,；0≤i≤l；
wherein R is 2 Representing the modular subtraction result; a represents the first redundancy group representation; b represents the second redundancy group representation; a, a i Representing an ith component of the first redundancy base representation; b i Representing an ith component of the second redundancy base representation; p is p i Representing an ith component of the third redundancy base representation; p represents the prime number; mod represents the remainder operation.
5. The method of claim 2, wherein the performing a modulo operation on the first redundancy base representation and the second redundancy base representation to obtain a modulo operation result of the first data and the second data comprises:
performing modular multiplication operation on the first redundant base representation and the second redundant base representation through a fourth operation formula to obtain modular multiplication operation results of the first data and the second data;
the fourth operation formula includes:
r 0 ＝a 0 b 0 ；
r 2m-2 ＝a m-1 b m-1 ；
wherein R is 3 Representing the modular multiplication operation result; a represents the first redundancy group representation; b represents the second redundancy group representation; a, a i Representing an ith component of the first redundancy base representation; b i Representing the ith component of the second redundancy base representation.
6. The method of any one of claims 1 to 5, wherein the target elliptic curve algorithm comprises an SM2 algorithm.
7. The method of claim 6, wherein the processing the target information based on the target elliptic curve algorithm to obtain a target processing result comprises:
and encrypting, decrypting or signing the target information based on a target elliptic curve algorithm to obtain the target processing result.
8. An information processing apparatus, characterized by comprising:
the first acquisition module is used for acquiring target information to be processed;
the first processing module is used for processing the target information based on a target elliptic curve algorithm to obtain a target processing result;
the first processing module executes a modular operation process in the target elliptic curve algorithm, which comprises the following steps: acquiring first data and second data to be operated; determining a target numerical value based on a target word length parameter and a target bit value, wherein the target word length parameter comprises a parameter smaller than the word length of a processor, and the target bit value comprises a bit value of a prime field in the target elliptic curve algorithm; converting the first data into a first redundant base representation of the target value; converting the second data into a second redundant base representation of the target value; and performing modular operation on the first redundant base representation and the second redundant base representation to obtain modular operation results of the first data and the second data.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program in the memory to implement the steps of the method of any one of claims 1 to 7.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method according to any one of claims 1 to 7.
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