CN113964190A - High-mobility p-type polysilicon gate LDMOS device and manufacturing method thereof - Google Patents
High-mobility p-type polysilicon gate LDMOS device and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a p-type polysilicon gate LDMOS device with high mobility and a manufacturing method thereof. The high-mobility p-type polysilicon gate LDMOS device comprises a semiconductor substrate and a grid electrode, wherein a body region contact region and a drift region are distributed in the semiconductor substrate, a source region and a drain region are respectively formed in the body region contact region and the drift region, a channel region is further distributed in the semiconductor substrate, a first doped region is further formed in the channel region, the semiconductor substrate, the grid electrode, the body region contact region and the channel region are of a first doping type, and the source region, the drain region, the drift region and the first doped region are of a second doping type. According to the high-mobility P-type polysilicon gate LDMOS device, the n-type lightly doped region is arranged in the P-type doped channel region, so that the influence of surface defects on the electron mobility is reduced, the influence of a hot carrier injection effect on the surface of a semiconductor device and a grid oxide layer is reduced, and the quality factors of the saturation current of the device and the reliability of the hot carrier injection are improved.
Description
Technical Field
The invention relates to an LDMOS device, in particular to a p-type polysilicon gate LDMOS device with high mobility and a manufacturing method thereof, and belongs to the technical field of semiconductors.
Background
The structure of a conventional N-type LDMOS device is shown in fig. 1, in which 100 is an N-type polysilicon gate, 200 is a gate oxide layer, 50 is a heavily doped N-type source region, 20 is a lightly doped N-type drift region, 40 is an N-type heavily doped drain region, 30 is a p-type heavily doped body contact region, 60 is a p-type channel region, and 10 is a p-type substrate.
The structure of fig. 1 above belongs to an enhancement mode device, and the threshold voltage is greater than zero. For the conventional device structure shown in fig. 1, the device is turned on by changing the voltage of the gate to control the device to be turned on and off, when the gate voltage exceeds the threshold voltage, the channel surface is reversely turned on, the device is turned on, and when the gate voltage is less than the threshold voltage, the channel is depleted or accumulated, and the device is turned off. For the enhancement device, under the conduction condition, the inversion layer on the surface of the channel has a large amount of electrons, which are easily affected by surface defects, so that the electron mobility is reduced, and the performance of the device is affected
Disclosure of Invention
The invention mainly aims to provide a p-type polysilicon gate LDMOS device with high mobility and a manufacturing method thereof, so as to overcome the defects in the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:
the embodiment of the invention provides a p-type polysilicon gate LDMOS device with high mobility, which comprises a semiconductor substrate and a gate, wherein a body region contact region and a drift region are distributed in the semiconductor substrate, a source region and a drain region are respectively formed in the body region contact region and the drift region, the source region and the drain region are respectively matched with a source electrode and a drain electrode, a channel region is further distributed in the semiconductor substrate, the channel region is positioned below the gate, a first doped region is further formed in a region, close to the surface of the semiconductor substrate, in the channel region, and is electrically contacted with or electrically combined with the source region, the semiconductor substrate, the gate, the body region contact region and the channel region are of a first doping type, and the source region, the drain region, the drift region and the first doped region are of a second doping type;
when the gate voltage exceeds the threshold voltage, the inversion layer near the source region will first occur below the first doped region when the channel region is inverted to form an electron layer.
Further, the high-mobility p-type polysilicon gate LDMOS device comprises a p-type semiconductor substrate and a p-type doped gate, wherein a p-type heavily doped body contact region and an n-type lightly doped drift region are distributed in the p-type semiconductor substrate, an n-type heavily doped source region and an n-type heavily doped drain region are respectively formed in the p-type heavily doped body contact region and the n-type lightly doped drift region, the n-type heavily doped source region and the n-type heavily doped drain region are respectively matched with a source electrode and a drain electrode, a p-type channel region is also distributed in the p-type semiconductor substrate, the p-type channel region is positioned below the p-type doped gate, an n-type lightly doped region is also formed in a region close to the surface of the p-type semiconductor substrate in the p-type channel region, and the n-type lightly doped region is also in electrical contact with or in electrical combination with the n-type heavily doped source region; when the voltage of the p-type doped grid electrode exceeds the threshold voltage and the inversion layer of the p-type channel region is inverted to form an electronic layer, the inversion layer close to the n-type heavily doped source region is firstly generated below the n-type lightly doped region.
The embodiment of the invention also provides a manufacturing method of the p-type polysilicon gate LDMOS device with high mobility, which comprises the following steps:
providing a semiconductor substrate, and manufacturing a grid electrode on the semiconductor substrate;
manufacturing a body region contact region, a drift region and a channel region on the semiconductor substrate, manufacturing a source region and a drain region in the body region contact region and the drift region respectively, wherein the source region and the drain region are matched with a source electrode and a drain electrode respectively, and the channel region is positioned below the grid electrode;
and manufacturing a first doping region in the channel region close to the surface of the semiconductor substrate, wherein at least a partial region of the channel region is covered by the first doping region, and the first doping region is electrically contacted or combined with the source region.
Compared with the prior art, the invention has the advantages that: according to the high-mobility P-type polysilicon gate LDMOS device, the N-type lightly doped region is arranged in the P-type doped channel region, so that the doping distribution of the channel region is changed; when the device starts to be conducted, the inversion layer is positioned below the n-type lightly doped region, and the inversion layer is gradually thickened and is close to the surface of the channel region along with the increase of the grid voltage; when the device works, the inversion layer is positioned in the semiconductor substrate and is far away from the surface, so that the influence of surface defects on the electron mobility is reduced, meanwhile, the influence of hot carrier injection effect on the surface of the semiconductor device and a grid oxide layer is reduced, and the quality factors of the saturation current and the hot carrier injection reliability of the device are further improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a prior art structure of an n-type LDMOS device;
FIG. 2 is a schematic diagram of a high mobility p-type polysilicon gate LDMOS device in accordance with an exemplary embodiment of the present invention;
FIG. 3 is a schematic diagram of another high mobility p-type polysilicon gate LDMOS device in accordance with an exemplary embodiment of the present invention;
FIG. 4 is a schematic diagram of a process flow for fabricating a high mobility p-type polysilicon gate LDMOS device in accordance with an exemplary embodiment of the present invention;
fig. 5 is a schematic diagram of a process flow for fabricating a high mobility p-type polysilicon gate LDMOS device in an exemplary embodiment of the invention.
Detailed Description
In view of the deficiencies in the prior art, the inventors of the present invention have made extensive studies and extensive practices to provide technical solutions of the present invention. The technical solution, its implementation and principles, etc. will be further explained as follows.
In order to overcome the problems in the prior art, the embodiment of the invention provides a P-type polysilicon gate LDMOS device with high mobility, wherein an n-type lightly doped region is formed in a P-type doped channel region to change the doping distribution of the channel region; when the device starts to be conducted, the inversion layer is positioned below the n-type lightly doped region, and the inversion layer is gradually thickened and is close to the surface of the channel region along with the increase of the grid voltage; when the device works, the inversion layer is positioned in the semiconductor substrate and is far away from the surface, so that the influence of surface defects on the electron mobility is reduced, meanwhile, the influence of hot carrier injection effect on the surface of the semiconductor device and a grid oxide layer is reduced, and further, the quality factors of the saturation current and the hot carrier injection reliability of the device are improved.
The embodiment of the invention provides a p-type polysilicon gate LDMOS device with high mobility, which comprises a semiconductor substrate and a gate, wherein a body region contact region and a drift region are distributed in the semiconductor substrate, a source region and a drain region are respectively formed in the body region contact region and the drift region, the source region and the drain region are respectively matched with a source electrode and a drain electrode, a channel region is further distributed in the semiconductor substrate, the channel region is positioned below the gate, a first doped region is further formed in a region, close to the surface of the semiconductor substrate, in the channel region, and is electrically contacted with or electrically combined with the source region, the semiconductor substrate, the gate, the body region contact region and the channel region are of a first doping type, and the source region, the drain region, the drift region and the first doped region are of a second doping type;
when the gate voltage exceeds the threshold voltage, the inversion layer near the source region will first occur below the first doped region when the channel region is inverted to form an electron layer.
Furthermore, a second doped region is formed in the channel region or the region close to the surface of the semiconductor substrate in the first doped region, the second doped region is of the first doping type, and the second doped region is electrically contacted with or electrically combined with the first doped region and the drift region.
Further, at least a local region of the first doped region is masked by the second doped region.
Further, the doping concentration of the first doping region and the second doping region is 1 x 1011 to 6 x 1012cm2。
Furthermore, an oxide layer is formed on the surface of the semiconductor substrate, and the grid electrode is arranged above the oxide layer.
Further, the high-mobility p-type polysilicon gate LDMOS device comprises a p-type semiconductor substrate and a p-type doped gate, wherein a p-type heavily doped body contact region and an n-type lightly doped drift region are distributed in the p-type semiconductor substrate, an n-type heavily doped source region and an n-type heavily doped drain region are respectively formed in the p-type heavily doped body contact region and the n-type lightly doped drift region, the n-type heavily doped source region and the n-type heavily doped drain region are respectively matched with a source electrode and a drain electrode, a p-type channel region is also distributed in the p-type semiconductor substrate, the p-type channel region is positioned below the p-type doped gate, an n-type lightly doped region is also formed in a region close to the surface of the p-type semiconductor substrate in the p-type channel region, and the n-type lightly doped region is also in electrical contact with or in electrical combination with the n-type heavily doped source region; when the voltage of the p-type doped grid electrode exceeds the threshold voltage and the inversion layer of the p-type channel region is inverted to form an electronic layer, the inversion layer close to the n-type heavily doped source region is firstly generated below the n-type lightly doped region.
The embodiment of the invention also provides a manufacturing method of the p-type polysilicon gate LDMOS device with high mobility, which comprises the following steps:
providing a semiconductor substrate, and manufacturing a grid electrode on the semiconductor substrate;
manufacturing a body region contact region, a drift region and a channel region on the semiconductor substrate, manufacturing a source region and a drain region in the body region contact region and the drift region respectively, wherein the source region and the drain region are matched with a source electrode and a drain electrode respectively, and the channel region is positioned below the grid electrode;
and manufacturing a first doping region in the channel region close to the surface of the semiconductor substrate, wherein at least a partial region of the channel region is covered by the first doping region, and the first doping region is electrically contacted or combined with the source region.
Furthermore, the manufacturing method also comprises the following steps; and manufacturing a second doped region in a region close to the surface of the semiconductor substrate in the channel region or in a region of the first doped region close to the surface of the semiconductor substrate, wherein at least a partial region of the first doped region is covered by the second doped region, and the second doped region is electrically contacted or combined with the first doped region and the drift region.
Further, the manufacturing method specifically comprises the following steps; the semiconductor substrate comprises a body region contact region, a drift region, a source region, a drain region, a first doped region and a second doped region, wherein the body region contact region and the drift region are formed by local processing of a semiconductor substrate in an ion implantation and thermal diffusion mode, the source region is formed by local processing of the body region contact region in an ion implantation mode, the drain region is formed by local processing of the drift region in an ion implantation mode, the first doped region is formed by local processing of a channel region in an ion implantation mode, and the second doped region is formed by local processing of the channel region or the first doped region in an ion implantation mode.
Further, the manufacturing method specifically comprises the following steps: and manufacturing an oxide layer on the surface of the semiconductor substrate, and then manufacturing a grid electrode on the oxide layer.
Furthermore, the material of the grid electrode comprises polysilicon.
Furthermore, the material of the oxide layer comprises silicon oxide, and the thickness of the oxide layer is 0.01-0.06 nm.
The technical solution, the implementation process and the principle thereof will be further explained with reference to the accompanying drawings and specific embodiments, it should be noted that the ion implantation process adopted in the embodiments of the present invention is a process known to those skilled in the art, and the specific process parameter conditions thereof may be adjusted according to specific situations, and are not limited herein.
Referring to fig. 2, a p-type polysilicon gate LDMOS device with high mobility according to an exemplary embodiment of the present invention includes a p-type semiconductor substrate 10 and a p-type doped gate 100, a p-type heavily doped body contact region 30 and an n-type lightly doped drift region 20 are distributed in the p-type semiconductor substrate 10, an n-type heavily doped source region 50 and an n-type heavily doped drain region 40 are respectively formed in the p-type heavily doped body contact region 30 and the n-type lightly doped drift region 20, the n-type heavily doped source region 50 and the n-type heavily doped drain region 40 are respectively matched with a source and a drain, a p-type channel region 60 is further distributed in the p-type semiconductor substrate 10, the p-type channel region 60 is located below the p-type doped gate 100, and an n-type lightly doped region 70 is further formed in a local region of the p-type channel region 60 near the surface of the p-type semiconductor substrate 10, the n-type lightly doped region 70 is further electrically contacted with or electrically combined with the n-type heavily doped source region 50; when the p-type channel region is inverted to form an electron layer after the voltage of the p-type doped gate 100 exceeds the threshold voltage, an inversion layer near the n-type heavily doped source region 50 will first occur below the n-type lightly doped region 70.
Specifically, a gate oxide layer 200 is further disposed on the p-type semiconductor substrate 10, the p-type doped gate 100 is disposed on the gate oxide layer 200, wherein the p-type doped gate 100 is made of polysilicon, the gate oxide layer 200 is made of silicon dioxide, and the p-type semiconductor substrate 10 may be made of silicon.
Referring to fig. 3, a p-type polysilicon gate LDMOS device with high mobility according to an exemplary embodiment of the present invention includes a p-type semiconductor substrate 10 and a p-type doped gate 100, a p-type heavily doped body contact region 30 and an n-type lightly doped drift region 20 are distributed in the p-type semiconductor substrate 10, an n-type heavily doped source region 50 and an n-type heavily doped drain region 40 are respectively formed in the p-type heavily doped body contact region 30 and the n-type lightly doped drift region 20, the n-type heavily doped source region 50 and the n-type heavily doped drain region 40 are respectively matched with a source and a drain, a p-type channel region 60 is further distributed in the p-type semiconductor substrate 10, the p-type channel region 60 is located below the p-type doped gate 100, and an n-type lightly doped region 70 and an n-type lightly doped region 40 are further formed in a local region of the p-type channel region 60 close to the surface of the p-type semiconductor substrate 10, A p-type doped region 80, at least a partial region of the n-type lightly doped region 70 is covered by the p-type doped region 80, the n-type lightly doped region 70 is further electrically contacted or electrically combined with the n-type heavily doped source region 50, and the p-type doped region 80 is electrically contacted or electrically combined with the n-type lightly doped region 70 and the n-type lightly doped drift region 20;
when the p-type channel region is inverted to form an electron layer after the voltage of the p-type doped gate 100 exceeds the threshold voltage, an inversion layer near the n-type heavily doped source region 50 will first occur below the n-type lightly doped region 70.
Specifically, a gate oxide layer 200 is further disposed on the p-type semiconductor substrate 10, and the p-type doped gate 100 is disposed on the gate oxide layer 200, wherein the p-type doped gate 100 is made of polysilicon, and the gate oxide layer 200 is made of silicon dioxide; wherein the n-type is lightThe doping concentration of the doped region 70 is 1 x 1011～6*1012cm2The doping concentration of the p-type doped region 80 is 1 x 1011～6*1012cm2。
Referring to fig. 4, a method for fabricating a p-type polysilicon gate LDMOS device with high mobility mainly includes the following steps:
providing a p-type semiconductor substrate 10, forming a gate oxide layer 200 on the surface of the p-type semiconductor substrate 10, forming a p-type doped gate 100 on the gate oxide layer, and etching the appearance of the gate;
processing and forming a p-type heavily doped body contact region 30, an n-type lightly doped drift region 20 and a p-type channel region 60 in the semiconductor substrate 10 by means of ion implantation and thermal diffusion, wherein the p-type channel region 60 is positioned below the p-type doped gate 100;
processing and forming an n-type heavily doped source region 50 and an n-type heavily doped drain region 40 in the p-type heavily doped body region contact region 30 and the n-type lightly doped drift region 20 respectively in an ion implantation mode, wherein the n-type heavily doped source region 50 and the n-type heavily doped drain region 40 are respectively matched with a source electrode and a drain electrode;
at the source end, by means of ion implantation, an n-type impurity is implanted at an inclined angle by using the layout of the source region, so as to process a region close to the surface of the p-type semiconductor substrate 10 in the p-type channel region 60 to form an n-type lightly doped region 70, at least a local region of the p-type channel region 60 is covered by the n-type lightly doped region 70, and the n-type lightly doped region 70 is electrically contacted with or electrically combined with the n-type heavily doped source region 50, so that the structure of the formed p-type polysilicon gate LDMOS device with high mobility is shown in fig. 2.
Referring to fig. 5, a method for fabricating a p-type polysilicon gate LDMOS device with high mobility mainly includes the following steps:
providing a p-type semiconductor substrate 10, and processing an area close to the surface of the p-type semiconductor substrate 10 in the semiconductor substrate 10 by means of ion implantation to form an n-type lightly doped region 70;
performing inclined angle p-type implantation on one side close to the n-type heavily doped source region by an ion implantation process to process and form a p-type doped region 80 in a local region of the n-type lightly doped region 70, and enabling the p-type doped region 80 to be electrically contacted or electrically combined with the n-type lightly doped region 70, wherein at least the part of the n-type lightly doped region 70 is covered by the p-type doped region 80;
processing and forming a p-type heavily doped body contact region 30, an n-type lightly doped drift region 20 and a p-type channel region 60 in the semiconductor substrate 10 by means of ion implantation, wherein the p-type channel region 60 is positioned below the n-type lightly doped region 70;
processing and forming an n-type heavily doped source region 50 and an n-type heavily doped drain region 40 in the p-type heavily doped body region contact region 30 and the n-type lightly doped drift region 20 respectively in an ion implantation mode, wherein the n-type heavily doped source region 50 and the n-type heavily doped drain region 40 are respectively matched with a source electrode and a drain electrode, the n-type lightly doped region 70 is electrically contacted with or electrically combined with the n-type heavily doped source region 50, and the p-type doped region 80 is electrically contacted with or electrically combined with the n-type lightly doped drift region 20;
a gate oxide layer 200 is formed on the surface of the p-type semiconductor substrate 10, a p-type doped gate 100 is formed on the gate oxide layer, the shape of the gate is etched, and the finally formed p-type polysilicon gate LDMOS device with high mobility is shown in fig. 3.
Further, the ion implantation concentration of the p-type heavily doped body region contact region 30 is 4 x 1013-2*1014cm2The energy is 25 to 150KEV, and the ion implantation concentration of the n-type lightly doped drift region 20 is 1 x 1012-4*1012cm2The energy is 50-200 KEV, the temperature of the thermal diffusion treatment of the p-type heavily doped body contact region 30 and the n-type lightly doped drift region 20 is 800-1000 ℃, and the time is 20-40 min; the ion implantation concentration of the n-type heavily doped source region 50 and the n-type heavily doped drain region 40 is 5 x 1014～5*1015cm2The energy is 25-100 KEV; the ion implantation concentration of the n-type lightly doped region 70 and the p-type doped region 80 is 1 x 1011-6*1012cm2And the energy is 25-150 KEV.
The main manufacturing process of the p-type polysilicon gate LDMOS device with high mobility is only given, wherein specific conditions such as manufacturing process parameters can be realized by the existing process by a person skilled in the art, and the specific process parameters can be adjusted and determined according to actual conditions.
The p-type polysilicon gate LDMOS device structure with high mobility is shown in fig. 2 and fig. 3, the core of the two device structures is that an n-type lightly doped region is added in a channel region, the doping distribution in the channel region is changed, an inversion layer of the channel region appears below the n-type lightly doped region firstly in the process of slow conduction of the device along with the increase of the voltage of a grid electrode of the device, and the inversion layer gradually moves towards the surface of the device or a semiconductor substrate along with the increase of the voltage of the grid electrode; because the doping concentration of the n-type lightly doped region is low, the inversion layer can be expanded to the surface of the channel region under the condition of high gate voltage, even if the inversion layer is distributed in the semiconductor substrate, most of the inversion layer is mainly generated in the semiconductor substrate and is far away from the surface under most of the gate voltage of the normal work of the device, so that the influence of surface defects on the electron mobility is reduced, the hot carrier injection effect is reduced, and the saturation current of the device can be further improved; the n-type lightly doped region in the channel region pulls down the threshold voltage; in addition, the embodiment of the invention adopts the P-type polycrystalline silicon as the grid electrode, so that the threshold voltage is improved and the application environment is compatible.
According to the high-mobility P-type polysilicon gate LDMOS device, the N-type lightly doped region is arranged in the P-type doped channel region, so that the doping distribution of the channel region is changed; when the device starts to be conducted, the inversion layer is positioned below the n-type lightly doped region, and the inversion layer is gradually thickened and is close to the surface of the channel region along with the increase of the grid voltage; when the device works, the inversion layer is positioned in the semiconductor substrate and is far away from the surface, so that the influence of surface defects on the electron mobility is reduced, meanwhile, the influence of hot carrier injection effect on the surface of the semiconductor device and a grid oxide layer is reduced, and the quality factors of the saturation current and the hot carrier injection reliability of the device are further improved.
It should be understood that the above-mentioned embodiments are merely illustrative of the technical concepts and features of the present invention, which are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and therefore, the protection scope of the present invention is not limited thereby. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (10)
1. A p-type polysilicon gate LDMOS device with high mobility is characterized by comprising a semiconductor substrate and a grid, wherein a body region contact region and a drift region are distributed in the semiconductor substrate, an active region and a drain region are respectively formed in the body region contact region and the drift region, the active region and the drain region are respectively matched with a source electrode and a drain electrode, a channel region is further distributed in the semiconductor substrate, the channel region is positioned below the grid, a first doping region is further formed in a region, close to the surface of the semiconductor substrate, in the channel region, and the first doping region is further electrically contacted with or combined with the source region, wherein the semiconductor substrate, the grid, the body region contact region and the channel region are of a first doping type, and the source region, the drain region, the drift region and the first doping region are of a second doping type;
when the gate voltage exceeds the threshold voltage, the inversion layer near the source region will first occur below the first doped region when the channel region is inverted to form an electron layer.
2. The high mobility p-type polysilicon gate LDMOS device set forth in claim 1 wherein: and a second doped region is also formed in the channel region or the region close to the surface of the semiconductor substrate in the first doped region, the second doped region is of the first doping type, and the second doped region is electrically contacted with or electrically combined with the first doped region and the drift region.
3. The high mobility p-type polysilicon gate LDMOS device set forth in claim 2 wherein: at least a local region of the first doped region is masked by the second doped region.
4. The high mobility p-type polysilicon gate LDM as set forth in claim 2An OS device, characterized by: the doping concentration of the first doping region and the second doping region is 1 x 1011～6*1012cm2。
5. The high mobility p-type polysilicon gate LDMOS device set forth in claim 1 wherein: an oxide layer is further formed on the surface of the semiconductor substrate, and the grid electrode is arranged above the oxide layer.
6. The high mobility p-type polysilicon gate LDMOS device set forth in claim 1, the p-type semiconductor substrate is internally distributed with a p-type heavily doped body contact region and an n-type lightly doped drift region, an n-type heavily doped source region and an n-type heavily doped drain region are respectively formed in the p-type heavily doped body region contact region and the n-type lightly doped drift region, the n-type heavily doped source region and the n-type heavily doped drain region are respectively matched with the source electrode and the drain electrode, and a p-type channel region is also distributed in the p-type semiconductor substrate and is positioned below the p-type doped grid electrode, an n-type lightly doped region is formed in a region, close to the surface of the p-type semiconductor substrate, in the p-type channel region, and is electrically contacted with or combined with the n-type heavily doped source region; when the voltage of the p-type doped grid electrode exceeds the threshold voltage and the inversion layer of the p-type channel region is inverted to form an electronic layer, the inversion layer close to the n-type heavily doped source region is firstly generated below the n-type lightly doped region.
7. The method of fabricating the high mobility p-type polysilicon gate LDMOS device of any one of claims 1-6, comprising:
providing a semiconductor substrate, and manufacturing a grid electrode on the semiconductor substrate;
manufacturing a body region contact region, a drift region and a channel region on the semiconductor substrate, manufacturing a source region and a drain region in the body region contact region and the drift region respectively, wherein the source region and the drain region are matched with a source electrode and a drain electrode respectively, and the channel region is positioned below the grid electrode;
and manufacturing a first doping region in the channel region close to the surface of the semiconductor substrate, wherein at least a partial region of the channel region is covered by the first doping region, and the first doping region is electrically contacted or combined with the source region.
8. The method of manufacturing according to claim 7, further comprising: and manufacturing a second doped region in a region close to the surface of the semiconductor substrate in the channel region or in a region of the first doped region close to the surface of the semiconductor substrate, wherein at least a partial region of the first doped region is covered by the second doped region, and the second doped region is electrically contacted or combined with the first doped region and the drift region.
9. The manufacturing method according to claim 8, characterized by specifically comprising: the semiconductor substrate comprises a body region contact region, a drift region, a source region, a drain region, a first doped region and a second doped region, wherein the body region contact region and the drift region are formed by local processing of a semiconductor substrate in an ion implantation and thermal diffusion mode, the source region is formed by local processing of the body region contact region in an ion implantation mode, the drain region is formed by local processing of the drift region in an ion implantation mode, the first doped region is formed by local processing of a channel region in an ion implantation mode, and the second doped region is formed by local processing of the channel region or the first doped region in an ion implantation mode.
10. The manufacturing method according to claim 7, characterized by specifically comprising: manufacturing an oxide layer on the surface of the semiconductor substrate, and then manufacturing a grid electrode on the oxide layer; preferably, the gate comprises polysilicon, the oxide layer comprises silicon dioxide, and the oxide layer has a thickness of 0.01-0.06 nm.
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| CN202010707870.8A CN113964190B (en) | 2020-07-21 | 2020-07-21 | High-mobility p-type polysilicon gate LDMOS device and manufacturing method thereof |
| PCT/CN2020/111569 WO2022016659A1 (en) | 2020-07-21 | 2020-08-27 | High-mobility p-type polysilicon gate ldmos device and manufacturing method therefor |
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| CN1866541A (en) * | 2005-05-12 | 2006-11-22 | 英飞凌科技股份公司 | Field effect transistor and method for manufacturing same |
| US20080023760A1 (en) * | 2006-07-28 | 2008-01-31 | Broadcom Corporation | Semiconductor device with increased breakdown voltage |
| CN109830538A (en) * | 2019-01-22 | 2019-05-31 | 上海华虹宏力半导体制造有限公司 | LDMOS device and its manufacturing method |
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| JP2001060686A (en) * | 1999-08-20 | 2001-03-06 | Ricoh Co Ltd | Ldmos type semiconductor device and manufacture thereof |
| JP4211884B2 (en) * | 1999-08-30 | 2009-01-21 | 株式会社リコー | Manufacturing method of LDMOS type semiconductor device |
| JP2008182106A (en) * | 2007-01-25 | 2008-08-07 | Denso Corp | Semiconductor device |
| CN111354792B (en) * | 2018-12-20 | 2023-09-12 | 中芯国际集成电路制造(上海)有限公司 | LDMOS device and formation method thereof, semiconductor device formation method |
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| CN1866541A (en) * | 2005-05-12 | 2006-11-22 | 英飞凌科技股份公司 | Field effect transistor and method for manufacturing same |
| US20080023760A1 (en) * | 2006-07-28 | 2008-01-31 | Broadcom Corporation | Semiconductor device with increased breakdown voltage |
| CN109830538A (en) * | 2019-01-22 | 2019-05-31 | 上海华虹宏力半导体制造有限公司 | LDMOS device and its manufacturing method |
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