CN113937016A - Semiconductor packaging method and semiconductor packaging structure - Google Patents

Abstract

The application provides a semiconductor packaging method and a semiconductor packaging structure. In the present application, a semiconductor packaging method includes: fixing the bare chip to be packaged and the conductive columns on the carrier plate, wherein the front surface of the bare chip to be packaged faces the carrier plate, the front surface of the bare chip to be packaged is provided with a welding pad, the back surface of the bare chip to be packaged is provided with an inductance element, and a first electric connection point of the inductance element is positioned on one side, far away from the bare chip to be packaged, of the inductance element; forming a plastic packaging layer on the carrier plate, wherein the plastic packaging layer wraps the bare chip to be packaged, the inductance element and the conductive columns, and the first electric connection points and the first ends of the conductive columns are exposed out of the plastic packaging layer; forming a first conductive trace on one side of the plastic packaging layer close to the back surface of the bare chip to be packaged, wherein the first conductive trace is connected with the first electrical connection point and the first end of the conductive column; removing the carrier plate; and forming a second conductive trace on one side of the plastic packaging layer close to the front surface of the bare chip to be packaged, wherein the second conductive trace is connected with the welding pad and the second end of the conductive column. In the embodiment of the application, the semiconductor packaging structure is small in size.

Description

Semiconductor packaging method and semiconductor packaging structure

technical field

The present application relates to the field of semiconductor technology, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.

Background technique

In the related art, in the packaging process, the inductors and the bare chips in the packaging components can be arranged on the carrier board together to form a package body with a parallel arrangement structure. The package of this type of structure has a large volume and is not compact in structure.

With the miniaturization and weight reduction of electronic devices, chip packages with compact structure and small volume are favored by more and more markets.

However, how to reduce the volume of the chip package is a technical problem to be solved.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a semiconductor packaging method and a semiconductor packaging structure, which can reduce the volume and compact structure of the semiconductor packaging structure.

Embodiments of the present application provide a semiconductor packaging method, including:

The die to be packaged and the conductive posts are fixed on the carrier board, the front side of the die to be packaged faces the carrier board, the front side of the die to be packaged is provided with a pad, and the back side of the die to be packaged is provided There is an inductance element, the inductance element includes a first electrical connection point, the first electrical connection point is located on the side of the inductance element away from the to-be-packaged die, and the conductive post is located on the to-be-packaged die. the peripheral side; the conductive column includes a first end and a second end, the first end is located at the end of the conductive column close to the inductance element, and the second end is located at the end of the conductive column away from the inductance element one end;

A plastic encapsulation layer is formed on the carrier board, the plastic encapsulation layer wraps the to-be-packaged die, the inductance element and the conductive post, the first electrical connection point of the inductance element and the first electrical connection point of the conductive post The surfaces of the ends are respectively exposed from the plastic sealing layer;

A first conductive trace is formed on the side of the plastic encapsulation layer close to the backside of the die to be packaged, and the first conductive trace connects the first electrical connection point of the inductance element and the first electrical connection point of the conductive column end;

removing the carrier;

A second conductive trace is formed on the side of the plastic encapsulation layer close to the front surface of the die to be packaged, and the second conductive trace connects the bonding pad of the die to be packaged and the second end of the conductive post .

In one embodiment, before the die to be packaged and the conductive pillars are fixed on the carrier board, the method further includes:

forming a first metal layer on the backside of the silicon wafer by an electroplating process;

The first metal layer is etched through an etching process to obtain the inductance element;

Divide the silicon wafer to obtain the to-be-packaged die, or,

forming a seed layer on the backside of the silicon wafer by a sputtering process;

forming a first metal layer on the seed layer by an electroplating process;

The first metal layer and the seed layer are etched through an etching process to obtain the inductance element;

dividing the silicon wafer to obtain the to-be-packaged die;

The seed layer includes a first seed layer and a second seed layer, the first seed layer is located on the silicon wafer, the second seed layer is located on the first seed layer, and the first seed layer is located on the silicon wafer. The material of the layer is titanium, and the material of the second seed layer is copper; or,

The seed layer includes a second seed layer, and the material of the second seed layer is copper.

In one embodiment, a protective layer is further formed on the front surface of the to-be-packaged die; the distance between the surface of the protective layer away from the inductance element and the surface of the inductance element away from the protective layer is smaller than the distance between the surface of the protective layer and the surface of the inductance element away from the protective layer. The height of the conductive post.

In one embodiment, the conductive posts are preformed;

or,

forming a second metal layer on the carrier;

The second metal layer is etched through an etching process to obtain the conductive pillars.

In one embodiment, the forming a plastic encapsulation layer on the carrier includes:

An encapsulation layer is formed on the carrier board, the encapsulation layer wraps the to-be-packaged die, the inductance element and the conductive pillar, and the thickness of the encapsulation layer is greater than the height of the conductive pillar;

The encapsulation layer is thinned to obtain the plastic encapsulation layer, so that the first ends of the conductive pillars are exposed from the plastic encapsulation layer.

In one embodiment, the plastic encapsulation layer includes a first opening to expose the first electrical connection point of the inductance element; the first opening is formed on the plastic encapsulation layer through a laser drilling process.

In one embodiment, forming a first conductive trace on a side of the plastic encapsulation layer close to the backside of the die to be encapsulated includes:

A first conductive medium is filled in the first opening to form a first conductive filling interface, and a first conductive layer is formed on the plastic encapsulation layer; the first conductive filling interface and the first electrical connection point of the inductance element electrical connection, the first conductive layer is electrically connected to the first conductive filling interface;

patterning the first conductive layer to obtain the first conductive traces;

Wherein, the first conductive filling interface and the first conductive layer are formed in the same process step.

In one embodiment, after forming the first conductive traces on the side of the plastic encapsulation layer close to the backside of the die to be encapsulated, the method further includes:

A first dielectric layer is formed on the first conductive trace, the first dielectric layer wrapping the first conductive trace.

In one embodiment, the semiconductor packaging method further includes:

forming a second opening on the protective layer to expose the bonding pads of the die to be packaged;

The step of forming a second opening on the protective layer is located after the step of removing the carrier, or after the step of forming a protective layer on the front surface of the die to be packaged, and is located at the before the steps of fixing the bare chip to be packaged and the conductive post on the carrier;

When the material of the protective layer is a laser reactive material, the second opening is formed on the protective layer by a laser drilling process;

When the material of the protective layer is a photosensitive material, the second opening is formed on the protective layer through a photolithography process.

In one embodiment, the forming the second conductive trace on the side of the plastic encapsulation layer close to the front surface of the die to be encapsulated includes:

A second conductive medium is filled in the second opening to form a second conductive filling interface, and a second conductive layer is formed on the plastic encapsulation layer and the protective layer; the second conductive filling interface and the to-be-packaged bare metal interface are formed. The pads of the chip are electrically connected, and the second conductive layer is electrically connected to the second conductive filling interface;

patterning the second conductive layer to obtain the second conductive traces;

Wherein, the second conductive filling interface and the second conductive layer are formed in the same process step.

In one embodiment, the second conductive trace includes a second electrical connection point, and the second electrical connection point is located on a side of the second conductive trace away from the die to be packaged; After the second conductive trace is formed on the side of the plastic encapsulation layer close to the front surface of the to-be-packaged die, the method further includes:

forming conductive bumps on the second electrical connection points of the second conductive traces;

A second dielectric layer is formed on the second conductive traces and the conductive bumps to obtain a plastic package. The second dielectric layer wraps the second conductive traces and the conductive bumps. The conductive bumps are exposed from the second dielectric layer away from the surface of the die to be packaged;

The plastic packaging body is cut to obtain a semiconductor packaging structure, the semiconductor packaging structure includes the bare chip to be packaged, the inductance element, the conductive column, the plastic packaging layer, the first conductive trace and the the second conductive trace; or,

After the second conductive trace is formed on the side of the plastic encapsulation layer close to the front surface of the die to be encapsulated, the method further includes:

forming conductive bumps on the second electrical connection points of the second conductive traces;

A second dielectric layer is formed on the second conductive traces and the conductive bumps to obtain a plastic package; the second dielectric layer wraps the second conductive traces and the conductive bumps, and the second dielectric layer wraps the second conductive traces and the conductive bumps. The conductive bumps are exposed from the second dielectric layer away from the surface of the die to be packaged;

forming a surface treatment layer on the exposed surfaces of the conductive bumps;

The plastic packaging body is cut to obtain a semiconductor packaging structure, the semiconductor packaging structure includes the bare chip to be packaged, the inductance element, the conductive column, the plastic packaging layer, the first conductive trace and the the second conductive trace.

Some embodiments of the present application also provide a semiconductor packaging structure, which is prepared by the above-mentioned semiconductor packaging method, and the semiconductor packaging structure includes:

a die to be packaged, the front side of the die to be packaged is provided with a solder pad;

an inductance element, located on the backside of the to-be-packaged die; the inductance element includes a first electrical connection point, and the first electrical connection point is located on a side of the inductance element away from the to-be-packaged die;

A conductive column is located on the peripheral side of the to-be-packaged die; the conductive column includes a first end and a second end, the first end is located at one end of the conductive column close to the inductance element, and the second end is located at one end of the conductive column away from the inductive element;

A plastic encapsulation layer wraps the die to be packaged, the inductance element and the conductive post, the first electrical connection point of the inductance element, the surface of the first end of the conductive post, and the second electrical connection point of the conductive post The surfaces of the ends are respectively exposed from the plastic sealing layer;

a first conductive trace, located on the side of the plastic encapsulation layer close to the backside of the to-be-packaged die, and connecting the first electrical connection point of the inductance element and the first end of the conductive column;

The second conductive trace is located on the side of the plastic encapsulation layer close to the front surface of the die to be packaged, and connects the bonding pad of the die to be packaged and the second end of the conductive post.

In the embodiment of the present application, by arranging the inductance element on the back of the to-be-packaged die, the to-be-packaged die and the inductance element are stacked in the thickness direction of the to-be-packaged die, and the thickness direction of the to-be-packaged die is rationally utilized. The space of the semiconductor package structure can be made compact, thereby reducing the volume of the semiconductor package structure. Therefore, in the embodiments of the present application, the semiconductor package structure is small in size and compact in structure, and is suitable for small and lightweight electronic devices.

Description of drawings

FIG. 1 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the present application.

FIG. 2 is a schematic flowchart of a semiconductor packaging method according to an embodiment of the present application.

3A is a schematic structural diagram of an intermediate structure produced in a process of preparing a semiconductor package structure according to an embodiment of the present application.

3B is a schematic structural diagram of an intermediate structure produced in a process of preparing a semiconductor package structure according to an embodiment of the present application.

3C is a schematic structural diagram of an intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present application.

FIG. 4 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present application.

FIG. 5 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present application.

FIG. 6 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present application.

FIG. 7 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present application.

8A is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present application.

8B is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present application.

FIG. 9 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present application.

FIG. 10 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present application.

FIG. 11 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present application.

FIG. 12 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present application.

FIG. 13 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present application.

FIG. 14 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present application.

FIG. 15 is a schematic structural diagram of another intermediate structure produced in the process of preparing a semiconductor package structure according to an embodiment of the present application.

FIG. 16 is a schematic diagram of cutting a plastic package according to an embodiment of the present application.

Detailed ways

Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. Where the following description refers to the drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the illustrative examples below are not intended to represent all implementations consistent with this application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as recited in the appended claims.

The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this application and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited by these terms. These terms are only used to distinguish the same type of information from each other. For example, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information without departing from the scope of the present application. Depending on the context, the word "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determining."

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and features in the embodiments may be combined with each other without conflict.

Embodiments of the present application provide a semiconductor package structure. The semiconductor package structure is the chip package body. The semiconductor packaging structure is suitable for antenna chip packaging. The conductor package structure can be applied to electronic equipment, such as mobile phones, computers and the like. As shown in FIG. 1 , the semiconductor package structure includes a die to be packaged 11 , an inductive element 12 , a conductive column 13 , a plastic packaging layer 14 , a first conductive trace 15 , a second conductive trace 16 , a protective layer 17 , and a first conductive trace The filling interface 18 , the second conductive filling interface 19 , the first dielectric layer 110 , the conductive bumps 111 , the second dielectric layer 112 and the surface treatment layer (not shown).

In this embodiment, the die 11 to be packaged includes a front side and a back side, and the front side and the back side are opposite to each other. The front surface of the die to be packaged 11 is an active surface, and the front surface of the die to be packaged 11 is provided with a solder pad (not shown), and the solder pad is used for electrical connection with the outside world.

In this embodiment, as shown in FIG. 1 , the inductance element 12 is located on the backside of the die 11 to be packaged. The inductance element 12 is an electromagnetic conversion device. In this embodiment, the material of the inductance element 12 is copper, but it is not limited thereto.

In this embodiment, the inductance element 12 includes a first electrical connection point (not shown), and the first electrical connection point is located on a side of the inductance element 12 away from the die 11 to be packaged. The first electrical connection point is used for electrical connection with the outside world.

In this embodiment, as shown in FIG. 1 , the conductive pillars 13 are located on the peripheral side of the die 11 to be packaged. The material of the conductive pillar 13 may be copper, but is not limited thereto. The conductive column 13 includes a first end and a second end, the first end is located at the end of the conductive column 13 close to the inductance element 12 , the second end is located at the end of the conductive column 13 away from the inductance element 12 , the first end of the conductive column 13 and the conductive column The second end of 13 is located opposite. The surfaces of the first ends of the conductive pillars 13 and the surfaces of the second ends of the conductive pillars 13 are respectively exposed from the plastic encapsulation layer 14 .

In this embodiment, as shown in FIG. 1 , the plastic encapsulation layer 14 wraps the to-be-packaged die 11 , the inductance element 12 and the conductive column 13 . Wherein, the plastic sealing layer 14 may be a polymer, a resin, a resin composite material, or a polymer composite material. For example, the plastic sealing layer 14 may be a resin with fillers, wherein the fillers are inorganic particles.

In this embodiment, the plastic encapsulation layer 14 includes a first opening (not shown) to expose the first electrical connection point of the inductance element 12 . Specifically, the first opening is located on the side of the plastic encapsulation layer 14 close to the inductance element 12, and the projection of the first opening on the inductance element 12 at least partially overlaps with the projection of the first electrical connection point on the inductance element 12, so that at least part of the An electrical connection point is exposed from the plastic encapsulation layer 14 . For example, the projection of the first opening on the inductance element 12 and the projection of the first electrical connection point (not shown) on the inductance element 12 may be completely coincident, so that the first electrical connection point is exposed from the plastic encapsulation layer 14 . For another example, the projection of the first opening on the inductance element 12 and the projection of the first electrical connection point on the inductance element 12 may partially overlap, so that part of the first electrical connection point is exposed from the plastic encapsulation layer 14 .

In this embodiment, as shown in FIG. 1 , the first conductive filling interface 18 is located in the first opening, and the first conductive filling interface 18 is electrically connected to the first electrical connection point of the inductance element 12 and to the first conductive trace. 15 Electrical connections. Wherein, the material of the first conductive filling interface 18 may be copper, but is not limited thereto.

In this embodiment, as shown in FIG. 1 , the first conductive traces 15 are located on the side of the plastic encapsulation layer 14 close to the backside of the die 11 to be packaged, and connect the first electrical connection point of the inductance element 12 with the conductive post 13 . first end. Wherein, the material of the first conductive traces 15 is copper, but not limited thereto.

In this embodiment, as shown in FIG. 1 , the first dielectric layer 110 is located on the first conductive traces 15 and covers the first conductive traces 15 . Wherein, the material of the first dielectric layer 110 is one or more layers of insulating material, which can be plastic film, PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer Composites or other materials with similar properties.

In this embodiment, as shown in FIG. 1 , the protective layer 17 is located on the front side of the die 11 to be packaged. The protective layer 17 is one or more layers of insulating material, which can be plastic film, PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite material or other materials with similar properties s material.

In this embodiment, the protective layer 17 includes a second opening to expose the solder pads of the die 11 to be packaged. The second opening is located on the side of the protective layer 17 away from the inductance element 12, and the projection of the second opening on the die to be packaged 11 at least partially coincides with the projection of the solder pad on the die to be packaged 11, so that at least part of the solder pad The protective layer 17 is exposed. For example, the projection of the second opening on the die to be packaged 11 completely coincides with the projection of the solder pad on the die to be packaged 11 , so that the solder pad is exposed from the protective layer 17 . For another example, the projection of the second opening on the die to be packaged 11 overlaps with the projection of the solder pad on the die to be packaged 11 , so that part of the solder pad is exposed from the protective layer 17 .

In this embodiment, as shown in FIG. 1 , the second conductive filling interface 19 is located in the second opening, the second conductive filling interface 19 is electrically connected to the pad of the die 11 to be packaged, and the second conductive trace 16 is connected to the second opening. The two conductive filling interfaces 19 are electrically connected. Wherein, the material of the second conductive filling interface 19 is copper, but not limited thereto.

In this embodiment, the second conductive traces 16 are located on the side of the plastic encapsulation layer 14 close to the front surface of the die to be packaged 11 , and are connected to the pads of the die to be packaged 11 and the second ends of the conductive pillars 13 . Wherein, the material of the second conductive traces 16 is copper, but not limited thereto.

In this embodiment, as shown in FIG. 1 , the conductive bumps 111 are located on the second electrical connection points (not shown) of the second conductive traces 16 . The material of the conductive bumps 111 is copper, but not limited thereto.

In this embodiment, as shown in FIG. 1 , the second dielectric layer 112 is located on the second conductive traces 16 and the conductive bumps 111 , and wraps the second conductive traces 16 and the conductive bumps 111 , and the conductive bumps The surface of 111 away from the die 11 to be packaged is exposed from the second dielectric layer 112 . The material of the second dielectric layer 112 is one or more layers of insulating materials, which can be plastic film, PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite material or other materials with similar properties.

In this embodiment, a surface treatment layer (not shown) is located on the surface of the exposed conductive bumps 111 . The surface treatment layer is used to delay the oxidation rate of the conductive bumps 111 . Wherein, the material of the surface treatment layer can be matte tin (matte tin) or composite electroplating layer. For example, the composite electroplating layer may include a third metal layer and a fourth metal layer, the third metal layer is located on the surface of the conductive bump 111, the fourth metal layer is located on the third metal layer, and the material of the third metal layer is nickel ( Ni), and the material of the fourth metal layer is gold (Au). For another example, the composite electroplating layer may include a fifth metal layer, a sixth metal layer and a seventh metal layer, the fifth metal layer is located on the surface of the conductive bump 111, the sixth metal layer is located on the fifth metal layer, and the seventh metal layer is located on the surface of the conductive bump 111. The layer is located on the sixth metal layer, the material of the fifth metal layer is nickel (Ni), the material of the sixth metal layer is palladium (Pd), and the material of the seventh metal layer is gold (Au).

It should be noted that the semiconductor package structure may not include a surface treatment layer.

In the embodiment, the inductance element 12 is electrically connected to the pads of the die to be packaged 11 through the first conductive filling interface 18 , the first conductive trace 15 , the conductive pillar 13 , the second conductive trace 16 , and the second conductive filling interface 19 . connect.

In the embodiment of the present application, by arranging the inductance element on the back of the to-be-packaged die, the to-be-packaged die and the inductance element are stacked in the thickness direction of the to-be-packaged die, and the thickness direction of the to-be-packaged die is rationally utilized. The space of the semiconductor package structure can be made compact, thereby reducing the volume of the semiconductor package structure. Therefore, in the embodiments of the present application, the semiconductor package structure is small in size and compact in structure, and is suitable for small and lightweight electronic devices.

Embodiments of the present application further provide a semiconductor packaging method for preparing the above-mentioned semiconductor packaging structure. As shown in FIG. 2, the semiconductor packaging method includes the following steps 201-211:

In step 201, the die to be packaged and the conductive posts are fixed on the carrier board, the front side of the die to be packaged 11 faces the carrier board, the front side of the die to be packaged 11 is provided with a solder pad, and the front side of the die to be packaged 11 is also A protective layer 17 is provided, and an inductance element 12 is disposed on the back of the to-be-packaged die 11. The inductance element 12 includes a first electrical connection point, and the first electrical connection point is located on the side of the inductance element 12 away from the to-be-packaged die 11. 13 is located on the peripheral side of the die to be packaged 11 , the conductive post 13 includes a first end and a second end, the first end is located at one end of the conductive post 13 close to the inductance element 12 , and the second end is located far from the conductive post 13 away from the inductive element 12 . one end. The distance between the surface of the protective layer 17 away from the inductance element 12 and the surface of the inductance element 12 away from the protective layer 17 is less than the height of the conductive pillar 13 , and the height of the conductive pillar 13 is the distance between the first end of the conductive pillar 13 and the conductive pillar 13 . distance between the second ends.

In this embodiment, the to-be-packaged die 11 and the conductive pillars 13 are fixed on the carrier board to obtain an intermediate structure as shown in FIG. 3A . In FIG. 3A , only three packaging units are shown. The packaging unit refers to a unit that forms a semiconductor packaging structure (chip) after the packaging is completed. In fact, there may be one or more packaging units on the carrier board. This application does not cover packaging. The number of units is limited.

In this embodiment, an adhesive layer is provided on the carrier board 31 for fixing the to-be-packaged die 11 and the conductive pillars 13 arranged on the carrier board 31. Preferably, the adhesive layer is a thermal separation adhesive layer .

In one embodiment, step 201 may include: first, as shown in FIG. 3B , forming a second metal layer 32 on the carrier 31 ; then, as shown in FIG. 3C , performing an etching process on the second metal layer 32 After etching, the conductive pillars 13 are obtained; then, the bare chip 11 to be packaged is mounted on the carrier board 31 .

In another embodiment, the conductive posts are preformed. Step 201 may include: first, providing the to-be-packaged die 11 and the pre-formed conductive pillars 13 ; and then, mounting the to-be-packaged die 11 and the conductive pillars 13 on the carrier board 31 .

In this embodiment, before step 201, the following steps are further included:

First, a seed layer is formed on the backside of the silicon wafer by a sputtering process. In this embodiment, the seed layer includes a first seed layer and a second seed layer. The first seed layer is located on the silicon wafer, the second seed layer is located on the first seed layer, the material of the first seed layer is titanium, and the material of the second seed layer is copper. The method for forming the seed layer is to form a first seed layer on the backside of the silicon wafer, and then form a second seed layer on the first seed layer. The material of the first seed layer is titanium, which can improve the interlayer adhesion, and the material of the second seed layer is copper, which has good mechanical properties and electrical conductivity. Of course, in actual implementation, the seed layer may only include the above-mentioned second seed layer.

Next, a first metal layer is formed on the seed layer through an electroplating process. In this embodiment, the material of the first metal layer may be copper. After the first metal layer 41 is formed on the seed layer, an intermediate structure as shown in FIG. 4 is obtained, wherein a seed layer (not shown) is included between the first metal layer 41 and the silicon wafer 42 .

It should be noted that the seed layer may not be provided between the first metal layer and the back surface of the silicon wafer.

Next, the first metal layer 41 and the seed layer are etched through an etching process to obtain the inductor element 12 . In this embodiment, as shown in FIG. 5 , the first metal layer 41 is etched to obtain the inductance element 12 . Specifically, the methods of spinning photo material, exposing, developing, striping, and etching can be used to form an inductor/coil on the backside of the silicon wafer.

Next, a protective layer 17 is formed on the front surface of the silicon wafer. In this embodiment, as shown in FIG. 6 , the protective layer 17 is formed on the front surface of the silicon wafer 42 . The protective layer 17 may be formed by lamination, spin coating, printing, molding or other suitable methods.

Next, the silicon wafer is divided to obtain the bare chip 11 to be packaged. In this embodiment, as shown in FIG. 7 , the silicon wafer 42 is divided to obtain the bare chip 11 to be packaged.

It should be noted that, in actual implementation, the seed layer may not be provided between the silicon chip 42 and the inductor 12 .

In step 202 , a plastic encapsulation layer is formed on the carrier board, and the plastic encapsulation layer 14 wraps the to-be-packaged die 11 , the inductance element 12 and the conductive column 13 , the first electrical connection point of the inductance element 12 and the first end of the conductive column 13 . The surfaces are exposed from the plastic encapsulation layer 14, respectively.

In this embodiment, as shown in FIG. 8A , the plastic encapsulation layer 14 wraps the to-be-packaged die 11 , the inductance element 12 and the conductive pillar 13 , and the surface of the first end of the conductive pillar 13 is exposed from the plastic encapsulation layer 14 , and the plastic encapsulation layer 14 is the same as the height of the conductive pillar 13 .

In this embodiment, step 202 may include the following steps: First, as shown in FIG. 8B , an encapsulation layer 81 is formed on the carrier board 31 , and the encapsulation layer 81 wraps the to-be-packaged die 11 , the inductance element 12 and the conductive Post 13 , the thickness of the encapsulation layer 81 is greater than the height of the conductive post 13 ; then, the encapsulation layer 81 is thinned to obtain the plastic encapsulation layer 14 , so that the first end of the conductive post 13 exposes the plastic encapsulation layer 14 . The thickness of the plastic encapsulation layer 14 is the same as the height of the conductive pillars 13 . When the encapsulation layer 81 is thinned, the encapsulation layer 81 may be thinned by means of mechanical grinding.

In this embodiment, as shown in FIG. 9 , the plastic encapsulation layer 14 includes a first opening 91 to expose the first electrical connection point of the inductance element 12 . The projection of the first opening 91 on the inductance element 12 at least partially coincides with the projection of the first electrical connection point on the inductance element 12 to expose at least part of the first electrical connection point.

In this embodiment, as shown in FIG. 9 , the surface of the plastic sealing layer 14 away from the carrier 31 can be opened by a laser drilling process to obtain the first opening 91 . For example, a laser can be used to form the first opening 91 on the plastic sealing layer 14 . An opening exposes the first electrical connection point of the inductive element 12 .

In step 203, a first conductive trace is formed on the side of the plastic encapsulation layer close to the backside of the die to be packaged, and the first conductive trace is connected to the first electrical connection point of the inductance element and the first end of the conductive column.

In this embodiment, as shown in FIG. 10 , a first conductive medium may be filled in the first opening 91 to form a first conductive filling interface 18 , and a first conductive layer (not shown) may be formed on the plastic sealing layer 14 , The first conductive filling interface 18 is electrically connected to the first electrical connection point of the inductance element, and the first conductive layer is electrically connected to the first conductive filling interface 18 . In addition, the first conductive layer may be formed by metal sputtering, electrolytic plating, electroless plating, or the like. The first conductive filling interface 18 and the first conductive layer can be formed through the same process step. Then, the first conductive layer is patterned to obtain first conductive traces 15 . In this way, the inductive element 12 can be electrically connected to the conductive post 13 through the first conductive trace 15 .

In step 204 , a first dielectric layer is formed on the first conductive traces, and the first dielectric layer 110 wraps the first conductive traces 15 .

In this embodiment, as shown in FIG. 11 , a first dielectric layer 110 is formed on the first conductive traces 15 , and the first dielectric layer 110 covers the first conductive traces 15 . Wherein, the first dielectric layer 110 may be formed by lamination, spin coating, printing, molding or other suitable methods.

In step 205, the carrier plate is removed.

In step 206, a second opening is formed in the protective layer to expose the bonding pads of the die to be packaged.

In this embodiment, as shown in FIG. 12 , a second opening 121 is formed on the protective layer 17 to expose at least part of the pad. Wherein, when the protective layer 17 is made of a laser reactive material, a laser opening process can be used to form a second opening on the protective layer 17, and when the protective layer 17 is made of a photosensitive material, a second opening can be formed on the protective layer 17 by a photolithography process. Two open.

Of course, step 206 may be located after step 205, or after the above-mentioned step of forming a protective layer on the front side of the silicon wafer, and before the step of fixing the die to be packaged and the conductive pillars on the carrier board.

In step 207 , a second conductive trace is formed on the side of the plastic encapsulation layer close to the front surface of the die to be packaged, and the second conductive trace 16 is connected to the bonding pad of the die to be packaged and the second end of the conductive post 13 .

In this embodiment, as shown in FIG. 13 , the second opening 121 may be filled with a second conductive medium to form a second conductive filling interface 19 , and a second conductive layer may be formed on the plastic sealing layer 14 and the protective layer 17 ; The two conductive filling interfaces 19 are electrically connected to the bonding pads of the die to be packaged 11 , and the second conductive layer is electrically connected to the second conductive filling interfaces 19 . The second conductive layer may be formed by metal sputtering, electrolytic plating, electroless plating, or the like. The second conductive filling interface 19 and the second conductive layer can be formed through the same process steps. Then, the second conductive layer is patterned to obtain second conductive traces 16 .

In step 208, conductive bumps are formed on the second electrical connection points of the second conductive traces.

In this embodiment, as shown in FIG. 14 , conductive bumps 111 are formed on the second electrical connection points of the second conductive traces 16 .

In step 209, a second dielectric layer is formed on the second conductive traces and the conductive bumps to obtain a plastic package. The second dielectric layer 112 wraps the second conductive traces 16 and the conductive bumps 111 , and the conductive bumps 111 are exposed from the second dielectric layer 112 away from the surface of the die 11 to be packaged.

In this embodiment, as shown in FIG. 15 , a second dielectric layer 112 may be formed on the second conductive traces 16 and the conductive bumps 111 to obtain the plastic package 20 . The second dielectric layer 112 wraps the second conductive traces 16 and the conductive bumps 111 , the conductive bumps 111 are exposed from the second dielectric layer 112 away from the surface of the die 11 to be packaged, and the second dielectric layer 112 is far away from the surface to be packaged. The surface of the packaged die 11 is flush with the surface of the conductive bump 111 away from the to-be-packaged die 11 . In actual implementation, the distance between the surface of the second dielectric layer 112 away from the die to be packaged 11 and the surface of the second dielectric layer 112 close to the die to be packaged 11 may be greater than the distance between the conductive bumps 111 away from the die to be packaged 11 The distance between the surface of the conductive bump 111 and the surface of the conductive bump 111 close to the die 11 to be packaged. After the second dielectric layer 112 is formed, the second dielectric layer 112 may be thinned until the second dielectric layer 112 is far away from the surface of the die to be packaged 11 and the conductive bumps 111 are far away from the surface of the die to be packaged 11 flush.

In step 210, a surface treatment layer is formed on the surfaces of the exposed conductive bumps.

Of course, in another embodiment, the surface treatment layer may not be formed on the surface of the conductive bump 111 .

In step 211 , the plastic package is cut to obtain a semiconductor package structure. The semiconductor package structure includes a die to be packaged, an inductance element, a conductive post, a plastic package, a first conductive trace and a second conductive trace.

In this embodiment, as shown in FIG. 16 , a cutting operation is performed on the plastic package 20 at the cutting position P, and the semiconductor package structure shown in FIG. 1 can be obtained.

In the embodiment of the present application, by arranging the inductance element on the back of the to-be-packaged die, the to-be-packaged die and the inductance element are stacked in the thickness direction of the to-be-packaged die, and the thickness direction of the to-be-packaged die is rationally utilized. The space of the semiconductor package structure can be made compact, thereby reducing the volume of the semiconductor package structure. Therefore, in the embodiments of the present application, the semiconductor package structure is small in size and compact in structure, and is suitable for small and lightweight electronic devices.

In this application, the apparatus embodiments and the method embodiments may complement each other without conflict. The device embodiments described above are only illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place , or distributed to multiple network elements. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the present application. Those of ordinary skill in the art can understand and implement it without creative effort.

The above are only preferred embodiments of the present application, and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the protection of the present application. within the range.

Claims (12)

1. a semiconductor packaging method, is characterized in that, comprises: The die to be packaged and the conductive posts are fixed on the carrier board, the front side of the die to be packaged faces the carrier board, the front side of the die to be packaged is provided with a pad, and the back side of the die to be packaged is provided There is an inductance element, the inductance element includes a first electrical connection point, the first electrical connection point is located on the side of the inductance element away from the to-be-packaged die, and the conductive post is located on the to-be-packaged die. the peripheral side; the conductive column includes a first end and a second end, the first end is located at the end of the conductive column close to the inductance element, and the second end is located at the end of the conductive column away from the inductance element one end; A plastic encapsulation layer is formed on the carrier board, the plastic encapsulation layer wraps the to-be-packaged die, the inductance element and the conductive post, the first electrical connection point of the inductance element and the first electrical connection point of the conductive post The surfaces of the ends are respectively exposed from the plastic sealing layer; A first conductive trace is formed on the side of the plastic encapsulation layer close to the backside of the die to be packaged, and the first conductive trace connects the first electrical connection point of the inductance element and the first electrical connection point of the conductive column end; removing the carrier; A second conductive trace is formed on the side of the plastic encapsulation layer close to the front surface of the die to be packaged, and the second conductive trace connects the bonding pad of the die to be packaged and the second end of the conductive post . 2 . The semiconductor packaging method according to claim 1 , wherein before the to-be-packaged die and the conductive post are fixed on the carrier board, the method further comprises: 3 . forming a first metal layer on the backside of the silicon wafer by an electroplating process; The first metal layer is etched through an etching process to obtain the inductance element; Divide the silicon wafer to obtain the to-be-packaged die, or, Before fixing the bare chip to be packaged and the conductive post on the carrier board, the method further includes: forming a seed layer on the backside of the silicon wafer by a sputtering process; forming a first metal layer on the seed layer by an electroplating process; The first metal layer and the seed layer are etched through an etching process to obtain the inductance element; dividing the silicon wafer to obtain the to-be-packaged die; The seed layer includes a first seed layer and a second seed layer, the first seed layer is located on the silicon wafer, the second seed layer is located on the first seed layer, and the first seed layer is located on the silicon wafer. The material of the layer is titanium, and the material of the second seed layer is copper; or, The seed layer includes a second seed layer, and the material of the second seed layer is copper. 3 . The semiconductor packaging method according to claim 1 , wherein a protective layer is further formed on the front surface of the die to be packaged; the protective layer is far away from the surface of the inductance element and the inductance element is far away from the inductance element. 4 . The distance between the surfaces of the protective layer is smaller than the height of the conductive pillars. 4. The semiconductor packaging method according to claim 1, wherein the conductive post is pre-shaped; or, forming a second metal layer on the carrier; The second metal layer is etched through an etching process to obtain the conductive pillars. 5. The semiconductor packaging method according to claim 1, wherein the forming a plastic sealing layer on the carrier board comprises: An encapsulation layer is formed on the carrier board, the encapsulation layer wraps the to-be-packaged die, the inductance element and the conductive pillar, and the thickness of the encapsulation layer is greater than the height of the conductive pillar; The encapsulation layer is thinned to obtain the plastic encapsulation layer, so that the first ends of the conductive pillars are exposed from the plastic encapsulation layer. 6 . The semiconductor packaging method according to claim 1 , wherein the plastic sealing layer comprises a first opening to expose the first electrical connection point of the inductance element; 6 . The first opening is formed on the plastic sealing layer by a laser drilling process. 7 . The semiconductor packaging method according to claim 6 , wherein the forming the first conductive traces on the side of the plastic packaging layer close to the backside of the die to be packaged comprises: 8 . A first conductive medium is filled in the first opening to form a first conductive filling interface, and a first conductive layer is formed on the plastic encapsulation layer; the first conductive filling interface and the first electrical connection point of the inductance element electrical connection, the first conductive layer is electrically connected to the first conductive filling interface; patterning the first conductive layer to obtain the first conductive traces; Wherein, the first conductive filling interface and the first conductive layer are formed in the same process step. 8 . The semiconductor packaging method according to claim 1 , wherein after forming the first conductive traces on the side of the plastic packaging layer close to the back surface of the to-be-packaged die, the method further comprises: 9 . A first dielectric layer is formed on the first conductive trace, the first dielectric layer wrapping the first conductive trace. 9. The semiconductor packaging method according to claim 3, further comprising: forming a second opening on the protective layer to expose the bonding pads of the die to be packaged; The step of forming a second opening on the protective layer is located after the step of removing the carrier, or after the step of forming a protective layer on the front surface of the die to be packaged, and is located at the before the steps of fixing the bare chip to be packaged and the conductive post on the carrier; When the material of the protective layer is a laser reactive material, the second opening is formed on the protective layer by a laser drilling process; When the material of the protective layer is a photosensitive material, the second opening is formed on the protective layer through a photolithography process. 10 . The semiconductor packaging method according to claim 9 , wherein the forming a second conductive trace on the side of the plastic packaging layer close to the front surface of the die to be packaged comprises: 10 . A second conductive medium is filled in the second opening to form a second conductive filling interface, and a second conductive layer is formed on the plastic encapsulation layer and the protective layer; the second conductive filling interface and the to-be-packaged bare metal interface are formed. The pads of the chip are electrically connected, and the second conductive layer is electrically connected to the second conductive filling interface; patterning the second conductive layer to obtain the second conductive traces; Wherein, the second conductive filling interface and the second conductive layer are formed in the same process step. 11. The semiconductor packaging method of claim 1, wherein the second conductive trace comprises a second electrical connection point, and the second electrical connection point is located away from the second conductive trace and away from the to-be-to-be-conducted trace. One side of the packaged die; after forming the second conductive trace on the side of the plastic encapsulation layer close to the front surface of the to-be-packaged die, further comprising: forming conductive bumps on the second electrical connection points of the second conductive traces; A second dielectric layer is formed on the second conductive traces and the conductive bumps to obtain a plastic package. The second dielectric layer wraps the second conductive traces and the conductive bumps. The conductive bumps are exposed from the second dielectric layer away from the surface of the die to be packaged; The plastic packaging body is cut to obtain a semiconductor packaging structure, the semiconductor packaging structure includes the bare chip to be packaged, the inductance element, the conductive column, the plastic packaging layer, the first conductive trace and the the second conductive trace; or, After the second conductive trace is formed on the side of the plastic encapsulation layer close to the front surface of the die to be encapsulated, the method further includes: forming conductive bumps on the second electrical connection points of the second conductive traces; A second dielectric layer is formed on the second conductive traces and the conductive bumps to obtain a plastic package. The second dielectric layer wraps the second conductive traces and the conductive bumps. The conductive bumps are exposed from the second dielectric layer away from the surface of the die to be packaged; forming a surface treatment layer on the exposed surfaces of the conductive bumps; The plastic packaging body is cut to obtain a semiconductor packaging structure, the semiconductor packaging structure includes the bare chip to be packaged, the inductance element, the conductive column, the plastic packaging layer, the first conductive trace and the the second conductive trace. 12. A semiconductor packaging structure, characterized in that, prepared by using the semiconductor packaging method according to any one of claims 1 to 11, the semiconductor packaging structure comprising: a die to be packaged, the front side of the die to be packaged is provided with a solder pad; an inductance element, located on the backside of the to-be-packaged die; the inductance element includes a first electrical connection point, and the first electrical connection point is located on a side of the inductance element away from the to-be-packaged die; A conductive column is located on the peripheral side of the to-be-packaged die; the conductive column includes a first end and a second end, the first end is located at one end of the conductive column close to the inductance element, and the second end is located at one end of the conductive column away from the inductive element; A plastic encapsulation layer wraps the die to be packaged, the inductance element and the conductive post, the first electrical connection point of the inductance element, the surface of the first end of the conductive post, and the second electrical connection point of the conductive post The surfaces of the ends are respectively exposed from the plastic sealing layer; a first conductive trace, located on the side of the plastic encapsulation layer close to the backside of the to-be-packaged die, and connecting the first electrical connection point of the inductance element and the first end of the conductive column; The second conductive trace is located on the side of the plastic encapsulation layer close to the front surface of the die to be packaged, and connects the bonding pad of the die to be packaged and the second end of the conductive post.

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