CN113937003A - A kind of high voltage MOSFET device and its manufacturing method - Google Patents

Abstract

The invention provides a high-voltage MOSFET device and a manufacturing method thereof, and provides a substrate, a gate dielectric layer is formed on the surface of the substrate, and a polysilicon gate is formed on the gate dielectric layer; several gaps above the gate dielectric layer are formed in the polysilicon gate; Sidewalls are formed on the side of the polysilicon gate; the exposed gate dielectric layer on the surface of the substrate is removed by a photolithography etching process; the source and drain are formed by implanting impurity ions into the substrate using the polysilicon gate and the sidewalls as a mask; forming a covering polysilicon gate , sidewalls, gaps and metal silicide barrier layers of the source and drain; use photolithography to remove the metal silicide barrier on the surface of the gap and source and drain; form metal silicide on the gap and source and drain; use wet The remaining metal silicide barrier layer is removed by an etching process. The invention not only improves the controllability of the metal gate CMP process, but also solves the problem of discontinuous channel and the device cannot work normally, and improves the performance of the device.

Description

High-voltage MOSFET device and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a high-voltage MOSFET device and a manufacturing method thereof.

Background

With the development of semiconductor technology, advanced logic chip processes have reached process processes below the 28nm node. When a large-size (channel length is larger than 2um) high-voltage (HV) MOSFET device is prepared, in order to solve the problem that the controllability of a metal gate CMP process is poor due to the large area of a metal gate, and further the height of the metal gate is seriously lost, a technical scheme that a gap is inserted into pseudo gate polysilicon so as to improve the controllability of the metal gate CMP process is provided.

However, we have found that there is a vulnerability in this solution, as shown in fig. 1, which illustrates an example where the substrate 11 is N-type, and the mosfet device includes a substrate 11, a gate dielectric layer 13, a metal gate 12, a gap 17, a source 15, a drain 16, and a metal silicide 19 located above the source 15 and the drain 16. When a forward voltage is applied to the metal gate 12, the inversion charge layer 14 appears in the channel region under the gate dielectric layer 13, and a channel is formed between the source electrode 15 and the drain electrode 16, but the existence of the gap 17 blocks the continuity of the transfer channel of the inversion charge layer 14, as shown by the solid coil 18, the channel is discontinuous, and thus the device cannot work normally.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a high-voltage MOSFET device and a manufacturing method thereof, which are used for solving the problems that a channel is discontinuous and the device cannot work normally due to gaps.

The invention provides a manufacturing method of a high-voltage MOSFET device, which comprises the following steps:

providing a substrate, wherein a gate dielectric layer is formed on the surface of the substrate, and a polysilicon gate is formed on the gate dielectric layer;

forming a plurality of gaps above the gate dielectric layer in the polysilicon gate;

thirdly, forming a side wall on the side surface of the polysilicon gate;

removing the exposed gate dielectric layer on the surface of the substrate by utilizing a photoetching process;

fifthly, with the polysilicon gate and the side wall as masks, performing impurity ion implantation on the substrate to form a source drain electrode;

sixthly, forming a metal silicide barrier layer covering the polysilicon gate, the side wall, the gap and the source drain electrode;

removing the metal silicide barrier layer on the gap and the surface of the source and drain electrodes by utilizing a photoetching process;

eighthly, forming metal silicide on the gap and the source and drain electrodes;

and step nine, removing the residual metal silicide barrier layer by utilizing a wet etching process.

Preferably, in the first step, the gate dielectric layer is a gate oxide layer.

Preferably, in the second step, the gaps are uniformly distributed in the polysilicon gate, the distance is 1um, and the width is 0.1 um.

Preferably, step four includes the steps of:

step a, forming a photoresist layer with polysilicon gate and side wall patterns;

b, etching the gate dielectric layer which is not blocked by the photoresist by using the photoresist layer as a mask through dry etching;

and c, removing the photoresist layer.

Preferably, the metal silicide barrier layer in the sixth step is an SiO2 film deposited by a chemical vapor deposition method.

Preferably, step seven includes the steps of:

d, forming a photoresist layer with polysilicon gates and side wall patterns on the metal silicide barrier layer;

e, etching the metal silicide barrier layer by using the photoresist layer as a mask and using a dry etching process;

and f, removing the photoresist layer by wet etching.

Preferably, step eight comprises the steps of:

step g, depositing NiPt and TiN by using a physical vapor deposition sputtering process;

h, carrying out first annealing treatment to generate high-resistance metal silicide Ni2 PtSi;

step i, removing TiN and NiPt which does not react with silicon by wet etching;

and j, carrying out secondary annealing treatment to convert the high-resistance state Ni2PtSi into low-resistance state NiPtSi 2.

Preferably, the method further comprises the step ten: and removing the polysilicon gate and depositing to form a metal gate.

The present invention also provides a high voltage MOSFET device comprising:

a substrate;

a source electrode and a drain electrode formed in the substrate;

a gate dielectric layer formed over the substrate;

a metal gate formed over the gate dielectric layer;

a plurality of gaps formed in the metal gate and located on the gate dielectric layer;

the side wall is formed on the side face of the metal gate;

a metal silicide formed over the gap, the source, and the drain; wherein, the clearance is in evenly distributed in the metal gate, the interval is 1um, the width is 0.1 um.

The high-voltage MOSFET device and the manufacturing method thereof of the invention increase the process step of forming the metal silicide on the gap area on the basis of the prior art, solve the problems of disconnection of an inversion layer and discontinuous channels caused by inserting the gap in the polysilicon, and further realize the continuous channels to ensure that the device can normally work on the basis of realizing the controllable process of the metal grid CMP.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 shows a schematic diagram of a high voltage MOSFET device formed in the prior art;

FIG. 2 is a flow chart of a method of fabricating a high voltage MOSFET device in accordance with an embodiment of the present invention;

FIG. 3 is a schematic view of a substrate according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a structure after forming a plurality of gaps according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram after forming a sidewall spacer according to an embodiment of the invention;

FIG. 6 is a schematic structural diagram of the gate dielectric layer exposed on the surface of the etched substrate according to the embodiment of the present invention;

fig. 7 is a schematic structural diagram after source and drain electrodes are formed in the embodiment of the present invention;

FIG. 8 is a schematic diagram illustrating a structure of a metal silicide formed according to an embodiment of the present invention;

fig. 9 shows a schematic diagram of a high voltage MOSFET device which is an embodiment of the invention.

Detailed Description

The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.

Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

Unless the context clearly requires otherwise, throughout this specification, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".

In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.

CMP, collectively known as Chemical Mechanical Polishing, is a high-end upgrade to common Polishing technology. The CMP technology is now widely used in integrated circuit fabrication, from STI (shallow trench isolation) to ILD (inter-layer dielectric) to metal interconnect to top metal at the end of the process.

Metal gates having high dielectric constant gate dielectric layers are commonly employed in processes below 28nm, often abbreviated as HKMG, where HK denotes a high dielectric constant (HK) gate dielectric layer and MG denotes a metal gate. In the forming process of the HKMG, in order to solve the problems of serious height loss and poor process controllability of a metal gate caused by a metal gate CMP process due to large area of the metal gate, a gap (Slot) is inserted in polysilicon to improve the controllability of the metal gate CMP process. But the existence of the gap (Slot) blocks the continuity of an inversion layer transmission channel of the MOS tube, so that the high-voltage device cannot work normally. Therefore, the present invention provides a high voltage MOSFET device and a method for manufacturing the same, and the technical solution of the present invention is further described by the following embodiments with reference to the accompanying drawings.

Fig. 2 is a flow chart showing a method of manufacturing a high voltage MOSFET device according to an embodiment of the present invention. As shown in fig. 2, the method for manufacturing a high voltage MOSFET device according to an embodiment of the present invention includes the following steps:

step one, providing a substrate 1, wherein a gate dielectric layer 2 and a polysilicon gate 3 are formed on the surface of the substrate 1.

As shown in fig. 3, in the embodiment of the present invention, the material of the substrate 1 may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. Shallow trench isolation structures (not shown) are also formed in the substrate 1. The gate dielectric layer 2 is a gate oxide layer silicon dioxide, the polysilicon gate 3 is a pseudo gate, and the length of a channel is larger than 2 um.

And step two, forming a plurality of gaps 4 above the gate dielectric layer 2 in the polysilicon gate 3.

When a large-size (the channel length is more than 2um) device is prepared, in order to solve the problem that the controllability of a metal gate CMP process is poor and the height of the metal gate is seriously lost due to the large area of the metal gate, a gap is inserted into a polysilicon gate. As shown in fig. 4, in the embodiment of the present invention, the gaps 4 are uniformly distributed in the polysilicon gate 3, and the spacing is 1um and the width is 0.1 um. Preferably, a plurality of gaps 4 may be formed in the polysilicon gate 3 by patterning the polysilicon gate 3.

Of course, in other embodiments, other desired distributions of gaps, polysilicon gates, may be patterned.

And step three, forming a side wall 5 on the side surface of the polysilicon gate 3.

In the second step, the polysilicon gate 3 is equally divided into a plurality of small polysilicon gates by the plurality of gaps 4, and as shown in fig. 5, side walls 5 are formed on the side surfaces of the plurality of small polysilicon gates. In the embodiment of the present invention, the material of the sidewall 5 is silicon oxide, silicon nitride, or silicon oxynitride. The side wall 5 may be a single-layer or multi-layer (greater than or equal to two layers) stacked structure.

And step four, removing the exposed gate dielectric layer 2 on the surface of the substrate 1 by utilizing a photoetching process.

Specifically, the fourth step includes the following steps:

step a, forming a photoresist layer with polysilicon gate and side wall patterns;

b, etching the gate dielectric layer which is not blocked by the photoresist by using the photoresist layer as a mask through dry etching;

and c, removing the photoresist layer.

As shown in fig. 6, after etching, a gate dielectric layer 2 is formed at the bottom of the polysilicon gate 3.

And fifthly, performing impurity ion implantation on the substrate by taking the polysilicon gate and the side wall as masks to form a source drain.

As shown in fig. 7, in the embodiment of the present invention, the source and drain electrodes 6 are formed by an ion implantation method, and the implanted impurity ions may be P-type impurity ions or N-type impurity ions.

And sixthly, forming a metal silicide barrier layer covering the polysilicon gate, the side wall, the gap and the source drain electrode.

In the embodiment of the invention, the metal Silicide Area Block (SAB) is a SiO2 film deposited by a chemical vapor deposition method, so that SiO2 is formed to cover the surface of a polysilicon gate and a side wall which do not need to be formed with metal Silicide (Salicide), and the metal Silicide is prevented from being formed by the polysilicon gate and the side wall.

And step seven, removing the metal silicide barrier layers on the surfaces of the gap 4 and the source and drain 6 by utilizing a photoetching process.

Specifically, the seventh step includes the steps of:

d, forming a photoresist layer with polysilicon gates and side wall patterns on the metal silicide barrier layer;

e, etching the metal silicide barrier layer by using the photoresist layer as a mask and using a dry etching process;

and f, removing the photoresist layer by wet etching.

In step f, the SiO2 not covered by the photoresist layer is removed to expose the metal silicide gap region 4 and the source/drain 6 to be formed, so as to prepare for the next metal silicide formation.

Step seven is followed still include: and cleaning the natural oxide layer. Specifically, the chemical solution NH4OH and HF are used to remove the native oxide layer, because the latter process is to deposit NiPt to remove the oxide on the surface more cleanly and to form metal silicide more easily, an acid tank is used to remove the native oxide layer before depositing NiPt.

And step eight, forming metal silicide on the gap and the source and drain electrodes.

Specifically, the step eight includes the steps of:

step g, depositing NiPt and TiN by using a physical vapor deposition sputtering process;

NiPt and thick TiN are deposited by a PVD sputtering process, and the TiN has the function of preventing NiPt from flowing in an RTA stage to cause different thicknesses of metal silicides and local non-uniform resistance values.

H, carrying out first annealing treatment to generate high-resistance metal silicide Ni2 PtSi;

under the environment of high temperature of about 200-300 ℃, N2 is introduced to make NiPt react with the active region and the polysilicon to generate high-resistance metal silicide Ni2 PtSi.

Step i, removing TiN and NiPt which does not react with silicon by wet etching;

in the embodiment of the invention, the TiN and the NiPt which does not react with silicon are removed by wet etching, so that the TiN and the NiPt are prevented from bridging to cause a circuit short circuit.

And j, carrying out secondary annealing treatment to convert the high-resistance state Ni2PtSi into low-resistance state NiPtSi 2.

Under the environment of high temperature of about 400-450 ℃, N2 is introduced to convert the Ni2PtSi in the high resistance state into NiPtSi2 in the low resistance state.

And step nine, removing the residual metal silicide barrier layer by utilizing a wet etching process.

As shown in fig. 8, through steps six to nine, the metal silicide layer 7 is formed.

The manufacturing method of the high-voltage MOSFET device of the embodiment of the invention also comprises the following steps: forming a contact hole etch stop layer (CESL) and an interlayer film;

and removing the polysilicon gate and depositing to form a metal gate.

Specifically, after forming process structures such as a contact hole etching stop layer (CESL) and an interlayer film, the polysilicon gate is removed, and then an HKMG structure is formed in the region where the polysilicon gate is removed. And will not be described in detail herein.

The manufacturing method of the high-voltage MOSFET device increases the process step of forming the metal silicide on the gap region on the basis of the prior art, and solves the problems of disconnection of an inversion charge layer and discontinuous channel caused by inserting the gap in the polysilicon.

Fig. 9 is a schematic structural diagram of a high voltage MOSFET device according to an embodiment of the present invention. As shown in fig. 9, the device includes a substrate 11, a source 15 and a drain 16 formed in the substrate, a gate dielectric layer 13 on the substrate, a metal gate 12 on the gate dielectric layer 13, a plurality of gaps 17 formed in the metal gate 12 and on the gate dielectric layer 13, and a metal silicide 19 formed over the source 15, the drain 16, and the gaps 17.

Compared with the high-voltage MOSFET device in the prior art shown in FIG. 1, the embodiment of the invention forms the metal silicide 19 above the gap 17, the metal silicide 19 is used for making the channel continuous, and as shown by a solid circle 20 in FIG. 9, the existence of the metal silicide 19 solves the problem that the continuity of the transmission channel of the inversion charge layer 14 is blocked due to the existence of the gap 17, and the structure enables the device to normally work, and improves the performance of the device.

It should be understood that many other layers may be present, such as sidewalls, Contact Etch Stop Layers (CESL), interlayer films, spacer elements and/or other suitable components, which are omitted from the illustration for simplicity.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. A method for manufacturing a high voltage MOSFET device, comprising the steps of:

providing a substrate, wherein a gate dielectric layer is formed on the surface of the substrate, and a polysilicon gate is formed on the gate dielectric layer;

forming a plurality of gaps above the gate dielectric layer in the polysilicon gate;

thirdly, forming a side wall on the side surface of the polysilicon gate;

removing the exposed gate dielectric layer on the surface of the substrate by utilizing a photoetching process;

fifthly, with the polysilicon gate and the side wall as masks, performing impurity ion implantation on the substrate to form a source drain electrode;

sixthly, forming a metal silicide barrier layer covering the polysilicon gate, the side wall, the gap and the source drain electrode;

removing the metal silicide barrier layer on the gap and the surface of the source and drain electrodes by utilizing a photoetching process;

eighthly, forming metal silicide on the gap and the source and drain electrodes;

and step nine, removing the residual metal silicide barrier layer by utilizing a wet etching process.

2. The method of claim 1, wherein in step one, the gate dielectric layer is a gate oxide layer.

3. The method of claim 1, wherein in step two, the gaps are uniformly distributed in the polysilicon gate, and have a pitch of 1um and a width of 0.1 um.

4. The method of manufacturing a high voltage MOSFET device according to claim 1, wherein step four comprises the steps of:

step a, forming a photoresist layer with polysilicon gate and side wall patterns;

b, etching the gate dielectric layer which is not blocked by the photoresist by using the photoresist layer as a mask through dry etching;

and c, removing the photoresist layer.

5. The method of claim 1, wherein in step six said metal silicide barrier layer is a SiO2 film deposited by chemical vapor deposition.

6. The method of manufacturing a high voltage MOSFET device according to claim 1, wherein step seven comprises the steps of:

d, forming a photoresist layer with polysilicon gates and side wall patterns on the metal silicide barrier layer;

e, etching the metal silicide barrier layer by using the photoresist layer as a mask and using a dry etching process;

and f, removing the photoresist layer by wet etching.

7. The method of manufacturing a high voltage MOSFET device according to claim 1, wherein step eight comprises the steps of:

step g, depositing NiPt and TiN by using a physical vapor deposition sputtering process;

h, carrying out first annealing treatment to generate high-resistance metal silicide Ni2 PtSi;

step i, removing TiN and NiPt which does not react with silicon by wet etching;

and j, carrying out secondary annealing treatment to convert the high-resistance state Ni2PtSi into low-resistance state NiPtSi 2.

8. The method of manufacturing a high voltage MOSFET device according to claim 1, further comprising: and removing the polysilicon gate and depositing to form a metal gate.

9. A high voltage MOSFET device formed by the method of manufacturing a high voltage MOSFET device according to any of claims 1 to 8, comprising at least:

a substrate;

a source electrode and a drain electrode formed in the substrate;

a gate dielectric layer formed over the substrate;

a metal gate formed over the gate dielectric layer;

a plurality of gaps formed in the metal gate and located on the gate dielectric layer;

the side wall is formed on the side face of the metal gate;

a metal silicide formed over the gap, the source, and the drain; wherein, the clearance is in evenly distributed in the metal gate, the interval is 1um, the width is 0.1 um.

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