JP2006108439A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a low gate leakage current and a threshold voltage and having a CMOS structure.
An NMOSFET includes a gate insulating film made of a silicon oxide film, a hafnium silicate film, and a gate electrode having an N-type polysilicon film formed on the gate insulating film. The PMOSFET includes a gate insulating film made of a silicon oxide film 12, a hafnium silicate film 13, and an aluminum oxide film 14, and a gate electrode having a P-type polysilicon film 16 formed on the gate insulating film. Is provided. The thickness of the aluminum oxide film 14 is preferably 2 nm or less.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a CMOS structure.

  In recent years, high integration in semiconductor integrated circuit devices has greatly advanced, and in MOS (Metal Oxide Semiconductor) type semiconductor devices, elements such as transistors are miniaturized and high performance is achieved. In particular, with regard to the gate insulating film which is one of the elements constituting the MOS structure, the thinning is rapidly progressing to cope with the miniaturization, high speed operation and low voltage of the transistor.

Conventionally, a silicon oxide film has been used as a material constituting the gate insulating film. On the other hand, when the gate insulating film becomes thinner with the miniaturization of the gate electrode, the tunnel current generated by the carriers (electrons and holes) directly tunneling through the gate insulating film, that is, the gate leakage current increases. . However, when a silicon oxide film is used, the gate leakage current due to the tunnel current exceeds an allowable value, and therefore, it is urgent to adopt a new material in place of the SiO ₂ film.

In view of this, research has been conducted on using a material having a higher relative dielectric constant as the gate insulating film instead of the silicon oxide film. Currently, hafnium oxide films, hafnium aluminate films, hafnium silicate films, and the like have been studied as high dielectric constant insulating films (hereinafter referred to as high-k films). Since these films have a relative dielectric constant higher than that of the silicon oxide film (relative dielectric constant 3.9), if the electrical film thickness (silicon oxide film equivalent film thickness) is constant, the film is more physically than the SiO ₂ film. The film thickness can be increased. Therefore, the leakage current can be suppressed by using the High-k film.

  On the other hand, in a conventional CMOSFET (Complementary Metal Oxide Semiconductor), a transistor having a high threshold voltage and a transistor having a low threshold voltage are simultaneously formed on a silicon substrate. Has adopted a dual gate structure using P-type polysilicon (see, for example, Patent Document 1).

JP 2000-174138 A

  However, when a dual-gate CMOSFET is manufactured using a High-k film, there is a problem that the difference in threshold voltage between the N-type transistor and the P-type transistor is reduced to about 0.2 V (Fermi level pinning phenomenon). For this reason, for example, when a hafnium silicate film is used as a gate insulating film, counter doping must be performed on the channel side of the P-type transistor in order to reduce the threshold voltage.

  The present invention has been made in view of such problems. That is, an object of the present invention is to provide a semiconductor device having a low gate leakage current and a low threshold voltage and having a CMOS structure.

  Other objects and advantages of the present invention will become apparent from the following description.

  The semiconductor device of the present invention is a semiconductor device having a CMOSFET composed of an NMOSFET and a PMOSFET on a silicon substrate. The NMOSFET is formed on a silicon oxide film formed on the silicon substrate, and on the silicon oxide film. A gate insulating film made of the formed first metal oxide film and a gate electrode having an N-type polysilicon film formed on the gate insulating film, and the PMOSFET is formed on the silicon substrate. A gate insulating film comprising: a silicon oxide film; a first metal oxide film formed on the silicon oxide film; and a second metal oxide film formed on the first metal oxide film; And a gate electrode having a P-type polysilicon film formed on the gate insulating film, wherein the first metal oxide film is an oxide film containing hafnium. It is an feature.

  In the semiconductor device of the present invention, the first metal oxide film can be either a hafnium oxide film or a hafnium silicate film.

  In the semiconductor device of the present invention, the second metal oxide film can be an aluminum oxide film. In this case, the aluminum oxide film is preferably 2 nm or less in thickness.

  As described above, according to the present invention, the gate insulating film of the NMOSFET includes the silicon oxide film and the first metal oxide film, and the gate insulating film of the PMOSFET includes the silicon oxide film, the first metal oxide film, Since it consists of a 2nd metal oxide film, it can be set as CMOSFET with a low threshold voltage and a gate leak current.

  According to the present invention, in a semiconductor device including a CMOSFET composed of an NMOSFET and a PMOSFET on a silicon substrate, the gate insulating film of the NMOSFET has a structure in which a silicon oxide film and a first metal oxide film are stacked in this order. The gate insulating film of the PMOSFET has a structure in which a silicon oxide film, a first metal oxide film, and a second metal oxide film are stacked in this order. Here, the first metal oxide film is a high dielectric constant insulating film (High-k film). In particular, in the present invention, the first metal oxide film is preferably an oxide film containing hafnium, such as a hafnium oxide film and a hafnium silicate film. The second metal oxide film is preferably an aluminum oxide film. In this case, considering the relative dielectric constant, the thickness of the aluminum oxide film is preferably 2 nm or less. On the other hand, the thickness of the silicon oxide film is preferably 0.5 nm or less for both the PMOSFET and the NMOSFET.

  FIG. 1 is an example of a cross-sectional view of a semiconductor device of the present invention.

  In FIG. 1, an element isolation insulating film 2 is formed around the element region of the silicon substrate 1. Further, in the element region, an N-type diffusion layer region 3, a P-type diffusion layer region 4, a P-type extension region 5, an N-type extension region 6, a P-type source / drain region 7, an N-type source / drain region 8 and A nickel silicide film 9 is formed.

  The gate insulating film of the NMOSFET formed on the channel is composed of a silicon oxide film 10 and a hafnium silicate film 11 as a first metal oxide film formed thereon. Here, the silicon oxide film 10 is a base interface layer.

  On the other hand, the gate insulating film of the PMOSFET has a structure in which a silicon oxide film 12, a hafnium silicate film 13 as a first metal oxide film, and an aluminum oxide film 14 as a second metal oxide film are laminated. Here, the silicon oxide film 12 is a base interface layer.

  When a high-k film is formed directly on the channel region of a silicon substrate, the interface characteristics between the silicon substrate and the gate insulating film are deteriorated, and the carrier mobility is lowered. By providing the base interface layer at the interface between the high-k film and the silicon substrate, the interface characteristics can be improved. In the present invention, in addition to the silicon oxide film, a silicon nitride film or a silicon oxynitride film may be used as the underlying interface layer.

  In FIG. 1, the N-type gate electrode includes an N-type polysilicon film 15 and a metal silicide film 9. On the other hand, the P-type gate electrode is composed of a P-type polysilicon film 16 and a nickel silicide film 9. A silicon nitride film 17 as a sidewall is formed on the sidewall of each gate electrode.

  When an N-type or P-type polysilicon film is formed on the hafnium silicate film, as a result of the Fermi level pinning phenomenon, any polysilicon film has an effective gate electrode work function close to the conduction band of silicon. On the other hand, when an N-type or P-type polysilicon film is formed on the aluminum oxide film, any polysilicon film has an effective gate electrode work function close to the valence band of silicon.

  FIG. 2 shows changes in the flat band voltage of the polysilicon gate electrode depending on the type of the gate insulating film. From the figure, a hafnium silicate film is suitable as the gate insulating film for the NMOSFET and an aluminum oxide film is suitable for the PMOSFET. However, when a laminated film composed only of a silicon oxide film and an aluminum oxide film is used as the gate insulating film of the PMOSFET, a sufficient gate electrode cannot be obtained because the relative dielectric constant of the aluminum oxide film is low.

  According to the present invention, since the stacked film of the silicon oxide film and the hafnium silicate film is used for the NMOSFET and the stacked film made of the silicon oxide film, the hafnium silicate film and the aluminum oxide film is used for the PMOSFET as the gate insulating film, the threshold voltage In addition, a CMOSFET having a low gate leakage current can be obtained.

  Next, an example of a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. In these drawings, the same reference numerals as those in FIG. 1 indicate the same parts.

  First, as shown in FIG. 3A, a silicon oxide film is embedded in a predetermined region of the silicon substrate 1, and an element isolation region 2 and a sacrificial oxide film 18 having an STI (Shallow Trench Isolation) structure are formed. In the present embodiment, a semiconductor substrate such as a strained silicon substrate or a silicon germanium substrate may be used in addition to the silicon substrate 1.

  Next, P (phosphorus) ions are implanted into the silicon substrate 1 using the resist 19 as a mask (FIG. 3B). The implantation of P is performed a plurality of times for the purpose of forming a diffusion layer and adjusting the threshold voltage of the transistor. After the implantation of P, the resist 19 is removed, and B (boron) is implanted into the silicon substrate by the same method. Thereafter, the N-type diffusion layer region 3 and the P-type diffusion layer region 4 are formed by diffusing impurities by heat treatment (FIG. 3C).

After the diffusion layer region is formed, the sacrificial oxide film 18 is removed using an NH ₄ F aqueous solution. Thereafter, a silicon oxide film 19 is formed on the surface of the silicon substrate 1. Further, a hafnium silicate film 21 and an aluminum oxide film 22 are sequentially formed on the silicon oxide film 20 (FIG. 4A).

  Next, in order to selectively remove the aluminum oxide film 22 in the NMOS region, as shown in FIG. 4B, a resist 23 is formed on the aluminum oxide film 22 in the PMOS region. The selective removal of the aluminum oxide film 22 can be realized, for example, by forming the aluminum oxide film 21 and performing a heat treatment at a temperature of about 950 ° C. and then performing wet etching with a hydrofluoric acid solution.

  FIG. 9 shows an example in which the hafnium silicate film and the aluminum oxide film are compared with each other at different measurement points after etching with a hydrofluoric acid solution. From the figure, it can be seen that the aluminum oxide film has a higher etching rate than the hafnium silicate film. That is, by using this, the etching selectivity of the aluminum oxide film to the hafnium silicate film can be increased, and the aluminum oxide film can be selectively removed without substantially removing the hafnium silicate film. Become.

  After the aluminum oxide film 22 is removed, the resist 23 that is no longer needed is removed to obtain the structure of FIG.

  Next, as shown in FIG. 5A, after the polysilicon film 24 is formed, P ions are implanted into the polysilicon film 24 using the resist 25 as a mask in order to form an N-type gate electrode. Next, after removing the resist 25, ions are implanted into the polysilicon film 23 by the same method to form a P-type electrode. Thereafter, a silicon oxide film 26 is formed on the entire surface, and then the silicon oxide film 26 is processed using the resist 27 as a mask to obtain the structure shown in FIG.

  Next, after removing the resist 27, the N-type polysilicon film 15 and the P-type polysilicon film 16 are processed using the silicon oxide film 26 as a mask, thereby forming a gate electrode as shown in FIG. . Further, using the silicon oxide film 26 as a mask, the aluminum oxide film 22, the hafnium oxide film 21, and the silicon oxide film 20 are etched so that the gate insulating film remains only under the gate electrode. Thus, as shown in FIG. 6B, the gate insulating film of the NMOSFET composed of the silicon oxide film 10 and the hafnium silicate film 11, and the gate of the PMOSFET composed of the silicon oxide film 12, the hafnium silicate film 13 and the aluminum oxide film 14. An insulating film is formed. The silicon oxide film 26 disappears by etching.

  Next, B is ion-implanted into the N-type diffusion layer region 3 using the resist 28 and the P-type polysilicon film 16 as a mask (FIG. 7A). Similarly, P is ion-implanted into the P-type diffusion layer region 4 using a resist (not shown) and the N-type polysilicon film 15 as a mask. Thereby, the P-type extension region 5 and the N-type extension region 6 are formed (FIG. 7B).

  Next, as shown in FIG. 7C, a silicon nitride film 29 is formed on the entire surface by the CVD method. Thereafter, the silicon nitride film 29 is removed by reactive ion etching, leaving the side wall of the gate electrode. Thereby, a silicon nitride film 17 as a sidewall is formed.

  Next, as shown in FIG. 8A, B is ion-implanted into the N-type diffusion layer region 3 using the gate electrode on which the resist 30 and the silicon nitride film 17 are formed as a mask. After the resist 30 is removed, P ions are implanted into the P-type diffusion layer region 4 in the same manner. Thereafter, the P-type source / drain region 7 and the N-type source / drain region 8 are formed by activating the impurities by heat treatment (FIG. 8B).

  Next, after forming a nickel film (not shown) and a titanium nitride film (not shown) on the entire surface, heat treatment is performed. Thereafter, the titanium nitride film and the unreacted nickel film are removed by etching, and the nickel silicide film 9 is selectively formed on the source / drain regions 7 and 8 and the N-type polysilicon film 15 and the P-type polysilicon film 16. It forms (FIG.8 (c)). Note that another metal silicide film such as a cobalt silicide film may be formed by forming a cobalt film or the like instead of the nickel film.

  Through the above steps, a structure similar to that shown in FIG. 1 can be obtained. Thereafter, after an interlayer insulating film is formed, planarization is performed by a CMP (Chemical Mechanical Polishing) method, and then contacts and wirings are formed.

  In the present embodiment, the gate electrode is formed using polysilicon, but the present invention is not limited to this. In the present invention, the gate electrode may be formed using germanium, silicon germanium, tungsten, or the like in addition to polysilicon. When the gate electrode has a stacked structure including a layer made of a metal such as tungsten, it is not necessary to form a metal silicide layer on the gate electrode. In addition to the above dual gate, the present invention can be applied to a triple gate, a vertical transistor, a Fin transistor, or the like.

It is sectional drawing of the semiconductor device concerning this Embodiment. It is the figure which showed the change of the flat band voltage of the polysilicon gate electrode by the kind of gate insulating film. (A)-(c) is sectional drawing which shows the manufacturing process of the semiconductor device concerning this Embodiment. (A)-(c) is sectional drawing which shows the manufacturing process of the semiconductor device concerning this Embodiment. (A)-(b) is sectional drawing which shows the manufacturing process of the semiconductor device concerning this Embodiment. (A)-(b) is sectional drawing which shows the manufacturing process of the semiconductor device concerning this Embodiment. (A)-(c) is sectional drawing which shows the manufacturing process of the semiconductor device concerning this Embodiment. (A)-(c) is sectional drawing which shows the manufacturing process of the semiconductor device concerning this Embodiment. It is an example in which the film thickness after etching with a hydrofluoric acid solution is compared between a hafnium silicate film and an aluminum oxide film.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation insulating film 3 N type diffused layer area | region 4 P type diffused layer area | region 5 P type extension area | region 6 N type extension area | region 7 P type source / drain area | region 8 N type source / drain area | region 9 Nickel silicide film 10, 12, 20, 26 Silicon oxide film 11, 13, 21 Hafnium silicate film 14, 22 Aluminum oxide film 15 N-type polysilicon film 16 P-type polysilicon film 17, 29 Silicon nitride film 18 Sacrificial oxide film 19, 23, 25, 27, 28, 30 Resist 24 Polysilicon film

Claims (4)

In a semiconductor device comprising a CMOSFET composed of an NMOSFET and a PMOSFET on a silicon substrate,
The NMOSFET includes a gate insulating film formed of a silicon oxide film formed on the silicon substrate and a first metal oxide film formed on the silicon oxide film,
A gate electrode having an N-type polysilicon film formed on the gate insulating film,
The PMOSFET includes a silicon oxide film formed on the silicon substrate, a first metal oxide film formed on the silicon oxide film, and a first metal oxide film formed on the first metal oxide film. A gate insulating film composed of two metal oxide films;
A gate electrode having a P-type polysilicon film formed on the gate insulating film,
The semiconductor device according to claim 1, wherein the first metal oxide film is an oxide film containing hafnium.   The semiconductor device according to claim 1, wherein the first metal oxide film is one of a hafnium oxide film and a hafnium silicate film.   The semiconductor device according to claim 1, wherein the second metal oxide film is an aluminum oxide film. The semiconductor device according to claim 3, wherein the aluminum oxide film has a thickness of 2 nm or less.

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