CN113903794A - Method for fabricating semiconductor device including trench gate and semiconductor device - Google Patents
Method for fabricating semiconductor device including trench gate and semiconductor device Download PDFInfo
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- CN113903794A CN113903794A CN202010639449.8A CN202010639449A CN113903794A CN 113903794 A CN113903794 A CN 113903794A CN 202010639449 A CN202010639449 A CN 202010639449A CN 113903794 A CN113903794 A CN 113903794A
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- trench
- epitaxial layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000002360 preparation method Methods 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 5
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 8
- 230000005669 field effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005429 filling process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a preparation method of a semiconductor device comprising a trench gate, which comprises the following steps: 1) forming an epitaxial layer on a semiconductor substrate, and forming a trench in the epitaxial layer; 2) etching the upper surface of the epitaxial layer and the inner wall of the trench to enable the diameter of the top of the trench to be larger than that of the bottom of the trench; 3) forming a shielding oxide layer on the upper surface of the epitaxial layer and the inner wall and the bottom of the groove; and 4) filling polycrystalline silicon in the groove to form a groove gate. The method effectively eliminates the gap in the trench gate. The invention also provides a semiconductor device prepared by using the method.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor device comprising a trench gate and the semiconductor device prepared by the method.
Background
The process of manufacturing a Power field effect transistor (Power MOSFET) based on trench technology typically comprises the following steps as shown in fig. 1: trenches 003 (see fig. 2a) are formed in the epitaxial layer 002 over the substrate 001 by etching based on the mask layer-the mask layer is removed and a shield oxide layer 004 (see fig. 2b) is formed on the surface of the trenches 003 and the top surface of the epitaxial layer 002-the trenches 003 are filled with polysilicon 002 to form trench gates (see fig. 2 c). However, for the trench with a large aspect ratio, the gap 006 is often formed in the middle of the trench gate due to insufficient filling capability of the polysilicon 005, and the like, and the gap can penetrate through the entire trench 003, so that the subsequent processes cannot be performed smoothly and the device performance is affected.
Therefore, how to eliminate the gap in the trench gate becomes an urgent technical problem to be solved in the field of semiconductor device manufacturing.
Disclosure of Invention
In order to solve the technical problem in the prior art, the invention provides a preparation method of a semiconductor device for effectively eliminating a gap in a trench gate and the semiconductor device prepared by using the method.
According to the present invention, there is provided a method of manufacturing a semiconductor device including a trench gate, comprising the steps of:
1) forming an epitaxial layer on a semiconductor substrate, and forming a trench in the epitaxial layer;
2) etching the upper surface of the epitaxial layer and the inner wall of the trench to enable the diameter of the top of the trench to be larger than that of the bottom of the trench;
3) forming a shielding oxide layer on the upper surface of the epitaxial layer and the inner wall and the bottom of the groove; and
4) and filling polysilicon in the trench to form a trench gate.
According to one embodiment of the present invention, step 1) includes forming a trench on the epitaxial layer based on the mask layer over the epitaxial layer, and removing the mask layer.
According to an embodiment of the present invention, step 2) comprises: 2.1) carrying out dry etching on the upper surface of the epitaxial layer, so that a first inclined surface is formed on the inner wall of the groove adjacent to the upper surface of the epitaxial layer, and an opening with the diameter larger than that of the bottom of the groove is formed in a region surrounded by the first inclined surface.
According to an embodiment of the present invention, step 2) comprises:
2.2) forming a sacrificial oxide layer on the upper surface of the epitaxial layer and the inner wall and the bottom of the groove;
2.3) removing the sacrificial oxide layer to enlarge the opening and form a second inclined plane on the inner wall outside the opening, wherein the diameter of the area surrounded by the second inclined plane is gradually increased from the bottom of the groove to the top of the groove.
According to one embodiment of the present invention, the average thickness of the sacrificial oxide layer is
According to one embodiment of the invention, the first inclined surface forms a first angle with the vertical, the first angle being 30-60 °.
According to an embodiment of the present invention, the second inclined surface forms a second included angle with the vertical direction, and a slope of the second included angle is 1:30 to 1: 20.
According to one embodiment of the present invention, the preparation method comprises: and 5) annealing the semiconductor device.
According to one embodiment of the present invention, the annealing process comprises heating the trench gate to 800-.
According to the present invention, there is provided a semiconductor device manufactured using the above method.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages:
1. according to the invention, the opening with the diameter larger than that of the bottom of the groove is formed at the top of the groove by adding dry etching, and the diameter of the groove is gradually increased along the direction far away from the bottom by sacrificing the oxide layer, so that the overall profile of the groove is improved, the possibility that polycrystalline silicon is closed at the top of the groove too early in the filling process is reduced, and the probability of forming a gap in the middle of a groove gate is reduced;
2. even if the gap is formed, the internal material of the polysilicon can be homogenized through a post annealing process, and the gap can be eliminated.
Drawings
Fig. 1 shows a flow chart of a prior art process for manufacturing a power field effect transistor;
FIGS. 2a-2c show schematic diagrams of a prior art process for fabricating a power field effect transistor;
fig. 3 shows a flow chart of a method of manufacturing a semiconductor device comprising a trench gate according to the present invention;
fig. 4a-4g show schematic views of a semiconductor device fabricated by the method of fig. 3.
In the figure, the position of the upper end of the main shaft,
001 substrate, 002 epitaxial layer, 003 trench, 004 shielding oxide layer, 005 polysilicon, 006 gap, 100 substrate, 200 epitaxial layer, 210 first inclined plane, 220 second inclined plane, 300 trench, 400 sacrificial oxide layer, 500 shielding oxide layer, 600 polysilicon, 700 primary gap, 700' secondary gap, a first angle, b second angle.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It should be appreciated by those skilled in the art that all expressions using "first", "second", "first" and "second" in the embodiments of the present invention are intended to distinguish two entities with the same name but different names, and it is understood that "first", "second", "first" and "second" are only for convenience of description and should not be construed as limiting the embodiments of the present invention, and the descriptions thereof in the following embodiments are omitted. Also, the terms of orientation in the embodiments of the present invention are all referred to semiconductor devices that are horizontally placed during normal manufacturing processes. For example, "the upper surface of the epitaxial layer" refers to the surface of the epitaxial layer away from the substrate; "vertical" is the direction perpendicular to the horizontally disposed substrate layer.
As shown in fig. 3 and 4a-4g, the method of manufacturing a semiconductor device including a trench gate according to the present invention generally includes the steps of:
1) an epitaxial layer 200 is formed on a semiconductor substrate 100 and trenches 300 are formed in the epitaxial layer 200 (fig. 4 a). Specifically, a mask layer may be covered over the epitaxial layer 200, and the trench 300 may be formed on the epitaxial layer 200 by etching, and then the mask layer may be removed.
2) The surface of epitaxial layer 200 and the inner walls of trench 300 are etched such that the diameter of the top of trench 300 is greater than the diameter of the bottom of the trench. In the embodiment of the present invention, the trench 300 having the above-described shape may be formed by a combination of dry etching and wet etching, and, in particular,
2.1) dry etching the surface of the epitaxial layer 200 so that a portion of the material at the junction of the upper surface of the epitaxial layer 200 and the inner wall of the trench 300 is removed, thereby forming a first inclined surface 210 (fig. 4b) at the inner wall of the trench 300 adjacent to the upper surface of the epitaxial layer 200, so that the area surrounded by the first inclined surface 210 may constitute an opening having a diameter greater than the diameter of the bottom of the trench 300. The first inclined surface 210 forms a first angle a with the vertical, which may be 30-60 °, preferably 45 °.
2.2) forming the upper surface of the epitaxial layer 200 and the inner wall and bottom of the trench 300 to a thickness of
-preferably
Sacrificial oxide layer 400 (fig. 4 c).
2.3) removing the sacrificial oxide layer 400 by wet etching, on the one hand, the opening can be further enlarged, and on the other hand, the second inclined surface 220 can be formed on the inner wall of the trench 300 outside the opening (fig. 4d), so that the diameter of the region surrounded by the second inclined surface 220 gradually increases from the bottom to the top of the trench 300. The second inclined surface 220 forms a second included angle b with the vertical direction, and the slope of the second included angle b may be 1:30 to 1:20, preferably 1: 35.
3) A screen oxide layer 500 is formed on the upper surface of the epitaxial layer 200 and on the inner walls and bottom of the trenches 300 (fig. 4 e).
4) The trench 300 is filled with polysilicon 600 to form a trench gate (fig. 4 f).
The trenches 300 after dry and wet etching have a generally wide and narrow profile, and particularly have a relatively large diameter opening at the top, which reduces the likelihood of premature closure of the polysilicon 600 at the top of the trench 300 during the filling process, and avoids the formation of gaps in the trench gate, or only the formation of a gap 700 of a smaller size.
Preferably, the method for manufacturing a semiconductor device including a trench gate according to the present invention may further include step 5) annealing the semiconductor device, for example, heating the trench gate to 800 ℃. — (1000 ℃), so as to homogenize the polysilicon internal material, thereby transforming the first gap 700 into a second gap 700' (fig. 4g) with a smaller size, or completely eliminating the first gap 700.
The semiconductor device prepared by the method can effectively avoid forming gaps which can affect the subsequent process or the device performance in the trench gate, thereby improving the yield of the semiconductor device.
The above examples only express embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010639449.8A CN113903794A (en) | 2020-07-06 | 2020-07-06 | Method for fabricating semiconductor device including trench gate and semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010639449.8A CN113903794A (en) | 2020-07-06 | 2020-07-06 | Method for fabricating semiconductor device including trench gate and semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| CN113903794A true CN113903794A (en) | 2022-01-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202010639449.8A Pending CN113903794A (en) | 2020-07-06 | 2020-07-06 | Method for fabricating semiconductor device including trench gate and semiconductor device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010006836A1 (en) * | 1994-02-04 | 2001-07-05 | Katsumi Nakamura | Method of forming a trench mos gate on a power semiconductor device |
| TW457567B (en) * | 2000-07-17 | 2001-10-01 | Mosel Vitelic Inc | Manufacturing method for gate oxide layer |
| US6495294B1 (en) * | 1999-10-28 | 2002-12-17 | Denso Corporation | Method for manufacturing semiconductor substrate having an epitaxial film in the trench |
| CN103311299A (en) * | 2012-03-09 | 2013-09-18 | 飞兆半导体公司 | Shielded gate mosfet device with a funnel-shaped trench |
-
2020
- 2020-07-06 CN CN202010639449.8A patent/CN113903794A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010006836A1 (en) * | 1994-02-04 | 2001-07-05 | Katsumi Nakamura | Method of forming a trench mos gate on a power semiconductor device |
| US6495294B1 (en) * | 1999-10-28 | 2002-12-17 | Denso Corporation | Method for manufacturing semiconductor substrate having an epitaxial film in the trench |
| TW457567B (en) * | 2000-07-17 | 2001-10-01 | Mosel Vitelic Inc | Manufacturing method for gate oxide layer |
| US20020006704A1 (en) * | 2000-07-17 | 2002-01-17 | Mosel Vitelic Inc. | Process for forming gate oxide layer |
| CN103311299A (en) * | 2012-03-09 | 2013-09-18 | 飞兆半导体公司 | Shielded gate mosfet device with a funnel-shaped trench |
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Application publication date: 20220107 |