CN113838803A

CN113838803A - Semiconductor structure and method of forming the same

Info

Publication number: CN113838803A
Application number: CN202010584728.9A
Authority: CN
Inventors: 王楠
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-06-24
Filing date: 2020-06-24
Publication date: 2021-12-24
Anticipated expiration: 2040-06-24
Also published as: CN113838803B

Abstract

A semiconductor structure and a method for forming the same. The forming method includes: after forming a trench, laterally etching a sacrificial layer exposed by the trench to form a first groove, and performing a process on the sacrificial layer exposed by the first groove in a second region. Lateral etching to form a second groove, the lateral dimension of the sacrificial layer under the gate structure in the second region is smaller than the lateral dimension of the sacrificial layer under the gate structure in the first region, the dummy gate structure and the sacrificial layer are removed, and a gate is formed After the pole structure is formed, the lateral dimension of the gate structure in contact with the channel layer in the second region is smaller, and the lateral dimension of the gate structure in the first region in contact with the channel layer is larger. When the semiconductor structure is in operation, the lateral dimension of the channel in the first region is larger than the lateral dimension of the channel in the second region, and the transistor formed in the first region has small on-current, low power consumption, and low leakage current probability. The transistor formed in the second region has a large on-current and a fast response speed.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, the feature size of the integrated circuit is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is also continuously shortened correspondingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the controllability of the gate structure to the channel is deteriorated, and the difficulty of the gate voltage to pinch off the channel is increased, so that the sub-threshold leakage (SCE) phenomenon, i.e. the so-called short-channel effect (SCE), is more likely to occur.

Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar transistors to more power efficient three-dimensional transistors, such as Gate-all-around (GAA) transistors. In the fully-surrounded metal gate transistor, the gate surrounds the region where the channel is located from the periphery, and compared with a planar transistor, the fully-surrounded metal gate transistor has stronger control capability on the channel by the gate, and can better inhibit a short-channel effect.

The full-gate nanowire can be obtained by adding only two process modules in the existing replacement gate fin field effect transistor (FinTET) process flow, wherein the two process modules are as follows: one is to grow a layer of Silicon on bulk Silicon (bulk Silicon) or SOI wafer, which avoids leakage of bulk Silicon material. Second, selectively remove the silicon germanium on the replaceable metal gate loop, and then use HKMG (high-k insulating layer + metal gate) to stack the surrounding silicon channel to form the all-around metal gate transistor.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize electrical properties of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first region and a second region, the substrate comprises a substrate, a channel lamination layer separated from the substrate and a pseudo gate structure crossing the channel lamination layer, the pseudo gate structure covers partial top wall and partial side wall of the channel lamination layer, the channel lamination layer comprises a sacrificial layer and a channel layer which are alternately stacked, and the bottommost part of the channel lamination layer is the sacrificial layer; etching the channel lamination layers on two sides of the pseudo gate structure, and forming a groove in the channel lamination layers; transversely etching the sacrificial layer exposed out of the groove by taking the extending direction which is parallel to the surface of the substrate and vertical to the pseudo gate structure as a transverse direction to form a first groove; transversely etching the sacrificial layer exposed out of the first groove in the second area to form a second groove; forming a side wall material layer in the first groove and the second groove; after the side wall material layer is formed, removing the pseudo gate structure to form a gate opening; after the grid opening is formed, removing the sacrificial layer to form a channel; a gate structure is formed in the channel and gate opening.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate comprising a first region and a second region; the source-drain doping layer is separated on the substrate; the channel layers are suspended on the substrate at intervals in the normal direction of the surface of the substrate and are positioned between the source-drain doped layers; the grid structure surrounds the channel layer and takes the extending direction which is parallel to the surface of the substrate and vertical to the grid structure as the transverse direction; the first side wall layer is positioned between the source-drain doping layer and the grid structure in the first region; and the second side wall layer is positioned between the source-drain doped layer and the grid structure in the second region, and the transverse dimension of the second side wall layer is greater than that of the first side wall layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the method for forming a semiconductor structure provided by the embodiment of the present invention, the base includes a first region and a second region, and in the step of providing the base, the base includes a substrate and a channel stack located on the substrate, trenches are formed in the channel stack at both sides of the dummy gate structure, and accordingly, a lateral dimension of the channel stack between the trenches of the first region is the same as a lateral dimension of the channel stack between the trenches of the second region, after the trenches are formed in the channel stack at both sides of the dummy gate structure, the sacrificial layer exposed by the trenches is laterally etched to form a first groove, and the sacrificial layer exposed by the first groove in the second region is laterally etched to form a second groove, where a lateral dimension of the second groove is greater than a lateral dimension of the first groove, and a lateral dimension of the sidewall material layer correspondingly formed in the second groove is greater than a lateral dimension of the material layer formed in the first groove The lateral dimension of the sacrificial layer below the gate structure in the second region is smaller than the lateral dimension of the sacrificial layer below the gate structure in the first region, the dummy gate structure and the sacrificial layer are removed, after the gate structure is formed, the lateral dimension of the gate structure in the second region, which is in contact with the channel layer, is smaller, the lateral dimension of the gate structure in the first region, which is in contact with the channel layer, is larger, correspondingly, when the semiconductor structure works, the lateral dimension of the channel in the first region is larger than the lateral dimension of the channel in the second region, the transistor formed in the first region has small conduction current, small power consumption and small leakage current probability, and the transistor formed in the second region has large conduction current and high response speed.

Drawings

Fig. 1 to 3 are schematic structural diagrams of key steps in a method for forming a semiconductor structure;

fig. 4 to 13 are schematic structural views corresponding to steps in the first embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention;

fig. 14 is a schematic structural diagram of a second embodiment of a semiconductor structure in accordance with an embodiment of the present invention.

Detailed Description

As can be seen from the background art, the performance of the devices formed at present is still not good. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.

Referring to fig. 1 to 3, there are shown schematic structural diagrams of key steps in a method for forming a semiconductor structure.

As shown in fig. 1, a base, which includes a first region I and a second region II, includes a substrate 1 and a channel stack 2 on the substrate 1, the channel stack 2 includes a sacrificial layer 21 and a channel layer 22 on the sacrificial layer 21; the pseudo gate structure 4 is positioned on the channel lamination layer 2, the pseudo gate structure 4 covers part of the top wall and part of the side wall of the channel lamination layer 2, and the extending direction which is parallel to the surface of the substrate 1 and vertical to the pseudo gate structure 4 is taken as the transverse direction; the source-drain doping layer 3 is positioned in the channel laminated layer 2 at two sides of the pseudo gate structure 4; the inner side wall layer 7 is positioned between the sacrificial layer 21 and the source drain doping layer 3; and the interlayer dielectric layer 6 is positioned on the side part of the dummy gate structure 4, and the top surface of the interlayer dielectric layer 6 is flush with the top surface of the dummy gate structure 4.

As shown in fig. 2, removing the dummy gate structure 4 to form a gate opening 5; after the gate opening 5 is formed, the sacrificial layer 21 is removed, and a first channel 8 surrounded by the substrate 1, the channel layer 22, and the inner sidewall layer 7, and a second channel 9 surrounded by the channel layer 22 and the inner sidewall layer 7 are formed.

As shown in fig. 3, a gate structure 10 is formed in the gate opening 5, the first channel 8 and the second channel 9.

The semiconductor structure is higher towards the integration level, and the semiconductor process gradually starts to transition from a planar transistor to a three-dimensional transistor with higher efficiency, such as a Gate-all-around (GAA) transistor, and the Gate of the GAA transistor has stronger control capability on a channel, so that the short channel effect can be better inhibited. Usually, the dummy gate structures 4 in the first device region I and the second device region II are formed by a self-aligned dual patterning process (SADP), and the corresponding dummy gate structures 4 in the first device region I and the dummy gate structures 4 in the second device region II have the same lateral dimension. With the requirement of a semiconductor structure, the channels in the first device region I and the second device region II need different lengths to meet different process requirements.

In order to solve the technical problem, in the method for forming a semiconductor structure provided in an embodiment of the present invention, the base includes a first region and a second region, in the step of providing the base, the base includes a substrate and a channel stack located on the substrate, trenches are formed in the channel stack on both sides of the dummy gate structure, accordingly, a lateral dimension of the channel stack between the trenches of the first region is the same as a lateral dimension of the channel stack between the trenches of the second region, after the trenches are formed in the channel stack on both sides of the dummy gate structure, the sacrificial layer exposed by the trenches is laterally etched to form a first groove, the sacrificial layer exposed by the first groove in the second region is laterally etched to form a second groove, a lateral dimension of the second groove is greater than a lateral dimension of the first groove, correspondingly, the lateral dimension of the side wall material layer formed in the second groove is larger than that of the side wall material layer formed in the first groove, the lateral dimension of the sacrificial layer below the gate structure in the second region is smaller than that of the sacrificial layer below the gate structure in the first region, the dummy gate structure and the sacrificial layer are removed, after the gate structure is formed, the lateral dimension of the gate structure in the second region in contact with the channel layer is smaller, the lateral dimension of the gate structure in the first region in contact with the channel layer is larger, correspondingly, when the semiconductor structure works, the lateral dimension of the channel in the first region is larger than that of the channel in the second region, the transistor formed in the first region has small conduction current and power consumption, the probability of leakage current is smaller, and the conduction current of the transistor formed in the second region is larger, the response speed is high.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Fig. 4 to fig. 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 4 and 5, fig. 5 is a cross-sectional view of fig. 4 in the direction AA, a base is provided, the base includes a first region and a second region, the base includes a substrate 100, a channel stack separated from the substrate 100, and a dummy gate structure 103 crossing the channel stack, the dummy gate structure 103 covers a part of a top wall and a part of a sidewall of the channel stack, the channel stack includes a sacrificial layer 101 and a channel layer 102 which are alternately stacked, and a bottommost portion of the channel stack is the sacrificial layer 101.

In this embodiment, the method for forming a semiconductor structure is used to form a semiconductor structure in which a channel length of a transistor formed in a first region is longer than a channel length of a transistor formed in a second region.

The substrate 100 is used to provide a process platform for subsequently forming semiconductor structures.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

The channel stack is used to provide a process foundation for the subsequent formation of the suspended channel layer 102. The sacrificial layer 101 is used to support the channel layer 102, provide process conditions for the spacer-floating arrangement of the subsequent channel layer 102, and also occupy space for the subsequently formed gate structure.

In this embodiment, the difficulty of etching the channel layer 102 is greater than the difficulty of etching the sacrificial layer 101, and the channel layer 102 is not easily damaged when the sacrificial layer 101 is subsequently removed.

In this embodiment, the material of the channel layer 102 is silicon; the material of the sacrificial layer 101 is silicon germanium. In other embodiments, the channel layer may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the sacrificial layer may also be made of silicon accordingly.

In this embodiment, the topmost film layer in the channel stack is the sacrificial layer 101. In other embodiments, the topmost film layer in the channel stack is a channel layer.

The dummy gate structure 103 occupies a space for forming a gate structure in a subsequent process.

In this embodiment, the dummy gate structure 103 includes a dummy gate oxide layer (not shown) conformally covering a portion of the top surface and a portion of the sidewalls of the channel stack and a dummy gate layer (not shown) on the dummy gate oxide layer.

In this embodiment, the material of the dummy gate oxide 1031 is silicon oxide. In other embodiments, the material of the dummy gate oxide layer may also be silicon oxynitride.

In this embodiment, the material of the dummy gate layer 1032 is polysilicon. In other embodiments, the material of the dummy gate layer may also be amorphous carbon.

The step of forming the dummy gate structure 103 includes: forming a dummy gate oxide material layer (not shown) covering the channel stack and a dummy gate material layer (not shown) on the dummy gate oxide layer; forming a gate mask layer 104 on the dummy gate material layer; and etching the pseudo gate oxide material layer and the pseudo gate oxide material layer by taking the gate mask layer 104 as a mask, wherein the residual pseudo gate oxide material layer is taken as the pseudo gate oxide 1031, and the residual pseudo gate material layer is taken as the pseudo gate layer 1032.

It should be noted that, taking the extending direction parallel to the surface of the substrate 100 and perpendicular to the dummy gate structure 103 as a lateral direction, in this embodiment, the lateral dimensions of the dummy gate structures in the first region and the second region are the same, which simplifies the forming process of the dummy gate structure 103 and is beneficial to improving the forming efficiency of the dummy gate structure 103.

In the step of providing the substrate, a gate sidewall layer 105 is formed on the sidewall of the dummy gate structure 103.

The gate sidewall layer 105 is used for defining a formation position of a source-drain doping layer formed subsequently, and is also used for protecting a sidewall of the dummy gate structure 103 from being damaged in a formation process of a subsequent semiconductor structure.

The material of the gate sidewall layer 105 includes: one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride boron silicon nitride, and boron nitride silicon carbide.

In this embodiment, both the first region and the second region may be used to form an nmos (negative Channel Metal Oxide semiconductor) or a pmos (positive Channel Metal Oxide semiconductor). In other embodiments, one of the first region and the second region may be an NMOS and one may be a PMOS.

It should be further noted that, the bottom-most end of the channel stack is the sacrificial layer 101, the sacrificial layer 101 at the bottom-most end is subsequently removed to form a channel, the channel is prepared for the subsequent formation of the gate structure, the channel layer 102 at the bottom-most end of the channel stack can be surrounded by the gate structure, and accordingly, the channel layer 102 at the bottom-most end is easily depleted when the semiconductor structure operates, which is beneficial to improving the electrical performance of the semiconductor structure.

In this embodiment, in the step of providing the substrate, the topmost layer of the channel stack is the sacrificial layer 101. In other embodiments, in the step of providing a substrate, a topmost layer of the channel stack is a channel layer.

It should be further noted that in the step of providing a substrate, the substrate further includes: a fin 112 protruding from the substrate 100, wherein the fin 112 is located between the substrate 100 and the channel stack; an isolation layer 113 on the substrate 100 where the fin portion 112 is exposed; the dummy gate structure 103 is located on the isolation layer 113.

The fin 112 protrudes from the substrate 100, and the side of the fin 112 provides a process space for the isolation layer 113.

In this embodiment, the material of the fin portion 112 is the same as that of the substrate 100. In other embodiments, the material of the fin may also be different from the material of the substrate.

The isolation layer 113 electrically isolates a gate structure formed by the replacement dummy gate structure 113 from the substrate 100, and the isolation layer 113 is used for further electrically isolating the fins 112.

In this embodiment, the isolation layer 113 is made of a dielectric material. Specifically, the isolation layer 113 includes silicon oxide, which is a dielectric material with a common process and a low cost, and has a high process compatibility, thereby facilitating reduction of process difficulty and process cost for forming the isolation layer 113.

In this embodiment, the dummy gate structure 103 is located on the isolation layer 113, and the dummy gate structure 103 crosses over the fin 112 and covers a part of the top wall and a part of the sidewall of the fin 112.

Referring to fig. 6, the channel stack on both sides of the dummy gate structure 103 is etched, and a trench 106 is formed in the channel stack.

The trench 106 is used for preparing a subsequent side wall material layer, and the trench 106 also provides a process space for the subsequent formation of a source-drain doped layer.

In this embodiment, the gate mask layer 104 is used as a mask to etch the channel stacks on both sides of the dummy gate structure 103 by using a dry etching process, so as to form the trench 106. The dry etching process has anisotropic etching characteristics and good etching profile controllability, is beneficial to enabling the appearance of the groove 106 to meet the process requirements, and can reduce the damage to other film layer structures by taking the top of the fin portion 112 as an etching stop position in the process of forming the groove 106 by adopting the dry etching process. Moreover, by replacing the etching gas, the sacrificial layer 101 and the channel layer 102 can be etched in the same etching apparatus, which is advantageous to increase the formation rate of the trench 106.

In other embodiments, a wet etching process or a combination of a dry etching process and a wet etching process may be used to etch the channel stack layers on both sides of the dummy gate structure to form a trench.

Referring to fig. 7, the sacrificial layer 101 exposed by the trench 106 is laterally etched with the extending direction of the dummy gate structure 103 being a lateral direction parallel to the surface of the substrate 100, so as to form a first groove 107.

The first groove 107 of the first region I provides a process space for forming a subsequent side wall material layer, the first groove 107 of the first region I is used for limiting the length of a channel region in the subsequent first region I, and the first groove 107 of the second region II provides for forming a second groove by subsequent further etching.

In this embodiment, the sacrificial layer 101 exposed by the trench 106 is laterally etched by using a wet etching process to form the first groove. The wet etching process is isotropic etching, has high etching rate, and is simple to operate and low in process cost. In other embodiments, the sacrificial layer exposed by the trench may be laterally etched by an isotropic dry etching process to form the first groove.

In this embodiment, the sacrificial layer 101 is made of silicon germanium, and correspondingly, in the process of laterally etching the sacrificial layer 101 exposed by the trench 106 by using a wet etching process, the wet etching solution used in the process includes an HCl solution.

Referring to fig. 8, the sacrificial layer 101 exposed by the first groove 107 in the second region II is laterally etched to form a second groove 108.

The base comprises a first region I and a second region II, in the step of providing the base, the base comprises a substrate 100 and a channel lamination layer positioned on the substrate 100, trenches 106 are formed in the channel lamination layer on two sides of the pseudo gate structure 103, correspondingly, the transverse dimension of the channel lamination layer between the trenches 106 of the first region I is the same as the transverse dimension of the channel lamination layer between the trenches of the second region II, after the trenches 106 are formed in the channel lamination layer on two sides of the pseudo gate structure 103, the sacrificial layer 101 exposed from the trenches 106 is transversely etched to form a first groove 107, the sacrificial layer 101 exposed from the first groove 107 in the second region II is transversely etched to form a second groove 108, the transverse dimension of the second groove 108 is larger than the transverse dimension of the first groove 107, and the transverse dimension of a sidewall material layer subsequently formed in the second groove 108 is larger than the sidewall material layer formed in the first groove 107 Correspondingly, after the lateral dimension of the sacrificial layer 101 below the gate structure in the second region II is smaller than the lateral dimension of the sacrificial layer 101 below the gate structure in the first region I, the dummy gate structure 103 and the sacrificial layer 101 are removed, and a gate structure is formed, the lateral dimension of the gate structure in the first region I in contact with the channel layer 102 is larger, the lateral dimension of the gate structure in the second region II in contact with the channel layer 102 is smaller, correspondingly, when the semiconductor structure works, the lateral dimension of the channel in the first region I is larger than the lateral dimension of the channel in the second region II, the transistor formed in the first region I has small conduction current and power consumption, and the leakage current probability is smaller, and the transistor formed in the second region II has large conduction current and high response speed.

The second groove 108 in the second region II provides a process space for forming a subsequent side wall material layer, and the second groove 108 in the second region II is used for defining the length of a channel region in the subsequent second region II.

The second groove 108 provides a process space for the subsequent formation of a side wall material layer.

The step of forming the second groove 108 includes: forming a shielding layer 109 covering the first groove 107 of the first region I and exposing the first groove 107 of the second region II; and performing lateral etching on the sacrificial layer 101 exposed from the first groove 107 in the second region II by using the shielding layer 109 as a mask to form the second groove 108.

The shielding layer 109 is a material easy to remove, and damage to the formed film layer can be reduced when the shielding layer 109 is subsequently removed.

The material of the shielding layer 109 is an organic material. Specifically, the material of the shielding layer 109 includes: one or more of a bottom-anti-reflective coating (BARC) material, a spin-on-carbon (SOC) material, an Organic Dielectric Layer (ODL) material, a photoresist, a dielectric anti-reflective coating (DARC) material, a DUO material, or an Advanced Patterning Film (APF) material. In this embodiment, the material of the shielding layer 109 includes photoresist.

The step of forming the shielding layer 109 includes: forming a shielding material layer (not shown in the figure) covering the first area I and the second area II; the masking material layer is patterned, and the remaining masking material layer serves as a masking layer 109.

In this embodiment, the blocking material layer is formed by a spin coating process. The spin coating process has the advantages of mild process conditions, simplicity in operation and the like, and has remarkable convenient effects of reducing pollution, saving energy, improving cost performance and the like.

In this embodiment, the shielding layer 109 is used as a mask, and a wet etching process is used to laterally etch the sacrificial layer 101 exposed from the first groove 107 in the second region II, so as to form a second groove 108. The wet etching process is isotropic etching, has high etching rate, and is simple to operate and low in process cost.

In this embodiment, the sacrificial layer 101 is made of silicon germanium, and correspondingly, in the process of laterally removing the sacrificial layer 101 with the width of the exposed portion of the sidewall of the trench 106 by using a wet etching process, the wet etching solution used in the process includes an HCl solution.

It should be noted that in the step of forming the second groove 108, the lateral dimension of the second groove 108 is neither too large nor too small than the lateral dimension of the first groove 107. If the lateral dimension of the second groove 108 is too large than the lateral dimension of the first groove 107, and accordingly, the lateral dimension of the remaining sacrificial layer 101 in the second region II is too small, the lateral dimension of a channel formed by subsequently removing the sacrificial layer 101 in the second region II is too small, and the lateral dimension of a gate structure formed in the second device region II is too small, when the semiconductor structure operates, the control capability of the gate structure in the second device region II on the channel is poor, which results in poor performance of the second device region II. If the lateral dimension of the second groove 108 is too small than the lateral dimension of the first groove 107, the lateral dimension of the sacrificial layer 101 in the second device region II is smaller than the lateral dimension of the sacrificial layer 101 in the first device region I, the lateral dimension of the sacrificial layer 101 in the second device region II is too large, after the sacrificial layer 101 in the second device region II is subsequently removed, the lateral dimension of a channel formed is too large, the lateral dimension of a gate structure formed in the channel of the second device region II is too large, when the semiconductor structure operates, the length of the channel in the second device region II is small, which results in a large conduction current of a second transistor formed in the second device region, large power consumption, and a large leakage probability, and the formed semiconductor structure cannot meet process requirements. In this embodiment, in the step of forming the second groove 108, the lateral dimension of the second groove 108 is 1 nm to 5 nm larger than the lateral dimension of the first groove 107.

The method for forming the semiconductor structure further comprises the following steps: after the second groove 108 is formed, the shielding layer 109 is removed.

In this embodiment, the material of the shielding layer 109 is an organic material, and accordingly, an ashing process is used to remove the shielding layer 109.

Referring to fig. 9, a side wall material layer is formed in the first groove 107 and the second groove 108.

And subsequently, removing the dummy gate structure 103 to form a gate opening, removing the sacrificial layer 101 to form a channel, and forming a gate structure in the channel and the gate opening, wherein because the lateral dimension of the first groove 107 is smaller than the lateral dimension of the second groove 108, the lateral dimension of the sidewall material layer formed in the first groove 107 is smaller than the lateral dimension of the sidewall material layer formed in the second groove 108, and accordingly, the lateral dimension of the channel of the second device region II is smaller than the lateral dimension of the channel of the first device region I, so that the lateral dimension of the gate structure of the second device region II is smaller than the lateral dimension of the gate structure of the first device region I.

The side wall material layer is used for reducing the capacitance coupling effect between the source-drain doping layer and the grid structure which are formed subsequently, so that the parasitic capacitance is reduced, and the electrical performance of the transistor structure is improved.

In this embodiment, the sidewall material layer located in the first groove 107 is used as a first sidewall layer 110, and the sidewall material layer located in the second groove 108 is used as a second sidewall layer 111.

In this embodiment, the material of the side wall material layer is a low-K dielectric material. A low-k dielectric material (a low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less). The low-K dielectric material has excellent insulating property. The electrical coupling effect between the gate structure and the source-drain doping layer which are formed on the two sides of the side wall material layer subsequently can be reduced, so that the parasitic capacitance is reduced, and the electrical performance of the transistor structure is improved.

Specifically, the material of the side wall material layer includes: SiON, SiBCN, SiCN, carbon doped SiN, or oxygen doped SiN. In this embodiment, the material of the spacer material layer includes carbon-doped SiN or oxygen-doped SiN.

The forming method of the side wall material layer comprises the following steps: forming a side wall material film (not shown in the figure) which conformally covers the dummy gate structure 103, the trench 106, the first groove 107 and the second groove 108; and removing the side wall material film at the bottom of the groove 106 and on the side wall of the pseudo gate structure 103, and using the remaining side wall material film positioned in the first groove 107 and the second groove 108 as a side wall material layer.

In this embodiment, the sidewall material film is formed by an Atomic Layer Deposition (ALD) process. The atomic layer deposition process refers to a deposition process in which a vapor phase precursor is alternately pulsed into a reaction chamber to chemisorb and cause a surface reaction on a substrate to be deposited. Through an atomic layer deposition process, the side wall material film is formed on the surfaces of the pseudo gate structure 103, the groove 106, the first groove 107 and the second groove 108 in an atomic layer mode, so that the uniformity of the deposition rate, the thickness uniformity of the side wall material film and the structural uniformity in the side wall material film are improved, and the side wall material film has good covering capability; in addition, the process temperature of the atomic layer deposition process is generally lower, so that the Thermal Budget (Thermal Budget) is favorably reduced, and the probability of performance deviation of the semiconductor structure is reduced.

The method for forming the semiconductor structure further comprises the following steps: after the sidewall spacer material layer is formed, a source-drain doping layer 114 is formed in the trench 106.

When the semiconductor structure works, the source-drain doped layer 114 is used for providing stress for a channel and improving the migration rate of carriers in the channel.

When the region is used to form an NMOS, the source-drain doped layer 114 is used to act as the source and drain of the NMOS. When the semiconductor structure works, the source-drain doped layer 114 applies tensile stress to a channel below the gate structure, and the channel is stretched to improve the migration rate of electrons.

When the regions are used to form a PMOS, the source drain doped layer 114 is used to act as the source and drain for the PMOS. When the semiconductor structure works, the source-drain doped layer 114 applies compressive stress to a channel below the gate structure, and the compressed channel can improve the mobility of holes.

The method for forming the semiconductor structure further comprises the following steps: after the source-drain doping layer 114 is formed, an interlayer dielectric layer 115 is formed on the substrate 100 on the side portion of the dummy gate structure 103, and the top surface of the interlayer dielectric layer 115 is lower than or flush with the top surface of the dummy gate structure 103.

Interlevel dielectric layer 115 is used to electrically isolate adjacent devices.

In this embodiment, the interlayer dielectric layer 115 is made of an insulating material. Specifically, the material of the interlayer dielectric layer 115 includes silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the interlayer dielectric layer 115.

It should be noted that, in the process of forming the interlayer dielectric layer 115, the gate mask layer 114 is removed.

Referring to fig. 11, the dummy gate structure 103 is removed, and a gate opening 116 is formed.

The gate opening 116 provides a process space for the subsequent formation of a gate structure.

In this embodiment, the dummy gate structure 103 is removed by a wet etching process. The wet etching process has the advantages of high etching rate, simple operation and low process cost.

In this embodiment, the dummy gate structure 103 includes a dummy gate oxide 1031 and a dummy gate layer 1032. The material of the dummy gate oxide 1031 is silicon oxide, and the material of the dummy gate layer 1032 is polysilicon. Specifically, in the step of removing the dummy gate structure 103, the etching solution used includes ammonia water and a tetramethylammonium hydroxide solution.

In this embodiment, the gate opening 116 exposes the topmost sacrificial layer 101.

Referring to fig. 12, after the gate opening 116 is formed, the sacrificial layer 101 is removed to form a channel 117.

The channel 117 and the gate opening 116 together provide a process space for the subsequent formation of a gate structure.

In this embodiment, the sacrificial layer 101 is removed by a wet etching process. The wet etching process has the advantages of high etching rate, simple operation and low process cost.

Specifically, the material of the sacrificial layer 101 is silicon germanium. Correspondingly, in the process of removing the sacrificial layer 101 by using the wet etching process, the adopted etching solution is an HCl solution.

Specifically, in the first region I, the channel 117 at the bottom is surrounded by the fin 112, the first sidewall layer 110 and the channel layer 102, the channel layer 117 at the top is surrounded by the channel layer and the first sidewall layer 110 and is communicated with the gate opening 116, and the remaining channel layer 117 is surrounded by the channel layer 102 and the first sidewall layer 110.

In the second region II, the bottom-most channel 117 is surrounded by the fin 112, the second sidewall layer 111, and the channel layer 102, the top-most channel layer 117 is surrounded by the channel layer and the second sidewall layer 111 and communicates with the gate opening 116, and the rest of the channel layer 117 is surrounded by the channel layer 102 and the second sidewall layer 111.

In this embodiment, the topmost layer in the channel stack is the sacrificial layer 101. After the sacrificial layer 101 is correspondingly removed, the exposed lateral dimension of the top surface of the channel layer 102 at the topmost part in the second region II is equal to the exposed lateral dimension of the rest of the channel layers 102 in the second region II, and after a gate structure is subsequently formed, when a semiconductor structure works, the channel lengths of the channel layers 102 in the second region II are the same, which is beneficial to improving the uniformity of device performance.

In other embodiments, the topmost layer of the channel stack is a channel layer.

The lateral contact size of the gate structure and the topmost top surface of the channel layer is a first size, and the lateral contact size of the gate structure and the bottommost channel layer is a second size.

When the transverse dimension of the second side wall layer is equal to that of the grid side wall layer, the first dimension is equal to the second dimension, and after a grid structure is formed subsequently, when the semiconductor structure works, the channel lengths of all the channel layers in the second area II are the same, so that the uniformity of the performance of the device is improved.

When the transverse dimension of the second side wall layer is larger than that of the grid side wall layer, the first dimension is smaller than the second dimension, and after a grid structure is formed subsequently, when the semiconductor structure works, the channel length of the topmost channel layer in the second region is different from the channel length of the bottom, so that the starting voltage of the channel at the top is different from the starting voltage of the channel at the bottom.

When the transverse dimension of the second side wall layer is smaller than that of the grid side wall layer, the first dimension is larger than the second dimension, after the grid structure is formed subsequently, when the semiconductor structure works, the channel length of the topmost channel layer in the second region is different from the channel length of the bottom, and therefore the starting voltage of the channel at the top is different from the starting voltage of the channel at the bottom.

Referring to fig. 13, a gate structure 118 is formed in the channel 117 and the gate opening 116.

The gate structure 118 is used to control the opening and closing of the channel during operation of the semiconductor structure.

In this embodiment, the gate structure 118 is made of a magnesium-tungsten alloy. In other embodiments, the material of the gate structure may also be W, Al, Cu, Ag, Au, Pt, Ni, Ti, or the like.

The method for forming the semiconductor structure further comprises the following steps: a gate dielectric layer (not shown) is formed in the channel 117 and gate opening 116 before the gate structure 118 is formed.

The gate dielectric layer is used to achieve electrical isolation between the gate structure 118 and the fin 112. The gate dielectric layer is made of a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide.

In this embodiment, the gate dielectric layer is made of HfO₂. In other embodiments, the material of the gate dielectric layer may also be selected from ZrO₂、HfSiO、HfSiON、HfTaO、HfTiO, HfZrO or Al₂O₃One or more of them.

Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 13, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.

The semiconductor structure includes: a substrate 100, the substrate 100 comprising a first region I and a second region II; a source-drain doped layer 114, which is separated from the substrate 100; a plurality of channel layers 102, which are suspended on the substrate 100 at intervals in the normal direction of the surface of the substrate 100, and the plurality of channel layers 102 are located between the source-drain doping layers 114; a gate structure 118 surrounding the channel layer 102 and having a lateral direction parallel to the surface of the substrate 100 and perpendicular to an extending direction of the gate structure 118; the first sidewall layer 110 is positioned between the source-drain doping layer 114 and the gate structure 118 in the first region I; and a second sidewall layer 111 located between the source-drain doping layer 114 and the gate structure 118 in the second region II, wherein a lateral dimension of the second sidewall layer 111 is greater than a lateral dimension of the first sidewall layer 110.

In the semiconductor structure provided in the embodiment of the present invention, in the step of forming the semiconductor structure, the forming position of the gate structure 118 is occupied by a dummy gate structure, in the step of forming the dummy gate structure, generally, the lateral dimensions of the dummy gate structures in the first region I and the second region II are the same, the source-drain doping layers 114 are formed on both sides of the dummy gate structure, and the corresponding interval between the source-drain doping layers 114 on both sides of the dummy gate structure in the first region I is equal to the interval between the source-drain doping layers 114 in the second region II, that is, the lateral dimension of the channel layer 102 between the source-drain doping layers 114 in the first region I is equal to the lateral dimension between the channel layers 102 between the source-drain doping layers 114 in the second region II. A first sidewall layer 110 located between the source-drain doping layer 114 and the gate structure 118 in the first region I, a second sidewall layer 111 located between the source-drain doping layer 114 and the gate structure 118 in the second region II, the lateral dimension of the second sidewall layer 111 is greater than the lateral dimension of the first sidewall layer 110, the lateral dimension of the gate structure 118 in the second region II in contact with the channel layer 102 is small, the lateral dimension of the gate structure 118 in the first region I in contact with the channel layer 102 is relatively large, and accordingly, when the semiconductor structure is in operation, the lateral dimension of the channel in the first region I is larger than that of the channel in the second region II, the transistor formed in the first region I has small conduction current and small power consumption, and the probability of leakage current is small, the conduction current of the transistor formed in the second area II is large, and the response speed is high.

In this embodiment, both the first region I and the second region II may be used to form an nmos (negative Channel Metal Oxide semiconductor) or a pmos (positive Channel Metal Oxide semiconductor). In other embodiments, one of the first region and the second region may be an NMOS and one may be a PMOS.

In addition, the semiconductor structure further includes: a fin 112 located between the substrate 100 and the plurality of channel layers 102.

The sides of the fins 112 provide process space for the isolation layer 113.

The semiconductor structure further includes: an isolation layer 113 is located on the substrate 100 at a side of the fin 112, and the isolation layer 113 covers a portion of a sidewall of the fin 112.

The isolation layer 113 electrically isolates the gate structure 118 from the substrate 100. In addition, the isolation layer 113 is also used to electrically isolate the fins 112.

Channel layer 102 serves as a channel when the semiconductor structure is in operation.

In this embodiment, the material of the channel layer 102 is silicon. In other embodiments, the material of the channel layer may also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials.

It should be further noted that a plurality of channel layers 102 are suspended on the substrate 100 at intervals in the direction of the surface normal of the substrate 100.

In this embodiment, the gate structure 118 is on the isolation layer 113, and the gate structure 118 crosses over the fin 112 and covers a portion of the top wall and a portion of the sidewall of the fin 112.

It should be noted that the gate structure 118 can completely surround the bottom-most channel layer 102, and accordingly, the bottom-most channel layer 102 is easily depleted during operation of the semiconductor structure, which is beneficial to improving the electrical performance of the semiconductor structure.

When the region is used to form an NMOS, the source-drain doped layer 114 is used to act as the source and drain of the NMOS. When the semiconductor structure is in operation, the source-drain doped layer 114 applies a tensile stress to the channel under the gate structure 118, and the tensile stress can increase the migration rate of electrons.

When the regions are used to form a PMOS, the source drain doped layer 114 is used to act as the source and drain for the PMOS. During operation of the semiconductor structure, the source-drain doped layer 114 applies a compressive stress to the channel under the gate structure 118, and the compressive stress can improve the mobility of holes.

The method for forming the semiconductor structure further comprises the following steps: a gate dielectric layer is formed in the channel 117 and gate opening 116 before the gate structure 118 is formed.

In this embodiment, the gate dielectric layer is made of HfO₂. In other embodiments, the material of the gate dielectric layer may also be selected from ZrO₂HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al₂O₃One or more of them.

In the first region I, the first sidewall layer 110 is used to define the length of a channel region in the subsequent first region I, and the first sidewall layer 110 is also used to reduce the capacitive coupling effect between the source-drain doping layer 114 and the gate structure 118, thereby reducing the parasitic capacitance and improving the electrical performance of the transistor structure.

In this embodiment, the material of the first sidewall layer 110 is a low-K dielectric material. A low-k dielectric material (a low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less). The low-K dielectric material has excellent insulating property. The electrical coupling effect between the gate structure 118 and the source-drain doping layer on the two sides of the first sidewall layer 110 can be reduced, so that the parasitic capacitance is reduced, and the electrical performance of the transistor structure is improved.

Specifically, the material of the first sidewall layer 110 includes: SiON, SiBCN, SiCN, carbon doped SiN, or oxygen doped SiN. In this embodiment, the material of the first sidewall layer 110 includes carbon-doped SiN or oxygen-doped SiN.

In this embodiment, in the first region I, the first sidewall layer 110 is also located on the topmost channel layer 102.

In the second region II, the second sidewall layer 111 is used to define the length of a channel region in the subsequent second region II, and the second sidewall layer 111 is used to reduce the capacitive coupling effect between the source-drain doping layer 114 and the gate structure 118, thereby reducing the parasitic capacitance and improving the electrical performance of the transistor structure.

In this embodiment, the material of the second sidewall layer 111 is a low-K dielectric material. The low-k dielectric material has excellent insulating property. The electrical coupling effect between the gate structure 118 and the source-drain doping layer which are formed on two sides of the second side wall layer 111 subsequently can be reduced, so that the parasitic capacitance is reduced, and the electrical performance of the transistor structure is improved.

Specifically, the material of the second sidewall layer 111 includes: SiON, SiBCN, SiCN, carbon doped SiN, or oxygen doped SiN. In this embodiment, the material of the second sidewall layer 111 includes carbon-doped SiN or oxygen-doped SiN.

In the step of forming the second sidewall layer 111, the lateral dimension of the second sidewall layer 111 is neither too large nor too small than the lateral dimension of the first sidewall layer 110. If the lateral dimension of the second sidewall layer 111 is too large than the lateral dimension of the first sidewall layer 110, and correspondingly, the lateral dimension of the gate structure 118 between the second sidewall layers 111 in the second region II is too small, when the semiconductor structure operates, the gate structure 118 in the second device region II has poor control capability on a channel, resulting in poor performance of the second device region II. If the lateral dimension of the second sidewall layer 111 is too small than the lateral dimension of the first sidewall layer 110, the difference between the lateral dimension of the gate structure 118 between the second sidewall layers 111 in the second device region II and the lateral dimension of the gate structure 118 between the first sidewall layers 110 in the first device region I is relatively small, that is, the lateral dimension of the gate structure 118 between the second sidewall layers 111 in the second device region II is too large, when the semiconductor structure operates, the channel length in the second device region II is relatively small, which results in a relatively large conduction current of a second transistor formed in the second device region, a relatively large power consumption, and a relatively large leakage probability, and the formed semiconductor structure cannot meet the process requirements. In this embodiment, in the step of forming the second sidewall layer 111, the lateral dimension of the second sidewall layer 111 is 1 nm to 5 nm larger than the lateral dimension of the first sidewall layer 110.

Note that the second sidewall layers 111 are located on the topmost channel layer 102, between the channel layers 102, and between the channel layer 102 and the substrate 100.

Specifically, between channel layer 102 and substrate 100 is referred to as between channel layer 102 and fin 112.

In this embodiment, in the second region II, a lateral contact dimension between the gate structure 118 and the topmost surface of the channel layer 102 is a first dimension, a lateral contact dimension between the gate structure 118 and the bottommost channel layer 102 is a second dimension, and the first dimension and the second dimension are equal.

The exposed lateral dimension of the top surface of the topmost channel layer 102 in the second region II is equal to the exposed lateral dimension of any surface of the rest of the channel layers 102 in the second region II, the areas of the channel layers 102 covered by the gate structure in the second region II are the same, when the semiconductor structure works, the lengths of the channel layers 102 in the second region II are the same, and the conduction currents in the corresponding channels are the same, which is favorable for improving the uniformity of the device performance.

The semiconductor structure further includes: an interlayer dielectric layer 115 on the substrate 100 at the side of the gate structure 118, wherein a top surface of the interlayer dielectric layer 115 is flush with a top surface of the gate structure 118.

In addition, the semiconductor structure further includes: and a gate sidewall layer 105 between the gate structure 118 and the interlayer dielectric layer 115.

During the formation of the semiconductor structure, the gate sidewall layer 105 is used to define the formation location of the gate structure 118.

Note that the second sidewall layer 111 on the topmost channel layer 102 is formed between the topmost channel layer 102 and the gate sidewall layer 105.

Correspondingly, the embodiment of the invention also provides a second semiconductor structure. Referring to fig. 14, the same parts of this embodiment as those of the first embodiment are not described herein again, but the differences are:

the second sidewall layer 211 is disposed between the channel layers 202 and the substrate 200.

Specifically, what is referred to between the channel layer 202 and the substrate 200 is between the channel layer 202 and the fin 212.

The lateral contact dimension of the gate structure 218 with the top surface of the topmost channel layer 202 is a first dimension, and the lateral contact dimension of the gate structure 218 with the bottommost channel layer 202 is a second dimension.

When the lateral dimension of the second sidewall layer 211 is equal to the lateral dimension of the gate sidewall layer 205, and the first dimension is equal to the second dimension, after the gate structure 218 is formed subsequently, when the semiconductor structure operates, the channel lengths of the channel layers 202 in the second region II are the same, which is beneficial to improving the uniformity of the device performance.

When the lateral dimension of the second sidewall layer 211 is greater than the lateral dimension of the gate sidewall layer 205, and the first dimension is smaller than the second dimension, after the gate structure 218 is formed subsequently, when the semiconductor structure is in operation, the channel length of the topmost channel layer 202 in the second region is different from the channel length of the bottom, so that the turn-on voltage of the top channel is different from the turn-on voltage of the bottom channel.

When the lateral dimension of the second sidewall layer 211 is smaller than the lateral dimension of the gate sidewall layer 205, and the first dimension is larger than the second dimension, after the gate structure 218 is formed subsequently, when the semiconductor structure is in operation, the channel length of the topmost channel layer 202 in the second region is different from the channel length of the bottom, so that the turn-on voltage of the top channel is different from the turn-on voltage of the bottom channel.

It should be noted that, when the first size and the second size are different, the difference between the first size and the second size is equal to twice the difference between the lateral sizes of the second sidewall layer 211 and the first sidewall layer.

The semiconductor structure may be formed by the formation method of the foregoing embodiment, or may be formed by other formation methods. For a detailed description of the semiconductor structure of this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.

Claims

1. A method for forming a semiconductor structure, comprising:

providing a base including a first region and a second region, the base including a substrate, a channel stack separate from the substrate, and a dummy gate structure spanning the channel stack, the The dummy gate structure covers part of the top wall and part of the sidewall of the channel stack, the channel stack includes alternately stacked sacrificial layers and channel layers, and the bottommost part of the channel stack is the sacrificial layer;

etching the channel stacks on both sides of the dummy gate structure to form trenches in the channel stacks;

The sacrificial layer exposed by the trench is laterally etched with a direction parallel to the substrate surface and perpendicular to the extension direction of the dummy gate structure to form a first groove;

performing lateral etching on the sacrificial layer exposed by the first groove in the second region to form a second groove;

forming a layer of spacer material in the first groove and the second groove;

After the spacer material layer is formed, the dummy gate structure is removed to form a gate opening;

After the gate opening is formed, the sacrificial layer is removed to form a channel;

A gate structure is formed in the channel and gate opening.

2 . The method for forming a semiconductor structure according to claim 1 , wherein in the step of forming the second groove, the lateral dimension of the second groove is larger than the lateral dimension of the first groove. 3 . 1 nm to 5 nm.

3 . The method for forming a semiconductor structure according to claim 1 , wherein the first groove is formed by laterally etching the sacrificial layer exposed by the trench using a wet etching process. 4 .

4. The method for forming a semiconductor structure according to claim 1, wherein a wet etching process is used to laterally etch the sacrificial layer exposed by the first groove in the second region to form a second groove.

5. The method for forming a semiconductor structure according to claim 1, wherein the step of forming the second groove comprises:

forming a shielding layer covering the first groove of the first area and exposing the first groove of the second area;

Using the shielding layer as a mask, laterally etching the sacrificial layer exposed by the first groove in the second region to form the second groove;

The method for forming the semiconductor structure further includes: after forming the second groove, removing the shielding layer.

6. The method for forming a semiconductor structure according to claim 5, wherein the material of the shielding layer comprises one of BARC material, SOC material, ODL material, photoresist, DARC material, DUO material or APF material one or more.

7 . The method for forming a semiconductor structure according to claim 1 , wherein the material of the spacer material layer is a low-K dielectric material. 8 .

8 . The method for forming a semiconductor structure according to claim 7 , wherein the material of the spacer material layer comprises: SiON, SiBCN, SiCN, carbon-doped SiN or oxygen-doped SiN. 9 .

9 . The method for forming a semiconductor structure according to claim 1 , wherein the method for forming the spacer material layer comprises: forming a conformal covering of the dummy gate structure, trenches, first grooves and second grooves. 10 . the spacer material film of the groove; the spacer material film of the bottom and sidewalls of the trench and the sidewall of the dummy gate structure is removed, and the remaining sidewalls are located in the first groove and the second groove A wall material film serves as the side wall material layer.

10 . The method for forming a semiconductor structure according to claim 9 , wherein the spacer material film is formed by an atomic layer deposition process or a chemical vapor deposition process. 11 .

11 . The method for forming a semiconductor structure according to claim 1 , wherein the method for forming the semiconductor structure further comprises: forming a source-drain doped layer in the trench after forming the spacer material layer. 12 . .

12. The method for forming a semiconductor structure according to claim 1, wherein in the step of providing the substrate, the topmost layer of the channel stack is a sacrificial layer;

Alternatively, the topmost layer of the channel stack is a channel layer.

13. The method for forming a semiconductor structure according to claim 1, wherein in the step of providing a base, the base further comprises: a fin, protruding from the substrate, and the fin is located at the between the substrate and the channel stack;

an isolation layer, located on the substrate exposed by the fin, and the isolation layer covers part of the sidewall of the fin;

The dummy gate structure is located on the isolation layer, and the dummy gate structure spans the fin and covers part of the top wall and part of the sidewall of the fin.

14. A semiconductor structure, characterized in that it comprises:

a substrate including a first region and a second region;

a source-drain doped layer, which is separate from the substrate;

a plurality of channel layers, suspended on the substrate at intervals in the normal direction of the surface of the substrate, and a plurality of the channel layers are located between the source and drain doped layers;

a gate structure, surrounding the channel layer, with a lateral direction parallel to the surface of the substrate and perpendicular to the extension direction of the gate structure;

a first spacer layer, located between the source-drain doped layer in the first region and the gate structure;

A second spacer layer is located between the source-drain doped layer and the gate structure in the second region, and the lateral dimension of the second spacer layer is larger than the lateral dimension of the first spacer layer.

15 . The semiconductor structure of claim 14 , wherein a lateral dimension of the second spacer layer is larger than a lateral dimension of the first spacer layer by 1 nm to 5 nm. 16 .

16. The semiconductor structure of claim 14, wherein the material of the second spacer layer comprises: SiON, SiBCN, SiCN, carbon-doped SiN or oxygen-doped SiN.

17 . The semiconductor structure of claim 14 , wherein the material of the first spacer layer comprises: SiON, SiBCN, SiCN, carbon-doped SiN or oxygen-doped SiN. 18 .

18. The semiconductor structure of claim 14, wherein, in the second region, the second spacer layer is located on the topmost channel layer, between the channel layers and between the channel layer and the substrate.

19. The semiconductor structure of claim 14, wherein the second spacer layer is located between the channel layers and between the channel layer and the substrate.

20. The semiconductor structure of claim 14, wherein the semiconductor structure further comprises:

a fin between the substrate and the plurality of channel layers;

an isolation layer on the substrate on the side of the fin, and the isolation layer covers part of the sidewall of the fin;

The gate structure, on the isolation layer, spans the fin and covers part of the top wall and part of the sidewall of the fin.