CN113838757B - A method of forming a VDMOS device that is resistant to single particle effects and a VDMOS device - Google Patents

Abstract

The present invention proposes a method for forming a single particle effect-resistant VDMOS device and a VDMOS device, which include: providing a substrate with a first doping type; and extending outwardly a layer with the third doping type on one surface of the substrate A doped type epitaxial layer; forming a body region with a second doping type, a body contact region and a source region with the first doping type on the side of the epitaxial layer facing away from the substrate; A trench region is formed on the epitaxial layer by etching in a direction perpendicular to the contact surface between the substrate and the epitaxial layer, and the trench region passes through the body region and the body contact region; by having the second doped Heterotype polysilicon fills the trench area to form a first filling area. The first filling area is not electrically connected to the body area and the body contact area, and the trench area is filled with an insulating medium. the remaining area; the present invention can greatly improve the anti-single-particle burnout and anti-single-particle gate penetration capabilities of the VDMOS device.

Description

A method for forming a VDMOS device that is resistant to single particle effects and a VDMOS device

Technical field

The invention relates to the field of semiconductor radiation resistance reinforcement, and in particular to a method for forming a VDMOS device that is resistant to single event effects and a VDMOS device.

Background technique

After charged particles such as heavy ions and protons in the space environment are incident on the semiconductor devices in the spacecraft electronic system, they lose energy through the ionization process and generate a large number of electron-hole pairs along the tracks. Under the action of the internal electric field of the device, excess carriers are collected by sensitive nodes, which can induce a single event effect (SEE), thereby interfering with the working status of the aerospace electronic system, and in severe cases, leading to functional failure. Power VDMOS devices have many advantages such as high input impedance, strong driving capability, wide safe operating area, and simple control circuit. They are widely used in DC/DC converters of spacecraft power systems. However, traditional VDMOS devices have poor anti-single event effect effects. How to effectively suppress single event effects has become a major problem that current VDMOS devices need to solve urgently.

Contents of the invention

In view of the above existing problems in the prior art, the present invention proposes a method for forming an anti-single event effect VDMOS device and a VDMOS device, which mainly solves the problems of traditional VDMOS devices having poor anti-single event burnout and anti-single event gate penetration capabilities.

In order to achieve the above objects and other objects, the technical solutions adopted by the present invention are as follows.

A method for forming a VDMOS device that is resistant to single event effects, including:

providing a substrate having a first doping type;

Extending and growing an epitaxial layer having the first doping type on one surface of the substrate;

Forming a body region with a second doping type, a body contact region and a source region with the first doping type on a side of the epitaxial layer facing away from the substrate;

Etching on the epitaxial layer perpendicular to the direction of the contact surface between the substrate and the epitaxial layer forms a trench area, where the trench area passes through the body area and the body contact area;

The trench region is filled with polysilicon having the second doping type to form a first filling region. The first filling region is not electrically connected to the body region and the body contact region and is insulated through The dielectric fills the remaining area of the trench area.

Optionally, forming a body region with a second doping type, a body contact region and a source region with the first doping type on a side of the epitaxial layer facing away from the substrate, including:

Doping regions including the body region and the body contact region are respectively formed on opposite sides of the epitaxial layer;

The source region is formed based on the body region on the corresponding side of the epitaxial layer.

Optionally, a gate oxide layer is generated based on the source region, body region and epitaxial layer;

generating a polysilicon gate based on the gate oxide layer;

Generate an insulating dielectric layer based on the trench area, body contact area, source area and polysilicon gate;

Etching to form openings on the basis of the insulating dielectric layer to expose the source area, body contact area and trench area, and growing a metal contact layer on the basis of the openings as the source electrode;

A metal layer is grown on the side of the substrate away from the epitaxial layer as a drain electrode.

Optionally, the epitaxial layer includes multi-layer doped regions with different doping concentrations in sequence upward from the substrate.

Optionally, the first doping type is N-type doping, and the second doping type is P-type doping; or, the first doping type is P-type doping, and the second doping type is P-type doping. The impurity type is N-type doping.

Optionally, the body region is located below the body contact region on the corresponding side and connected to the body contact region on the corresponding side, and the source region is respectively connected to the body region and the body contact region on the corresponding side. .

Optionally, the first filling area is located below the body area.

Optionally, the body region and the body contact region are formed by selective doping and annealing.

Optionally, the insulating dielectric layer includes silicon oxide or silicon nitride.

A VDMOS device that is resistant to single event effects, including:

a substrate having a first doping type;

An epitaxial layer having the first doping type is located on one surface of the substrate;

a body region having a second doping type, a body contact region and a source region having the first doping type located on a side of the epitaxial layer facing away from the substrate;

A trench area located on the epitaxial layer perpendicular to the direction of the contact surface between the substrate and the epitaxial layer, the trench area passing through the body area and the body contact area;

A first filling region with the second doping type is located in the trench region, and the first filling region is not electrically connected to the body region and the body contact region;

An insulating dielectric filling region located in the trench region and used to cooperate with the first filling region to completely fill the trench region.

As mentioned above, the present invention proposes a method for forming a VDMOS device that is resistant to single event effects and a VDMOS device, which has the following beneficial effects.

By utilizing the different doping type of the first filling region in the trench region and the doping type of the epitaxial layer, a PN junction is formed between the first filling region and the epitaxial layer, which can effectively suppress the occurrence of single particle burnout and single particle gate penetration effects.

Description of drawings

FIG. 1 is a schematic diagram of forming an N-type epitaxial layer on an N-type substrate in an embodiment of the present invention.

FIG. 2 is a schematic diagram of forming a P-type body region and a P-type body contact region through selective doping and annealing in an embodiment of the present invention.

FIG. 3 is a schematic diagram of a trench region formed by selective etching in an embodiment of the present invention.

FIG. 4 is a schematic diagram of filling a trench area with P-type polysilicon in an embodiment of the present invention.

FIG. 5 is a schematic diagram of depositing oxide to fill the trench area and smooth the surface in an embodiment of the present invention.

FIG. 6 is a schematic diagram of forming a gate oxide layer, a polysilicon gate, a source region and an insulating dielectric layer in an embodiment of the present invention.

Figure 7 is a schematic structural diagram of an N-channel VDMOS device that is resistant to single event effects after electrode contact is formed in an embodiment of the present invention;

FIG. 8 is a graph illustrating the change of VDMOS drain current with time after heavy ions with different LCD values are vertically incident from the channel region in an embodiment of the present invention.

Figure 9 is a graph showing changes in electric field intensity inside the VDMOS gate oxide layer after heavy ions with LCD=1pC/μm are vertically incident from the center of the neck region for 50ps in an embodiment of the present invention.

Detailed ways

The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, as long as there is no conflict, the following embodiments and the features in the embodiments can be combined with each other.

It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the drawings only show the components related to the present invention and do not follow the number, shape and number of components during actual implementation. Dimension drawing, in actual implementation, the type, quantity and proportion of each component can be arbitrarily changed, and the component layout type may also be more complex.

The inventor's research found that since the source region, body region and epitaxial layer of VDMOS form a parasitic bipolar transistor structure, after high-energy charged particles are incident into the device, a large number of electron-hole pairs are generated along the track, and under the influence of the drain-source electric field Under the action, a large number of excess carriers flow through the body region to the source, thereby generating a certain voltage drop in the body region. When the voltage drop in the body region is greater than the EB junction turn-on voltage of the parasitic bipolar transistor, the transistor enters the forward amplification state, and carriers in the source region are continuously injected into the body region and swept toward the drift region. If the source-drain voltage of the VDMOS is greater than the BVCEO of the parasitic bipolar transistor, the current flowing through the transistor will further increase under the action of the forward feedback mechanism. Due to the current concentration effect at local points in the VDMOS device, the lattice temperature rises sharply, leading to the Single Event Burnout (SEB) effect. In addition, when heavy ions are incident from the VDMOS neck region, a large number of carriers generated in the drift region gather toward the gate oxide layer/silicon interface under the action of the drain-source electric field, thereby generating an additional electric field in the gate oxide layer. When the electric field intensity in the gate oxide layer is higher than its intrinsic breakdown field intensity, the gate oxide layer is partially broken down, thereby inducing the Single Event Gate Rapture (SEGR) effect, causing the gate leakage current to increase, and even Loss of gate control capability. Single event burnout and single event gate penetration are the two most important types of single event effects in VDMOS devices. Unlike recoverable single event effects such as Single Event Transient (SET) and Single Event Upset (SEU), both will cause irreversible material damage inside the device. Therefore, VDMOS devices for aerospace applications Reinforcement measures against single-event burning and single-event gate penetration must be taken.

Please refer to Figure 1. The present invention provides a method for forming a VDMOS device that is resistant to single event effects, including the following steps: providing a substrate with a first doping type; extending outwardly on one surface of the substrate to grow An epitaxial layer having the first doping type; forming a body region, a body contact region having a second doping type and a source having the first doping type on a side of the epitaxial layer facing away from the substrate area; etching on the epitaxial layer perpendicular to the direction of the contact surface between the substrate and the epitaxial layer forms a trench area, which passes through the body area and the body contact area; by having the The second doping type polysilicon fills the trench region to form a first filling region. The first filling region is not electrically connected to the body region and the body contact region, and is filled with an insulating medium. the remaining area of the trench area.

In one embodiment, doped regions including the body region and the body contact region are respectively formed on opposite sides of the epitaxial layer; the doped regions are formed on the basis of the body region on the corresponding side of the epitaxial layer. Describe the source area.

In an embodiment, further, a gate oxide layer can be generated based on the source region, body region and epitaxial layer; a polysilicon gate can be generated based on the gate oxide layer; An insulating dielectric layer is generated on the basis of the contact area, the source area and the polysilicon gate; on the basis of the insulating dielectric layer, a window is formed by etching to expose the source area, the body contact area and the trench area, and on the basis of the window A metal contact layer is grown on the substrate as a source electrode; a metal layer is grown on a side of the substrate facing away from the epitaxial layer as a drain electrode.

In one embodiment, the epitaxial layer sequentially includes multi-layer doped regions with different doping concentrations from the substrate upward. Specifically, on the premise of ensuring that the breakdown voltage of VDMOS does not significantly degrade, the doping concentration of some doped regions can be increased, or the doping concentration of all doped regions can be increased to reduce the on-resistance of the VDMOS device. According to the load According to carrier recombination theory, the non-equilibrium carrier lifetime in a semiconductor is inversely proportional to the majority carrier concentration. Therefore, after high-energy charged particles are incident on VDMOS, the excess carriers generated along the track recombine rapidly, thereby reducing the number of excess carriers flowing to the body region and neck region, and ultimately suppressing the single-particle burnout and single-particle gate penetration effects. produce.

In one embodiment, the body region is located below the body contact region on the corresponding side and connected to the body contact region on the corresponding side, and the source region is in contact with the body region and the body on the corresponding side respectively. area connection.

In one embodiment, the first doping type is N-type doping, and the second doping type is P-type doping; or, the first doping type is P-type doping, and the second doping type is P-type doping. The second doping type is N-type doping.

In one embodiment, the insulating dielectric layer includes silicon oxide or silicon nitride.

The following takes the formation method of N-channel VDMOS devices as an example. The specific implementation process is:

Step 1. Please refer to Figure 1. An N-type epitaxial layer 2 with a thickness of 18 μm is grown on a heavily doped N-type silicon substrate 1 (resistivity 0.002Ω·cm). The N-type epitaxial layer 2 is grown from the surface of the silicon substrate 1 to different thickness intervals. The doping concentration of layer 2 is 2×10 ¹⁶ cm ^-3 (0μm-6.5μm), 5×10 ¹⁵ cm ^-3 (6.5μm-8μm), 1×10 ¹⁵ cm ^-3 (8μm-9μm), 7.4 ×10 ¹⁴ cm ^-3 (9μm-18μm);

Step 2: Refer to Figure 2, forming P-type body region 3 and P-type body contact region 4 through selective boron ion implantation and annealing;

Step 3. Please refer to Figure 3. Selectively etch the device structure obtained in Step 2 to form a trench region 5 that passes through the P-type body region 3 and the P-type body contact region 4 and reaches the N-type epitaxial layer. The trench Depth 11μm, width 3μm;

Step 4. Please refer to Figure 4. Use P-type polysilicon to fill the trench area 5 with a filling depth of 6 μm and a doping concentration of 1×10 ¹⁶ cm ^-3 to form the first filling area 6;

Step 5. Refer to Figure 5. An insulating medium such as deposited oxide can be used to fill the remaining portion of the trench to form an insulating dielectric filling area 7, and the device surface can be smoothed through chemical mechanical planarization;

Step 6. Referring to Figure 6, the gate oxide layer 8, the polysilicon gate 9, the N-type source region 10 and the oxide insulating dielectric layer 11 are formed through the traditional VDMOS manufacturing process;

Step 7. Please refer to Figure 7. Selectively etch the oxide insulating dielectric layer 11 to form a source metal contact window, and through a metallization process, form a source metal contact 12 on the side of the substrate 1 away from the epitaxial layer. The metallization process forms the drain metal contact 13, thereby preparing an N-channel VDMOS structure with a polysilicon trench filling region.

Figure 8 shows the drain end of a reinforced VDMOS device using the above anti-single event effect device structure and preparation method and an unreinforced conventional VDMOS device after heavy ions of different linear energy deposition (Linear Charge Deposition, LCD) are vertically incident from the channel region. The change of current with time. It can be seen from the figure that for unreinforced VDMOS devices, heavy ions with an LCD of 0.3pC/μm can induce single-particle burnout, while the reinforced VDMOS device does not burn after heavy ions with an LCD of 1pC/μm are incident. In summary, the reinforced structure and preparation method of the present invention can significantly improve the single particle burnout threshold of VDMOS.

Figure 9 shows the electric field inside the gate oxide layer after heavy ions with LCD=1pC/μm are vertically incident from the center of the neck region for 50ps for the reinforced VDMOS device and the unreinforced conventional VDMOS device using the above-mentioned anti-single event effect device structure and preparation method. Intensity contrast. It can be seen from the figure that the electric field intensity inside the VDMOS gate oxide layer after reinforcement is significantly lower than that of the unreinforced device, thereby inhibiting local breakdown of the oxide layer. In summary, the reinforced structure and preparation method of the present invention can significantly improve the anti-single particle gate penetration capability of VDMOS.

In one embodiment, the present invention also provides an anti-single event effect VDMOS device, which is characterized in that it includes: a substrate with a first doping type; and the first doping type is located on one surface of the substrate. A doped type epitaxial layer; a body region with a second doping type, a body contact region and a source region with the first doping type located on a side of the epitaxial layer facing away from the substrate; located on the A trench area on the epitaxial layer perpendicular to the direction of the contact surface between the substrate and the epitaxial layer, the trench area passing through the body area and the body contact area; located in the trench area, there is the A first filling region of a second doping type, the first filling region is located below the body region and the first filling region is not electrically connected to the body region and the body contact region; located in the trench An insulating dielectric filling area in the trench area is used to cooperate with the first filling area to completely fill the trench area.

In one embodiment, the first filling area is not connected to the body area and the body contact area. The body area is located below the body contact area and connected to the body contact area; the source area is located between the body area and the body contact area, and connects the body area and the body contact area respectively. A gate oxide layer is provided on the basis of the source area, body area, and epitaxial layer. A polysilicon gate is provided on the gate oxide layer. The gate oxide layer and the polysilicon gate are covered by an insulating dielectric layer; the insulating dielectric layer is provided with a window in the source area. A metal contact layer is provided at the window opening position to connect to the source region and serves as the source electrode; a metal contact layer is provided on the side of the substrate away from the epitaxial layer as the drain electrode.

In summary, the present invention proposes a method for forming a VDMOS device that is resistant to single event effects and a VDMOS device. A PN junction is formed between the polysilicon trench filling region of the second impurity doping type and the silicon epitaxial layer of the first impurity doping type. . When a voltage is applied between the drain and the source to reverse bias the PN junction, the polysilicon trench filling region obtains potential from the reverse biased PN junction, thus contributing to the depletion of the first impurity doped type silicon epitaxial layer and causing drift The area can withstand greater applied voltage. Therefore, on the premise of ensuring that the VDMOS breakdown voltage does not significantly degrade, the doping concentration of the first impurity doping type silicon epitaxial layer can be increased or partially increased. According to the carrier recombination theory, the non-equilibrium carrier lifetime in a semiconductor is inversely proportional to the majority carrier concentration. Therefore, after high-energy charged particles are incident on VDMOS, the excess carriers generated along the track recombine rapidly, thereby reducing the number of excess carriers flowing to the body region and neck region, and ultimately suppressing the single-particle burnout and single-particle gate penetration effects. Produced; placing the process steps of the polysilicon trench filling area after the epitaxial growth and high-temperature advancement of the body region weakens the out-diffusion of impurities in the polysilicon, so the reinforcement effect can be achieved without changing the thermal budget of the entire process; the epitaxial layer is doped The increase in impurity concentration also reduces the on-resistance of VDMOS; the polysilicon trench filling area is far away from the current transmission path of VDMOS, does not increase the cell pitch, and avoids the electric field concentration at the edge of the body area. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (6)

1. A method for forming a single event effect resistant VDMOS device, which is characterized by including: providing a substrate having a first doping type; An epitaxial layer with the first doping type is grown outwardly on one surface of the substrate, and the epitaxial layer sequentially includes multi-layer doped regions with different doping concentrations upward from the substrate. , wherein the growth thickness of the epitaxial layer is 18 μm; the doping concentrations of the doped regions in different layers from the substrate surface upward are 2×10 ¹⁶ cm ^-3 (0 μm-6.5 μm), 5×10 ¹⁵ cm ^-3 (6.5 μm-8 μm), 1×10 ¹⁵ cm ^-3 (8 μm-9 μm), 7.4×10 ¹⁴ cm ^-3 (9 μm-18 μm); Forming a body region with a second doping type, a body contact region and a source region with the first doping type on the side of the epitaxial layer facing away from the substrate, including: on two opposite sides of the epitaxial layer Doping regions including the body region and the body contact region are respectively formed on each side; the source region is formed based on the body region on the corresponding side of the epitaxial layer; A trench region is formed on the epitaxial layer by etching perpendicular to the direction of the contact surface between the substrate and the epitaxial layer, and the trench region passes through the body region and the body contact region; wherein, the body contact region and the body region is formed by selective boron ion implantation and annealing; the groove depth of the trench region is 11 μm and the width is 3 μm; The trench region is filled with polysilicon having the second doping type to form a first filling region, wherein the depth of the first filling region is 6 μm and the doping concentration is 1×10 ¹⁶ cm ^-3 ; The first filling region is not electrically connected to the body region and the body contact region, and the remaining area of the trench region is filled with an insulating medium, and the first filling region is located below the body region; in A gate oxide layer is generated based on the source region, body region and epitaxial layer; a polysilicon gate is generated based on the gate oxide layer; a polysilicon gate is generated based on the trench region, body contact region, source region and polysilicon gate Generate an insulating dielectric layer; etching on the basis of the insulating dielectric layer to form openings exposing the source region, the body contact region and the trench region, and growing a metal contact layer as the source on the basis of the openings; A metal layer is grown on the side of the substrate away from the epitaxial layer as a drain electrode. 2. The method for forming a single event effect-resistant VDMOS device according to claim 1, wherein the first doping type is N-type doping, and the second doping type is P-type doping; or , the first doping type is P-type doping, and the second doping type is N-type doping. 3. The method for forming a single event effect-resistant VDMOS device according to claim 1, wherein the body region is located below the body contact region on the corresponding side and connected to the body contact region on the corresponding side, so The source area is respectively connected to the body area and the body contact area on the corresponding side. 4. The method for forming a single event effect resistant VDMOS device according to claim 1, wherein the body region and the body contact region are formed by selective doping and annealing. 5. The method for forming a single event effect-resistant VDMOS device according to claim 1, wherein the insulating medium includes silicon oxide or silicon nitride. 6. An anti-single event effect VDMOS device obtained by the formation method according to any one of claims 1 to 5, characterized in that it includes: a substrate having a first doping type; There is an epitaxial layer of the first doping type located on one surface of the substrate, and the epitaxial layer sequentially includes multi-layer doped regions with different doping concentrations upward from the substrate; a body region having a second doping type, a body contact region and a source region having the first doping type located on a side of the epitaxial layer facing away from the substrate; A trench area located on the epitaxial layer perpendicular to the direction of the contact surface between the substrate and the epitaxial layer, the trench area passing through the body area and the body contact area; A first filling region with the second doping type is located in the trench region, and the first filling region is not electrically connected to the body region and the body contact region; An insulating dielectric filling region located in the trench region and used to cooperate with the first filling region to completely fill the trench region.