CN113821470B

CN113821470B - Bus device, embedded system and system on chip

Info

Publication number: CN113821470B
Application number: CN202010568121.1A
Authority: CN
Inventors: 高海飞
Original assignee: Hangzhou C Sky Microsystems Co Ltd
Current assignee: Hangzhou C Sky Microsystems Co Ltd
Priority date: 2020-06-19
Filing date: 2020-06-19
Publication date: 2024-09-06
Anticipated expiration: 2040-06-19
Also published as: CN113821470A

Abstract

The embodiment of the disclosure provides a bus device, an embedded system and a system on a chip. The bus device includes: a write command buffer for buffering a plurality of write addresses transmitted by the master device and transmitting consecutive write addresses of the plurality of write addresses to the address redirection unit for the same slave device according to the notification of the arbitration unit; an address redirection unit for redirecting the write address to the same slave device to an address space of the same slave device; and the arbitration unit is used for notifying the write command buffer to transmit the write address after the write address of the same slave device after the write transaction of the write address of the same slave device is completed. The bus device provided by the embodiment of the disclosure executes the continuous write transaction of the write address of the same slave device in a plurality of write addresses, and after the execution is finished, the write transaction of the write address after the execution is executed, so that the bus interlocking problem does not occur.

Description

Bus device, embedded system and system on chip

Technical Field

The present disclosure relates to the field of chips, and in particular, to a bus device, an embedded system, and a system on a chip.

Background

With the continuous expansion of system on chip (SoC), the bus structure and hierarchy become extremely complex, and the cascade of bus devices inevitably occurs in a large-scale system on chip design. Bus interlock problems occur when design considerations are poor or bus devices do not match the behavior of the devices. Referring to fig. 1, a master device 1 sends a read-write request to a slave device 1 through a path 1 of a bus device 1, forwards the read-write request to a bus device 0 through a path 2, and then loops back to the bus device 1 through a path 3, and at this time, the path 2 and the path 3 form a loop, so that the system cannot complete the read-write request of the master device 1 to the slave device 1. Similarly, a similar problem occurs when the master device 0 issues a read/write request to the slave device 0 via the path of the bus device 0. So that the whole system cannot continue to work normally.

Typically, the bus protocol defines only basic read-write transfer behavior, and in particular use, a hardware system engineer needs to ensure that bus interlock problems do not occur between bus devices. While the typical interlock problem shown in fig. 1 is relatively easy to find and correct at the beginning of the design, as the bus device architecture becomes more complex, it becomes more difficult to find the bus interlock problem, and it is often the case that there is a small probability of an interlock problem in the bus device architecture based on very random stress testing at a very late stage of the large-scale stability test of the project.

Disclosure of Invention

The present disclosure proposes a bus device, and an embedded system and a system on chip including the bus device, capable of solving an interlocking problem in a cascade structure of the bus device.

According to a first aspect, according to an embodiment of the present disclosure, there is provided a bus device comprising:

a write command buffer for buffering a plurality of write addresses transmitted by the master device and transmitting consecutive write addresses of the plurality of write addresses to the address redirection unit for the same slave device according to the notification of the arbitration unit;

An address redirection unit for redirecting the write address to the same slave device to an address space of the same slave device;

and the arbitration unit is used for notifying the write command buffer to transmit the write address after the write address of the same slave device after the write transaction of the write address of the same slave device is completed.

Optionally, the arbitration unit controls the duration of the active level of any one of the write address active signal and the write address ready signal between the master device and the same slave device to be at least the number of consecutive write addresses to the same slave device.

Optionally, the controlling the duration of the active level of any one of the write address active signal and the write address ready signal between the master device and the same slave device is at least the number of write addresses to the same slave device includes:

maintaining a write address valid signal between the master device and the same slave device at an active level;

The active level duration of the write address ready signal between the master device and the same slave device is made equal to the number of consecutive write addresses to the same slave device.

Enabling the duration period of the valid level of the write address valid signal between the master device and the same slave device to be equal to the number of the continuous write addresses to the same slave device;

The write address ready signal between the master and the same slave is maintained at an active level.

Optionally, the controlling the duration of the active level of any one of the write address active signal and the write address ready signal between the master device and the same slave device is at least the number of consecutive write addresses to the same slave device includes:

and enabling the write address valid signal and the write address ready signal between the master device and the same slave device to change simultaneously, wherein the valid level duration period of the write address valid signal and the write address ready signal is equal to the number of the continuous write addresses to the same slave device.

Optionally, the arbitration unit controls the write data valid signal and the write data ready signal between the master device and the same slave device to be valid levels after the duration of the valid level of at least one of the write address valid signal and the write address ready signal between the master device and the same slave device is at least the number of consecutive write addresses to the same slave device.

Optionally, the completion of the execution of the write transaction to the write address of the same slave device is determined by the arbitration unit through the received write reply signal from the same slave device.

Optionally, the arbitration unit further controls at least one of a write data valid signal and a write data ready signal between the master device and the same slave device to change from a valid level to an invalid level after the execution of the write transaction to the write address of the same slave device is completed.

Optionally, the bus device is an AXI bus device.

Optionally, the number of write addresses to the same slave device is less than or equal to the maximum number of in-transit transactions of the bus device.

In a second aspect, an embodiment of the present disclosure provides an embedded system, including: a bus device as claimed in any preceding claim; a plurality of said master devices connected to said bus device; and a plurality of slave devices connected to the bus device.

Optionally, the master device is a processing unit, and the slave device is a memory controller or a random access memory.

Optionally, the processing units are embedded processors and acceleration units, the slave devices are a storage controller and a random access memory, the embedded processors control the storage controller to read data from an external memory and store the data into the random access memory, and the acceleration units read the data from the random access memory to calculate.

In a third aspect, embodiments of the present disclosure provide a system on a chip, comprising: a bus device as claimed in any preceding claim; a plurality of said master devices connected to said bus device; and a plurality of slave devices connected to the bus device.

In the prior art, after the bus device receives the write addresses of the write transactions from the master device to the plurality of slave devices, the write transactions of at least two slave devices may be performed simultaneously. Thus, due to transmission delay and the like, the write transactions to the at least two slave devices may cause bus interlocking, in the embodiment of the present disclosure, if the bus device receives multiple write addresses sent by the master device and performing write transactions to the at least two slave devices, only consecutive write addresses to the same slave device in the multiple write addresses are sent to the address redirection unit, so that the write transactions to the write addresses of the same slave device are performed first, and after the execution is completed, the write transactions to the write address after the execution are performed. In this way, the write transactions executed in the same batch are all directed to the write address of the same slave device, and thus, no bus interlock problem occurs.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent by describing embodiments thereof with reference to the following drawings in which:

FIG. 1 is intended to illustrate a typical bus interlock problem;

FIG. 2 is a schematic structural diagram of a write transaction;

FIG. 3 is a signal timing diagram of a write transaction;

FIG. 4 is a dependency of handshake signals in a write transaction;

FIG. 5 is an embedded system of a cascade of secondary bus devices;

FIG. 6 is a signal timing diagram of the embedded system shown in FIG. 5;

FIG. 7 is a schematic diagram of an exemplary bus device;

fig. 8 is a signal timing diagram of a solution according to an embodiment of the present disclosure.

Detailed Description

The present disclosure is described below based on embodiments, but the present disclosure is not limited to only these embodiments. In the following detailed description of the present disclosure, certain specific details are set forth in detail. The present disclosure may be fully understood by one skilled in the art without a description of these details. Well-known methods, procedures, and flows have not been described in detail so as not to obscure the nature of the disclosure. The figures are not necessarily drawn to scale.

The following terms are used herein.

SoC, system on Chip, chip scheme for implementing the entire application System on a monolithic Chip.

AXI, advanced Extensible Interface, advanced scalable bus devices, currently the dominant large SoC on-chip bus devices.

Lock, AXI bus equipment interlock, and the bus equipment can not continue normal work.

Outlining: on-the-way transmission, the Master can initiate the next read-write transaction on the premise that the last read-write transaction is not completed, so that the transmission efficiency is effectively improved;

Maximum number of transactions in transit: referring to the maximum number of in-transit read or write transactions that can be supported by the characteristics of the bus device outstanding, the number of read or write transactions that are currently outstanding by the bus device is less than or equal to the maximum number of in-transit transactions. When (when)

DDRC, double Data Rate Controllor, double rate memory controller, soC off-chip memory controller.

SRAM, static Random Access Memory, static random access memory, soC chip internal memory unit.

Before describing the various embodiments of the present disclosure, it is first necessary to first understand various aspects of the bus. The bus currently in wide use is the AIX bus. The AXI bus is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0.0 and above protocols proposed by ARM corporation, which is an on-chip bus that is directed to high performance, high bandwidth, low latency. The AIX bus separates address/control and data phase, supports misaligned data transfer, and supports burst transfer and out-of-order transfer, thus meeting the requirements of ultra-high performance and complex system-on-chip design.

Fig. 2 is a schematic structural diagram of the principle of a write transaction. A write transaction includes a complete set of operations. As shown in the figure, the initiator of the write transaction is the master device 20 and the receiver is the slave device 30.

The write transaction includes data transfers for 3 channels, a write address channel (WRITE ADDRESS CHANNEL) 201, a write data channel (WRITE DATA CHANNEL) 202, and a write reply channel (write response channel) 203, respectively. The write address channel 201 is used to transmit write addresses and control information describing the nature of the data being transmitted. The write data path 202 is used to transmit write data. The write reply channel 203 is used to transmit response information. The arrows indicate the channel directions, as shown in the figure, each channel being unidirectional.

Each channel includes a two-way VALID, READY handshake mechanism. The VALID signal is used by the master device 20 to indicate when the write address and control information in the channel are VALID. The READY signal is used by the slave device 30 to indicate when data can be received. Specifically, the write address signals transmitted by channel 201 include a write address valid signal (AWVALID) and a write address ready signal (AWREADY), which when the AWVALID signal is 1, indicates that the write address and control information are valid, and when the AWVALID signal is 0, indicates that the write address and control information are invalid, which signals are controlled by master device 20, and when the AWREADY signal is 1, indicates that the device is ready, and when the signal is 0, indicates that the device is not ready, which signals are controlled by slave device 30; the write data signals transmitted by channel 202 include a write data valid signal (WVALID) and a write data ready signal (WREADY), which when the WVALID signal is 1 indicates that the write data is valid and when it is 0 indicates that the write data is invalid, the signals being controlled by master device 20, when the WREADY signal is 1 indicates that the device is ready and when it is 0 indicates that the device is not ready, the signals being controlled by slave device 30; the write response signals transmitted by channel 203 include a write response valid signal (BVALID) signal and a write response ready signal (break) that indicate that the write response is valid when BVALID signal is 1 and that the write response is invalid when 0, and that indicate that the device is ready when break signal is 1 and that the device is not ready when 0, and that are controlled by slave device 20.

It should be understood that there is no sequence requirement for writing data between the write address channel 201 and the write data channel 202, for example, the write address may be written to the write address channel 201 first, then the write data may be written to the write data channel 202, or the write data may be written to the write data channel 202 first, and then the write address may be written to the address channel 201. But the write address signals and write data signals need to be able to correspond. For example, the AXI3.0 specification specifies that the write address signal and the write data signal each have a tag that can correspond to the write address signal and the write data signal. However, in the AXI4.0 specification, the tags in the write data signals are omitted, and therefore the order of the write data signals must be identical to the order of the write address signals.

FIG. 3 is a signal timing diagram of a write transaction. Wherein CLK is a clock signal, AWADDR transmits address information, WDATA transmits data information, WLAST is a data end signal, which is sent in the write data channel, indicating that the write data information has been sent, BRESP transmits response information, and the remaining signals are described above, and will not be described again here.

At the beginning of a write transaction, master 20 sends signal AWADDR to write address channel 201 to carry the write address while setting AWVALID high, slave 30 sets AWREADY high when ready, and handshakes AWVALID and AWREADY succeed at time T2 (clock signal rising edge) to begin transfer of the write address within the write address channel. The master device 20 sends a signal WDATA carrying write data D (A0), D (A1), D (A2) and D (A3) to the write data channel while setting WVALID high accordingly according to the data, the slave device 30 sets WREADY high accordingly, handshakes are successful at times T4, T6, T8 and T9, and transmission of the write data is performed. When the write data ends, the master device 20 sets WLAST to high level, and the write data transmission ends at time T9. Subsequently, the master device 20 sets the signal BVALID to a high level, and transmits response information OKAY to the write reply channel 203. At time T10, BVALID and break are both high, and response information OKAY is transmitted.

Fig. 4 is a dependency of handshake signals in a write transaction. The signal pointed by the single arrow can be enabled after the signal pointed by the single arrow is not enabled or enabled, namely the single arrow indicates that no dependency exists between the two signals; the signal pointed by the double arrow must be enabled after all the signals pointed to it are enabled, i.e. the double arrow indicates that there is a dependency between the two signals. It follows from the figure that in a write transaction, only BVALID signals need to be enabled after signals AWVALID, AWREADY, WVALID and WREADY are all enabled, and there is no dependency between the remaining signals.

With knowledge of various aspects of the bus, the bus interlock problem and corresponding solutions to be addressed by embodiments of the present disclosure are described below by way of example in relation to an embedded system of a cascade of two-level bus devices as shown in fig. 5.

As shown in the figure, in order to meet the requirements of the system in terms of speed, volume and power consumption, the embedded system generally does not use a storage medium such as a magnetic disk, which has a large capacity and a slow speed, to store data and program instructions, but mostly uses a random access Memory 508 or a Flash Memory (not shown in the figure), and may connect an external Memory 602 through a Memory controller 507 to obtain more storage capacity. The data and program instructions stored in the external memory 602 may be transferred to the random access memory 508 or the flash memory at any time via the memory controller 507. The ram 508 may be a static ram or a dynamic ram, and the memory controller 507 may be a static ram controller or a double rate memory controller, for example, if the memory controller 507 is a static ram controller, the external memory 602 is a static ram accordingly.

Second, in the system, a/D (analog/digital) interfaces 503, 603 are required for measurement and control, which is rarely used in general-purpose computers. The a/D interfaces 503, 603 mainly perform conversion of analog signals to digital signals and conversion of digital signals to analog signals required in the test. The embedded system often needs testing when applied to industrial production. Because the single-chip microcomputer generates digital signals, the digital signals need to be converted into analog signals for testing, and therefore, unlike a general-purpose computer, an A/D (analog/digital conversion) interface is required to complete relevant conversion. In addition, in order to test the internal circuits of the embedded system, the processor chip generally adopts a boundary scan test technology. To accommodate this test, debug interfaces 506, 606 may also be employed in the system. Bus devices Bus0, bus1 are used for transferring instructions and data between processing unit 501 and other parts of the system (e.g., ram 508, serial interface 502, etc.).

Again, system 500 requires communication with devices located off-chip and other systems, and thus requires a connection interface. One or more of the following interface types may be provided on the system: USB (Universal Serial Bus, universal serial bus device abbreviation) interface (not shown), serial interfaces 502, 602, SPI (SERIAL PERIPHERAL INTERFACE ) interface (not shown), UART (communications transceiver, not shown), I2C bus device interface (not shown). Of course, the interface types applicable to the system are not limited to those described above. A general purpose computer will also have the same or similar interfaces, but the system will typically be provided with fewer interface types. Furthermore, the structure and function of the processing unit 501 are relatively simple compared to the processing unit in a general-purpose computer. For example, instruction set architectures support fewer instructions.

As shown, a master or slave device of one portion of the system 500 is connected to a single bus device and a master or slave device of another portion is connected to both bus devices. Specifically, the processing unit 501 is a master device connected only through the Bus device Bus0, and the slave devices connected only through the Bus device Bus0 have a serial interface 502, an a/D interface 503, and a debug interface 506. The master device connected only through the Bus device Bus1 is a processing unit 601, and the slave device has a serial interface 602, an a/D interface 603, and a debug interface 606. The slaves connected to both Bus0 and Bus1 are: random access memory 508, memory controller 507, and general purpose I/O interface 510. The physical port of the Bus device Bus0 connected to the ram 508 and the memory controller 507 is denoted as S0, and the physical port of the Bus device S1 connected to the ram 508 and the memory controller 507 is denoted as S1.

In addition, with the rapid development of ultra-large scale integrated circuits (VERY LARGE SCALE Integration) and semiconductor processes, the embedded system can be implemented on a silicon chip, i.e., an embedded system on a chip (SoC).

As can be seen from the figure, when the processing unit 501 performs a write transaction to the memory controller 507, the random access memory 508 and the general I/O interface 510, it is required to pass through the Bus device Bus0, and when the processing unit 601 performs a write transaction to the memory controller 507, the random access memory 508 and the general I/O interface 510, it is required to pass through the Bus device Bus1.

A write transaction involving a bus device will be described with reference to fig. 2, taking as an example a write transaction by the processing unit 501 to the memory controller 507. The processing unit 501 forms three channels of write transactions with Bus device Bus0, and Bus device Bus0 and memory controller 507 form three channels of write transactions. The channels, signals, and handshake mechanisms are the same as described above. The Bus device Bus0 here controls the data transmission via channels with the processing unit 501 and with the memory 507. For Bus devices Bus0 and Bus1, the simplest processing method is to complete one write transaction and then to process the next write transaction, so that although the processing efficiency is low, the Bus interlock problem does not occur. Bus interlock problems may occur when Bus devices Bus0 and Bus1 handle multiple write transactions simultaneously. By parallel processing of multiple write transactions, it is meant that the bus device does not have to wait for one write transaction to complete before processing the next write transaction. Parallel processing of multiple write transactions is one of the bus device characteristics of AXI, referred to as outstanding characteristics, and may be characterized by a maximum number of transactions in transit, e.g., the bus device has a maximum number of transactions in transit of 4, indicating that the number of write transactions processed in real-time in parallel does not exceed 4, if there are currently 4 write transactions in process, the bus device no longer acquires a new write transaction, and when one of the write transactions is completed, the bus device continues to acquire a new write transaction.

Fig. 6 shows a signal timing diagram of the embedded system shown in fig. 5. The process of generating a bus interlock problem is described below with reference to fig. 5 in conjunction with fig. 6. In this example, the maximum number of in-transit transactions for Bus device Bus0 and Bus device Bus1 is 4. The specific meaning of signals such as CLK, AWADDR, AWREADY, WVALID in the figures is the same as that described above, and will not be repeated here. In addition, the signal names on the drawing use the master or slave names as prefixes, for example, 501.Awaddr represents a write address signal transferred in a write address channel between the processing unit 501 and the Bus device Bus0, 507.S0.WREADY represents a write data ready signal transferred in a write data channel between the Bus device Bus0 and the memory controller 507, which has the same meaning and function as WREADY above.

First, from time T0, the processing unit 501 writes the write addresses addr1-addr4 to the write address channel, where addr1 and addr2 are write addresses of consecutive write transactions initiated by the processing unit 501 to the memory controller 507, and addr3-addr4 is a write address of consecutive write transactions initiated by the processing unit 501 to the random access memory 508. Similarly, from time T0, the processing unit 601 writes the write addresses addr3-addr4 and addr1-addr2 to the write address channel, where addr3-addr4 is the write address of the consecutive write transaction initiated by the processing unit 601 to the random access memory 508, and addr1-addr2 is the write address of the consecutive write transaction initiated by the processing unit 601 to the memory controller 507. A sequential write transaction refers to the act of writing data in successive clock cycles, as in fig. 6, addr1 and addr2 are written in two adjacent clock cycles.

At time T0, bus device Bus1 sets 601.Awready to high. Herein, a high level means an active level, and a low level means an inactive level.

At time T1, bus device Bus0 sets 501.Awready to high.

At time T2, the transfer of the write address between the processing unit 501 and the Bus0, between the Bus0 and the memory controller 507 and between the processing unit 601 and the Bus1, between the Bus1 and the memory controller 507 and between the memory controller 508, and between the write address phase is completed. As can be seen from the figure, the duration of the high level of 501.Awready is 4 clock cycles. Bus device Bus0 may control 501. The duration of the high level of awready depending on the number of write transactions currently in transit. For example, if the number of write transactions currently in transit is 2, bus device Bus0 may last the high level of 501. AWRADY for 2 clock periods to read out both write addresses. In addition, the timing diagram of signal AWVALID is omitted from the figure for ease of illustration.

At time T3, the signal 508.s0.wready goes high due to the different transmission delays, indicating that the write data channel of the random access memory 508 is preferentially responsive to the processing unit 501, waiting to accept data from the processing unit 501; while 507.s1.wready goes high indicating that the write data channel of memory controller 507 is preferentially responsive to processing unit 601 awaiting receipt of data from processing unit 601.

At time T4, since the memory controller 507 is not responsive to the write data from the processing unit 501 according to the write order-preserving principle, 507.s0.wready remains in a low level state until 507.s1 writing data is completed; inside the random access memory 508 is a serial design, and 508.s1.wready remains in a low state until 508.s0 writing data is completed, not in response to the writing data from the processing unit 601.

Thus, WVALID and WREADY cannot form a handshake mechanism at time T4, resulting in a transfer failure to complete, creating a bus interlock problem.

As can be appreciated from the above examples, based on the outbound characteristics of the AXI bus, the bus device, upon receiving a plurality of write transactions issued consecutively by the processing units 501 and 601, simultaneously containing both the memory controller 507 and the random access memory 508, causes bus interlock problems due to transfer delays and the like.

For the Bus interlock problem described above, as an alternative embodiment, bus devices Bus0 and Bus1 keep the maximum number of transactions in transit of the Bus device always at 1.

An exemplary illustration is provided with a bus device 70 as shown in fig. 7. As shown in fig. 7, the bus device 70 includes an arbitration unit 701, an address redirection unit 702 coupled to the arbitration unit 701, a write data buffer 704, and a write response buffer 705. The bus device 70 further comprises a write command buffer 703 coupled to the address redirection unit 702. The write command buffer 703 is used to receive write addresses and control information from the write address channel of the host device and to transfer the write address and control information to the address redirection unit 702. The address redirection unit 702 is used to redirect write addresses to the address space of the slave device for addressing. The write data buffer 704 is used to receive write data from the write data channel of the master device. The write response buffer 705 is used to receive response data of the slave device via the arbitration unit 701. The arbitration unit 701 is used to perform various arbitration operations.

For the purpose of keeping the maximum number of in-transit transactions of Bus devices Bus0 and Bus1 at 1, the write command buffer 703 may buffer only one write address, and buffer the next write address only after the execution of the write transaction corresponding to the write address is completed, or although the write command buffer 703 may buffer a plurality of write addresses, the write command buffer 703 may transmit one write address to the address redirecting unit 702 only after receiving the notification of the arbitration unit 701, and the arbitration unit 701 notifies the write command buffer 703 of transmitting one write address after the write address to the address redirecting unit 702 after determining that the execution of the write transaction corresponding to the write address is completed.

As another alternative embodiment, the write command buffer 703 may buffer a plurality of write addresses, but only after receiving the notification from the arbitration unit 701, the write command buffer 703 may send consecutive write addresses to the same slave device to the address redirection unit 702, and the arbitration unit 701 notifies the write command buffer 703 of the write address after the consecutive write transactions corresponding to the write address to the same slave device have been executed.

For example, as illustrated in the figure, the write command buffer 703 receives the write addresses addr1-addr4 from the master device 20, addr1 and addr2 are the write addresses to the slave device 30, addr3-addr4 are the write addresses to the slave device 31, then the write command buffer 703 will first send addr1-addr2 to the address redirecting unit 702, the address redirecting unit 702 will direct addr1 and addr2 to the address space of the slave device 30, while the master device 20 sends data corresponding to addr1 and addr2 to the write data buffer 704, and then sends the data to the address space of the slave device 30 via the arbitration unit 701, and the arbitration unit 701 receives the write response signal from the slave device 30 and writes to the write response buffer 705, and then provides the data to the master device 20. Thus, the arbitration unit 701 may determine that the write transaction corresponding to addr1-addr2 has been performed after receiving the write response signal or after writing the write response signal to the write response buffer 705, then inform the write command buffer 703 to transfer addr3-addr4 to the address redirection unit 702, and so on.

It should be emphasized that the number of consecutive write addresses to the same slave device among the plurality of write addresses in the present embodiment is less than or equal to the maximum number of in-transit transactions of the bus device. In other words, if the number of consecutive write addresses to the same slave device among the plurality of write addresses is greater than the maximum number of transactions in transit of the bus device, the write command buffer 703 should deliver the write addresses to the address redirection unit 702 in a number of transactions in transit that does not exceed the maximum number of transactions in transit of the bus device.

Furthermore, although it is specified in the present embodiment that consecutive write addresses to the same slave device among a plurality of write addresses are transferred to the address redirecting unit by the write command buffer according to the notification of the arbitration unit, the operation of this portion of the time product may also be implemented by the address redirecting unit 702, that is, the address redirecting unit 702 fetches consecutive write addresses to the same slave device only from the plurality of write addresses at a time, so that it is also possible to implement that write transactions executed in the same batch are all directed to the write addresses of the same slave device.

In addition, in engineering practice, developers may also use a combination of software and bus devices to solve the bus interlock problem. For example, the bus interlock problem can be basically solved by disabling the processing units from cross-accessing the different memories by software while reducing the maximum number of transactions in transit of the bus device to 2. Cross-accessing different memories refers to, for example, two consecutive write addresses, a first write address accessing a first memory and a second write address accessing a second memory.

Fig. 8 is a timing diagram of signals obtained by the system shown in fig. 7.

As shown in the figure, first, from time T0, the processing unit 501 writes the write addresses addr1-addr4 to the write address channel, where addr1 and addr2 are write addresses of the write transaction initiated by the processing unit 501 to the memory controller 507, addr3-addr4 is a write address of the two write transactions initiated by the processing unit 501 to the random access memory 508, and similarly, from time T0, the processing unit 601 writes the write addresses addr3-addr4 and addr1-addr2 to the write address channel, addr3-addr4 is a write address of the write transaction initiated by the processing unit 601 to the random access memory 508, and addr1-addr2 is a write address of the two write transactions initiated by the processing unit 601 to the memory controller 507.

At time T0, bus device Bus1 sets 601.Awready to high.

At time T1, bus device Bus0 sets 501.Awready to high.

Therefore, at time T2, the transfer of the write address between the processing unit 501 and Bus0, between Bus0 and the memory controller 507 and between the processing unit 601 and Bus1, between Bus1 and the memory controller 507 and between the random access memory 508 is completed, and only the write addresses addr1 and addr2 are transferred by controlling the duration of the high level of AWREADY and AWVALID. To achieve this, the duration of either high level of AWREADY and AWVALID is at least two clock cycles, i.e., the number of consecutive write addresses to the same slave device for addr1-addr4, including: 1) AWREADY remains high for all times, AWVALID remains high for two clock cycles; 2) AWVALID remains high for all times, AWREADY remains high for two clock cycles; 3) AWREADY and AWVALID are varied synchronously and the duration of the high level is equal to two clock cycles.

At time T3, 501.Wvalid and 501.Wready go high, indicating that the processing unit 501 is ready to write data, 507.S0.Wvalid and 507.S0.Wready go high, so that the processing unit 501 writes data of addr1 and addr2 to the memory controller 507 beginning at time T3. Also, at time T3, 601.Wvalid and 601.Wready become high, indicating that the processing unit 601 has ready to receive data, 508.s1.wvalid and 508.s1.wready become high, so that, starting at time T4, the processing unit 601 writes data of addr3 and addr4 to 508.

At time T4, 501.awaddr goes high, and since the maximum number of in-transit transactions is 2, the write addresses addr3 and addr4 are transferred during this time.

At time T5, 501.wvalid and 501.wready go high, 508.s1.wvalid and 508.s0.wready go high, so that at time T5, processing unit 501 writes addr3 and addr4 data to 508, and likewise at time T5, 601.wvalid and 601.wready go high, 507.s1.wvalid and 507.s0.wready go high, so that at time T5, processing unit 601 writes addr1 and addr2 data to 507.

As is apparent from the above-described timing chart, when a plurality of write transactions to the memory controller 507 and the random access memory 508 are sequentially issued to the processing unit 501 or 601, the write transaction to the same memory is processed after the execution of the write transaction to the same memory is completed, and so on, so that it is ensured that the bus interlock problem does not occur.

It should be understood that, although the above embodiment is described by taking an embedded system of a two-level bus device cascade as an example, the embedded system may be a three-level bus device cascade or more, and the bus interlock problem and the corresponding solution to be solved by the embodiments of the present disclosure may also be applied to an embedded system of a three-level bus device cascade or more.

Furthermore, although in the above embodiments, the processing unit is described as an example of a write transaction to the memory, this does not mean that the write transaction does not occur between other components, for example, if the security chip is included in an embedded system, the security chip may also access the memory as a slave device as a master device, and thus the embodiments of the present disclosure provide a solution to the bus interlock problem that can be applied extendably between any master device and slave device that employ bus device based connections.

In addition, the embedded system provided by the present disclosure also has various usage scenarios. For example, the embedded system is used as an edge computing device, and audio or video data is collected at the cloud computing edge and model computation is performed. For another example, the embedded system may be used as a distributed computing device, where the computing efficiency is improved by collecting a plurality of node data and performing distributed parallel computing using a plurality of internal processing units.

Commercial value of embodiments of the present disclosure

The bus equipment provided by the embodiment of the disclosure can be applied to various embedded equipment to ensure that the bus interlocking problem does not occur, and the embedded system has a plurality of use scenes, so that the bus equipment provided by the embodiment of the disclosure has high application value and market prospect.

Those skilled in the art will appreciate that the present disclosure may be implemented as a system, method, and computer program product. Accordingly, the present disclosure may be embodied in the form of hardware entirely, software (including firmware, resident software, micro-code), or in a combination of software and hardware. Furthermore, in some embodiments, the present disclosure may also be embodied in the form of a computer program product in one or more computer-readable media having computer-readable program code embodied therein.

Any combination of one or more computer readable media may be employed. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium is, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer readable storage medium include the following: in particular, the electrical connection of one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical memory, a magnetic memory, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with a processing unit, apparatus, or device.

The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a notch. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any other suitable combination. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., and any suitable combination of the foregoing.

Computer program code for carrying out embodiments of the present disclosure may be written in one or more programming languages or combinations. The programming languages include object oriented programming languages such as JAVA, c++, and may also include conventional procedural programming languages such as C. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

The foregoing is merely a preferred embodiment of the present disclosure, and is not intended to limit the present disclosure, so that various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. An embedded system, comprising:

A plurality of bus devices;

A plurality of master devices, each master device being connected to only one of the plurality of bus devices;

A plurality of slave devices, each slave device being connected to at least two bus devices of the plurality of bus devices, wherein the bus devices comprise:

2. The embedded system according to claim 1, wherein the arbitration unit controls a duration of an active level of any one of a write address active signal and a write address ready signal between the master device and the same slave device to be at least the number of consecutive write addresses to the same slave device.

3. The embedded system of claim 2, wherein the controlling the duration of the active level of any one of the write address active signal and the write address ready signal between the master device and the same slave device is at least the number of write addresses to the same slave device comprises:

4. The embedded system of claim 2, wherein the controlling the duration of the active level of any one of the write address active signal and the write address ready signal between the master device and the same slave device is at least the number of write addresses to the same slave device comprises:

5. The embedded system of claim 2, wherein the controlling the number of write addresses to the same slave device for a duration of an active level of any one of a write address active signal and a write address ready signal between the master device and the same slave device is at least the number of consecutive write addresses comprising:

6. The embedded system according to claim 2, wherein the arbitration unit controls the write data valid signal and the write data ready signal between the master device and the same slave device to be valid levels after a duration of a valid level of at least one of the write address valid signal and the write address ready signal between the master device and the same slave device is at least the number of consecutive write addresses to the same slave device.

7. The embedded system of claim 1, wherein the completion of the write transaction to the write address of the same slave device is determined by the arbitration unit via a received write reply signal from the same slave device.

8. The embedded system of claim 6, wherein the arbitration unit further controls at least one of a write data valid signal and a write data ready signal between the master device and the same slave device to change from a valid level to an invalid level after the execution of the write transaction to the write address of the same slave device.

9. An embedded system according to any one of claims 1 to 8, wherein the bus device is an AXI bus device.

10. An embedded system according to any one of claims 1 to 8, wherein the number of write addresses to the same slave device is less than or equal to the maximum number of in-transit transactions of the bus device.

11. The embedded system of claim 1, wherein the master device is a processing unit and the slave device is a memory controller or a random access memory.

12. The embedded system according to claim 1, wherein a plurality of the master devices are embedded processors and an acceleration unit, a plurality of the slave devices are a memory controller and a random access memory, the embedded processors control the memory controller to read data from an external memory and store the data into the random access memory, and the acceleration unit to read data from the random access memory to calculate.

13. A system on a chip, comprising:

A plurality of bus devices;

a plurality of master devices, each master device being connected to one of the plurality of bus devices;