CN101000593A

CN101000593A - Device and method for implementing communication between processes

Info

Publication number: CN101000593A
Application number: CN 200610086481
Authority: CN
Inventors: 季渊; 刘铁锋; 刘宇; 陈庆
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2006-06-23
Filing date: 2006-06-23
Publication date: 2007-07-18
Anticipated expiration: 2026-06-23
Also published as: CN100464319C

Abstract

A method for carrying out communication between processors includes setting multiprocessor communication unit in multiprocessor system, calling said multiprocessor communication unit by each processor through control bus in order to carry out communication between processors through said multiprocessor communication unit. The device used for realizing said method is also disclosed.

Description

Device and method for realizing communication between processors

Technical Field

The present invention relates to the field of communications, and in particular, to a device and method for implementing communication between processors.

Background

ARM (a reduced instruction set computer processor) is a mainstream RISC (reduced instruction set computer) processor widely used in embedded systems, and almost all semiconductor manufacturers in the world produce general-purpose chips based on the ARM architecture. ARM has a huge market in the fields of wireless devices, network products, consumer electronics, automotive electronics, mass storage devices, imaging systems, security products, and the like.

ARM has great advantages in operating systems, while DSP (digital signal processor) has great advantages in calculating various mathematical algorithms, so that many embedded systems adopt ARM + DSP architectures at present, and communication, media and other applications are realized through the ARM + DSP architectures.

In the prior art, a communication scheme between an ARM and a DSP is as follows: in the prior art, a multifunctional combined portable digital audio player is proposed, which belongs to a consumer electronics and computer peripheral product. The digital audio player has a plurality of digital audio decoding and digital recording functions such as MP3 and the like, and simultaneously has the functions of a PC external sound card, mobile storage, language repeating, an electronic watch, a perpetual calendar and the like, supports sound effects such as super bass, surround sound and the like, and the firmware can be upgraded.

The digital audio player adopts an ARM + DSP dual-core structure, and the ARM core processes decoding of various compressed audio files, realizes the functions of mobile storage and external sound card and supports multi-language display; the DSP kernel processes various sound effects; and a class-D power amplifier and a USB bus are adopted for supplying power. The digital audio player mainly comprises the following purposes: PC external sound card and loudspeaker, digital music playing, voice recording, mobile storage, FM radio, language repeater, electronic watch, electronic perpetual calendar and power amplifier.

The communication method between the ARM and the DSP in the prior art has the following disadvantages: in the dual-core audio processor of ARM + DSP in this scheme, the communication mechanism between ARM and DSP is relatively simple, and only simple communication such as inquiry and synchronization can be performed based on the waiting interaction mode, which is not conducive to faster operation of the system and more complex functions.

If the function level of the whole system is to be improved, the operation system must be run on the ARM, and various audio algorithms must be run on the DSP, then the ARM and the DSP must run cooperatively, and by simply relying on the above simple communication mechanisms such as query and synchronization based on the waiting interaction mode, considerable resources will be spent between the ARM and the DSP to monitor or wait for the behavior and state of the other party, and the running speed of the whole system cannot be exerted to a high degree. Meanwhile, a system without a good communication mechanism between the ARM and the DSP generally has difficulty in supporting functions or services such as a real-time operating system, a file system, and a large data volume operation, and is easily to cause a system to have a single function, even to be unstable.

Disclosure of Invention

In view of the above problems in the prior art, it is an object of the present invention to provide an apparatus and method for performing communication between processors, so as to achieve fast and timely communication between processors.

The purpose of the invention is realized by the following technical scheme:

the device comprises a multiprocessor communication unit and a control bus, wherein each processor accesses the multiprocessor communication unit through the control bus and carries out communication among the processors through the multiprocessor communication unit.

The multiprocessor communication unit specifically includes: a read-write controller, a decoder, and an interrupt register module, wherein:

a read-write controller: receiving an address signal and a control signal transmitted by a sending end processor through a control bus, generating a write enable signal and a read enable signal according to the control signal, and transmitting the generated write enable signal and read enable signal and the received address signal to a decoder;

a decoder: decoding the address signal, the write enable signal and the read enable signal transmitted by the read-write controller, and transmitting the decoded address signal, the decoded write enable signal and the decoded read enable signal to the interrupt register module;

an interrupt register module: the system comprises a plurality of interrupt registers, a decoder and a processor, wherein the interrupt registers write effective values in corresponding interrupt registers according to address signals and write enable signals transmitted by the decoder and output corresponding interrupt control signals to the processor at a receiving end; or reading out effective value from corresponding interrupt register according to address signal and read enable signal from decoder and outputting.

The multiprocessor communication unit further comprises:

a buffer: and receiving the address signal and the control signal transmitted by the sending end processor through the control bus, carrying out delay processing on the address signal and the control signal, and transmitting the processed address signal and the processed control signal to the read-write controller.

The multiprocessor communication unit further comprises:

an error judgment module: when the signal on the control bus accords with the error condition of the control bus protocol, the error control signal is transmitted to the read-write controller, so that the read-write controller does not generate effective write enable signals and read enable signals.

The interrupt register module specifically includes:

interrupt source register: the method comprises the steps of setting the number of bits, wherein each bit corresponds to an interrupt, and writing a corresponding effective value into the corresponding number of bits according to a write enable signal transmitted by a decoder;

an interrupt status register: the method comprises the steps of setting digits, writing a corresponding effective value into a corresponding digit according to the combination of the value of each digit in an interrupt source register, and outputting a corresponding interrupt control signal to a receiving end processor; or reading out the effective value from the corresponding interrupt source register according to the read enable signal transmitted by the decoder and outputting the effective value.

The interrupt register module further comprises:

interrupt enable register: the method comprises the steps of setting the number of bits, wherein each bit corresponds to an interrupt, and writing a corresponding effective value into the corresponding number of bits according to a write enable signal transmitted by a decoder; and the value of each bit in the interrupt enable register and the value of each bit in the interrupt source register are combined to obtain the value of the corresponding bit number in the interrupt status register.

The interrupt register module further comprises:

interrupt clear register: the method comprises the steps of setting the number of bits, wherein each bit corresponds to an interrupt, and setting the value of the corresponding bit of the interrupt source register to be invalid according to the value written in the corresponding bit.

The processor is as follows: a central processing unit CPU or a microprocessor MPU or a microcontroller MCU or a reduced instruction set computer processor ARM or a data signal processor DSP.

The control bus is as follows: advanced high-performance bus AHB or advanced peripheral bus APB or advanced system bus ASB or advanced extensible interface AXI or chip internal interconnection bus Wishbone.

A method for enabling communication between processors, comprising:

a multiprocessor communication unit is provided in a multiprocessor system, each processor accesses the multiprocessor communication unit via a control bus, and communication between the processors is performed via the multiprocessor communication unit.

The method comprises the following steps:

A. a sending end processor accesses the multiprocessor communication unit through a control bus, and writes effective values into corresponding bits of an interrupt source register in the multiprocessor communication unit, or writes effective values into corresponding bits of an interrupt enable register and an interrupt source register in the multiprocessor communication unit; the interrupt state register in the multiprocessor communication unit obtains the value of the corresponding digit according to the written effective value;

B. the multiprocessor communication unit generates an interrupt control signal according to the value of the corresponding digit in the interrupt state register and sends the interrupt control signal to a receiving end processor; and the receiving end processor acquires the effective value information written by the sending end processor according to the interrupt control signal.

The step A specifically comprises the following steps:

a1, the sending end processor accesses the multiprocessor communication unit through a control bus and sends an address signal and a control signal to the multiprocessor communication unit;

a2, writing effective values into corresponding bits of the interrupt source registers in the multiprocessor communication unit according to the address signals and the control signals, and combining the values of each bit in the interrupt source registers by the interrupt state registers in the multiprocessor communication unit to obtain the values of corresponding bits;

or,

and writing effective values into corresponding bits of a corresponding interrupt enable register and an interrupt source register in the multiprocessor communication unit according to the address signal and the control signal, and combining the values of each bit in the interrupt enable register and the interrupt source register by an interrupt state register in the multiprocessor communication unit to obtain the value of the corresponding bit.

The step B, in which the receiving end processor obtains the valid value information written by the sending end processor according to the interrupt control signal specifically includes:

b1, after receiving the interrupt control signal, the receiving end processor accesses the multiprocessor communication unit through the control bus and sends an address signal and a control signal to the multiprocessor communication unit;

b2, the multiprocessor communication unit reads the effective value from the corresponding bit of the interrupt source register or reads the effective value from the corresponding bit of the interrupt source register and the interrupt enable register according to the address signal and the control signal, and outputs the read effective value information to the receiving end processor.

The step B also comprises the following steps:

when the interrupt control signal is to be cleared, a valid value is written to a corresponding bit in an interrupt clear register in the multiprocessor communication unit, the interrupt clear register setting the corresponding bit of the interrupt source register to invalid.

Further comprising:

in the case where a plurality of interrupts occur simultaneously or a plurality of interrupts are nested, the multiprocessor communication unit prioritizes the plurality of interrupts by software, and preferentially responds to an interrupt having a high priority.

It can be seen from the above technical solutions that, by setting a multiprocessor communication unit between processors (such as a CPU, an ARM, or a DSP), the present invention has the following advantages compared with the prior art:

1. the processors (such as a CPU, an ARM or a DSP) interact through an interrupt mechanism, the real-time performance is very strong, and each time one processor needs the assistance of the other processor, the other processor can immediately give a response, so that the system performance is improved.

2. The coupling degree between the ARM and the DSP is improved, so that the SOC (on-chip) system such as ARM + DSP can meet the requirements of real-time, large data volume and multiple services in the aspects of audio, streaming media and communication, and the resources of the SOC system can be better utilized.

3. By expanding the bit width of the interrupt register, both the ARM and the DSP can have a plurality of maskable interrupt sources, and the application requirements of most communication, protocols, algorithms, real-time interaction and the like can be met.

4. The software completes the operations of interrupt inquiry, priority sequencing and the like, thereby saving hardware resources. The interrupt of ARM and DSP is output by combination, the occupied system interrupt resource is only 2, and the complexity of system hardware is reduced.

5. The invention can be applied to SOC systems with multiple ARM, multiple DSP and multiple layers of system buses by accessing the AHB bus interface in the multiprocessor communication unit to the SOC system bus.

Drawings

FIG. 1 is a schematic structural diagram of an embodiment of a system for completing an interrupt communication between an ARM and a DSP according to the present invention via an INT _ GEN;

FIG. 2 is a schematic interface diagram of INT _ GEN according to the present invention;

FIG. 3 is a schematic diagram of the INT _ GEN according to the present invention;

FIG. 4 is a flowchart illustrating a method for communication between an ARM and a DSP according to an embodiment of the present invention.

Detailed Description

The invention provides a device and a method for realizing communication between processors, the core of the invention is as follows: an INT _ GEN (multiprocessor communication unit) is provided in the multiprocessor system, and each processor accesses the INT _ GEN multiprocessor communication unit through a control bus and performs communication through the INT _ GEN multiprocessor communication unit.

The present invention is described in detail below, and the processor according to the present invention may be: a CPU (central processing unit), an MPU (microprocessor), an MCU (microcontroller), an ARM (reduced instruction set computer processor), or a DSP (data signal processor). The present invention is described below by taking ARM and DSP as examples.

The schematic structural diagram of the embodiment of the system for completing the interrupt communication between the ARM and the DSP by the INT _ GEN according to the present invention is shown in fig. 1. ARM _ AHB (ARM _ advanced high Performance bus) and DSP _ AHB (DSP _ advanced high Performance bus) are connected through MUX (multiplexer), and the MUX is connected with INT _ GEN through the AHB bus, and both ARM and DSP can select to access INT _ GEN through the MUX.

The ARM, the DSP and the INT _ GEN can also be hung on the same AHB bus, the control right of the AHB bus is judged through an arbiter on the AHB bus, and the current ARM and the DSP are judged to have access right to the INT _ GEN.

In practical applications, the AHB bus may be replaced by an APB (advanced peripheral bus), an ASB (advanced system bus), an AXI (advanced extensible interface), or a Wishbone (inter-chip interconnect bus).

The INT GEN can be integrated into the system controller, or into the interrupt controller of the entire system, or into other modules.

The interface schematic of INT _ GEN described above is shown in fig. 2. The system comprises an AHB Slave bus interface, an arm _ int interface and a dsp _ int interface.

The AHB Slave bus interface signal is connected with an AHB bus and used for reading and writing access of a configuration register in an INT _ GEN of the AHB system bus line. The AHB interface conforms to the AHB protocol of AMBA (advanced microprocessor bus architecture).

The ARM _ int signal is an ARM interrupt signal, i.e., an interrupt signal sent to the ARM by the AHB bus. The DSP _ int signal is a DSP interrupt signal, i.e., an interrupt signal sent to the DSP by the AHB bus. These two interrupt signals may also be connected to an interrupt controller (such as the vector interrupt controller IP provided by ARM corporation) of the overall system for further combination and prioritization with other interrupt signals.

The INT _ GEN is shown in fig. 3, and includes an interrupt register module: buffer, read/write controller, DEC module and error decision module.

An interrupt register module: the system comprises 8 registers, namely an ARM interrupt source register, an ARM interrupt enable register, an ARM interrupt clear register, an ARM interrupt state register, a DSP interrupt source register, a DSP interrupt enable register, a DSP interrupt clear register and a DSP interrupt state register. All registers are 32 bits wide, each bit in the four registers related to the ARM corresponds to an ARM interrupt, and each bit in the four registers related to the DSP corresponds to a DSP interrupt, so that the ARM and the DSP can respectively have 32 logic interrupt sources. And combining all 32-bit values in the ARM interrupt state register through the MUX to output an ARM _ int signal, and combining all 32-bit values in the DSP interrupt state register through the MUX to output a DSP _ int signal. Buffer: and receiving an address signal haddr and control signals hsel, htrans, hwrite and hreadyin transmitted by the DSP or the ARM through an AHB bus, so that the address signal haddr and the control signals hsel, htrans, hwrite and hreadyin are delayed by one beat, and the address signal haddr and the data signal wrdata are effective in the same clock. And transmitting the processed address signal haddr and the control signals hsel, htrans, hwrite and hreadyin to the read-write controller.

A read-write controller: generating a write enable signal and a rden enable signal according to the control signals hsel, htrans, hwrite and hreadyin transmitted by the Buffer, and transmitting the generated write enable signal and rden and the received address signal haddr to the DEC module.

A DEC module: and decoding the address signals haddr, wren and rden transmitted by the read-write controller, and addressing 8 interrupt registers in the register module according to the decoded address signals haddr. When wren is effective, writing correct wrdata into corresponding positions of an interrupt enable register and an interrupt source register obtained through addressing, namely setting the wrdata to be effective; when rden is active, data is read out from the corresponding location of the interrupt source register obtained by addressing, and the read data is output through the MUX, which can be accessed by the AHB bus in the next beat.

An error judgment module: when the AHB interface signal accords with the error condition of the AHB bus protocol, the error discrimination module makes hreadyout on the AHB bus pull down by one beat, which indicates that the current data transmission is in error. And transmits an ERROR control signal hreadyou to the read/write controller, and does not generate valid wren and rden signals from the read/write controller while setting hresp to ERROR, holding two beats.

Based on the INT _ GEN, a processing flow of an embodiment of a method for performing communication between an ARM and a DSP is shown in fig. 4, and includes the following steps:

step 4-1: the DSP or ARM accesses the INT _ GEN and transmits an address signal and a control signal to the INT _ GEN.

When the DSP needs to send an interrupt to the ARM, the DSP firstly accesses INT _ GEN through an AHB bus, transmits corresponding address signals and control signals to a Buffer, and the Buffer carries out delay processing on the address signals and the control signals and transmits the processed address signals and the processed control signals to a read-write controller. The read-write controller generates wren according to the control signal transmitted by the Buffer, and transmits the generated wren and the received address signal to the DEC module.

When the ARM needs to send an interrupt to the DSP, the ARM firstly accesses INT _ GEN through an AHB bus and transmits corresponding address signals and control signals to a Buffer, the Buffer carries out delay processing on the address signals and the control signals and transmits the processed address signals and the processed control signals to a read-write controller. The read-write controller generates wren according to the control signal transmitted by the Buffer, and transmits the generated wren and the received address signal to the DEC module.

Step 4-2: the corresponding bits of the interrupt enable register and interrupt source register in INT GEN are set to valid.

When the DSP needs to send an interrupt to the ARM, the DEC module decodes the address signal and wren transmitted by the read-write controller, and addresses 8 interrupt registers in the register module according to the decoded address signal. And writing correct wrdata into corresponding bits of the ARM interrupt enable register and the ARM interrupt source register obtained through addressing, namely setting the bits to be valid. Because the value of the ARM interrupt state register is the combination of the ARM interrupt source register and the ARM interrupt enable register, the combined result ensures that the interrupt bit is valid, and therefore, the corresponding bit of the ARM interrupt state register is also valid.

In the above processing procedure, the DEC module may also write effective values only in corresponding bits of the ARM interrupt source register, and the ARM interrupt state register combines values of each bit in the ARM interrupt source register to obtain values of corresponding bits.

When the ARM needs to send an interrupt to the DSP, the DEC module decodes the address signals and wren transmitted by the read-write controller, and addresses 8 interrupt registers in the register module according to the decoded address signals. And writing correct wrdata into corresponding positions of the DSP interruption enabling register and the DSP interruption source register obtained through addressing, namely setting the correct wrdata to be valid. Because the value of the DSP interruption state register is the combination of the DSP interruption source register and the DSP interruption enabling register, the combined result ensures that the interruption bit is valid, and therefore, the corresponding bit of the DSP interruption state register is also valid.

In the above processing procedure, the DEC module may also write an effective value only in a corresponding bit of the DSP interrupt source register, and the DSP interrupt state register combines values of each bit in the DSP interrupt source register to obtain a value of a corresponding bit.

Step 4-3: and the INT _ GEN sends an ARM _ INT signal or a DSP _ INT signal according to the values of all the bits in the interrupt state register, and the ARM or the DSP inquires the INT _ GEN after receiving the ARM _ INT signal or the DSP _ INT signal to acquire effective value information.

When the corresponding bit of the DSP interrupt state register or the ARM interrupt state register is set to be effective, the INT _ GEN can generate a DSP _ in signal or a tar _ INT signal according to the value of all the bits in the DSP interrupt state register or the ARM interrupt state register, and sends an ARM _ INT signal to the ARM or sends a DSP _ INT signal to the DSP.

The ARM _ int signal is a combined output of all 32 bits in the ARM interrupt status register, and is a logical or of 32 bits if the interrupt high level is active, or is a logical and of 32 bits if the interrupt low level is active. When the ARM _ int is to be cleared, a valid value is written into a corresponding bit in the ARM interrupt clear register, and the valid value can be a high level or a low level. The ARM interrupt clear register sets the corresponding bit of the ARM interrupt source register to be invalid, and therefore the corresponding bit in the ARM interrupt state register is cleared.

The DSP _ int signal is the combined output of all 32 bits in the DSP interrupt status register, which is the logical or of 32 bits if the interrupt high is active, or the logical and of 32 bits if the interrupt low is active. If the DSP _ int is to be cleared, a valid value is written to the corresponding bit in the DSP interrupt clear register. The effective value may be high or low. The DSP interruption clearing register sets the corresponding bit of the DSP interruption source register to be invalid, thereby clearing the corresponding bit in the DSP interruption state register.

The ARM and the DSP both have 32 interrupt sources, after receiving the ARM _ INT signal or the DSP _ INT signal, the ARM or the DSP needs to query the INT _ GEN again to obtain the effective value information written by the DSP or the ARM in the interrupt source register and the interrupt enable register, that is, to query the effective value information, and the specific query process is as follows:

when the DSP needs to inquire an effective value from INT _ GEN, namely corresponding interrupt event information, the DSP firstly accesses INT _ GEN through an AHB bus and transmits corresponding address signals and control signals to a Buffer, and the Buffer carries out delay processing on the address signals and the control signals and transmits the processed address signals and the processed control signals to a read-write controller. The read-write controller generates rden according to the control signal transmitted by the Buffer, and transmits the generated rden and the received address signal to the DEC module.

The DEC module decodes the address signals and rden transmitted by the read/write controller, and addresses 8 interrupt registers in the register module according to the decoded address signals. The valid value is read from the corresponding DSP interrupt source register. And outputs the read valid value to the DSP through the MUX. Each bit in the DSP interrupt source register logically represents an interrupt source, and the effective value of the INT _ GEN output is the combined interrupt DSP _ INT of these bits (as long as one of these bits is effective, INT _ GEN will generate the interrupt output).

When the ARM needs to inquire an effective value from the INT _ GEN, the ARM needs to access the INT _ GEN through the AHB bus, transmit a corresponding address signal and a corresponding control signal to the Buffer, delay the address signal and the control signal by the Buffer, and transmit the processed address signal and the processed control signal to the read/write controller. The read-write controller generates rden according to the control signal transmitted by the Buffer, and transmits the generated rden and the received address signal to the DEC module.

The DEC module decodes the address signals and rden transmitted by the read/write controller, and addresses 8 interrupt registers in the register module according to the decoded address signals. The valid value is read from the corresponding ARM interrupt source register. And outputs the read valid value to the ARM through the MUX. Each bit in the ARM interrupt source register logically represents an interrupt source, and the effective value of the INT _ GEN output is the combination of these bits to interrupt ARM _ INT (as long as one of these bits is effective, INT _ GEN will generate an interrupt output).

And under the condition of simultaneously generating a plurality of interrupts or nesting a plurality of interrupts, the INT _ GEN carries out priority ordering operation on the plurality of interrupts through software and responds to the interrupts with high priority preferentially.

For example, the case where a plurality of interrupts occur simultaneously is as follows: the interrupt 2 with high priority and the interrupt 5 with low priority are simultaneously interrupted, and INT _ GEN judges that the priority of the interrupt 2 is higher than that of the interrupt 5 through software, so INT _ GEN firstly responds to the interrupt 2; after the interrupt 2 is finished, the interrupt 2 is cleared and then the interrupt 5 is responded to. The processing mechanism for simultaneously generating more than two interrupts is the same as the above process, and always responds to the interrupt with high priority first.

For example, the case of multiple interrupt nesting is as follows: the interrupt 3 with low priority is interrupted first, the INT _ GEN responds to the interrupt 3 through software, clears the interrupt source of the interrupt 3, and runs an interrupt service program of the interrupt 3; at this time, a high-priority interrupt 6 occurs again, so the INT _ GEN responds to the interrupt 6 immediately through software, shields the interrupt 3 entering the low-priority interrupt, and runs the interrupt service routine of the interrupt 6; and when the interrupt 6 is completely operated, the service program of the interrupt 3 is operated. The processing mechanism for nesting more than two interrupts at the same time is the same as the above process, and always responds to the interrupt with high priority first.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. The device for realizing communication among the processors is characterized by comprising a multiprocessor communication unit and a control bus, wherein each processor accesses the multiprocessor communication unit through the control bus and carries out communication among the processors through the multiprocessor communication unit.

2. The apparatus of claim 1, wherein the multiprocessor communication unit specifically comprises: a read-write controller, a decoder, and an interrupt register module, wherein:

3. The apparatus of claim 2, wherein the multiprocessor communication unit further comprises:

4. The apparatus of claim 2, wherein the multiprocessor communication unit further comprises:

5. The apparatus of claim 2, 3 or 4, wherein the interrupt register module specifically comprises:

6. The apparatus of claim 5, wherein said interrupt register module further comprises:

7. The apparatus of claim 5, wherein said interrupt register module further comprises:

8. The apparatus of claim 1, wherein the processor is configured to: a central processing unit CPU or a microprocessor MPU or a microcontroller MCU or a reduced instruction set computer processor ARM or a data signal processor DSP.

9. The apparatus of claim 1, wherein the control bus is: advanced high-performance bus AHB or advanced peripheral bus APB or advanced system bus ASB or advanced extensible interface AXI or chip internal interconnection bus Wishbone.

10. A method for enabling communication between processors, comprising:

11. The method according to claim 10, comprising the steps of:

12. The method according to claim 11, wherein the step a specifically comprises:

or,

13. The method according to claim 11 or 12, wherein the step B of acquiring, by the receiving-end processor according to the interrupt control signal, the valid value information written by the sending-end processor specifically includes:

14. The method according to claim 11 or 12, wherein said step B further comprises:

15. The method of claim 11 or 12, further comprising: