CN113820612B - Error compensation circuit and integrated circuit for measuring battery impedance - Google Patents

Abstract

The invention relates to an error compensation circuit, which includes a delay unit, a first error detection unit, a second error detection unit, a first error compensation unit, a second error compensation unit and an output control unit. Among them, the delay unit is used to delay the input signal for a fixed time to generate the first delayed signal; the first error detection unit is used to compare the first delayed signal with the output signal of the external component to detect the rising edge of the output signal error, the second error detection unit is used to compare the first delay signal and the output signal of the external component to detect the falling edge error of the output signal; the first error compensation unit is used to generate the first compensation signal according to the rising edge error and the input signal, The second error compensation unit is used to generate the second compensation signal according to the falling edge error and the input signal; the output control unit is used to control the error compensation circuit to output the first compensation signal or the second compensation signal, so as to compensate the output signal generated by the external components error.

Description

Error Compensation Circuit and Integrated Circuit for Measuring Battery Impedance

technical field

The invention relates to the field of integrated circuits, in particular to an error compensation circuit and an integrated circuit for measuring battery impedance.

Background technique

In the field of battery research, measuring battery internal resistance (impedance) parameters is an important means to evaluate battery performance. Electrochemical Impedance Spectroscopy (EIS, Electrochemical Impedance Spectroscopy) is usually used to measure the internal resistance of the battery. The measurement principle is to input sinusoidal voltage (current) signals of small amplitude and different frequencies to the battery system under the normal working state of the battery, measure the corresponding output current (voltage) signal, and obtain the lithium battery according to the ratio of the voltage signal to the current signal of each frequency. The frequency impedance spectrum of the battery can reflect subtle changes in the battery.

FIG. 1 is a schematic diagram of a battery impedance measurement system. Referring to FIG. 1 , the battery impedance measurement system 100 mainly includes a signal generator 110 and a measurement circuit 120 . Wherein, the signal generator 110 outputs the sine wave signal and the cosine wave signal to the external battery 140 and the measurement circuit 120 . The signal generator 110 can generate a sine wave signal (Sin) and a cosine wave signal (Cos) with a frequency of 7.45mHz to 7.8kHz. There is a phase difference of 180 degrees between Cos and -Cos. The measurement circuit 120 is usually a FFT/DFT (Fast Fourier Transform/Discrete Fourier Transform) circuit. The battery impedance measurement system 100 also includes an external transistor 130 connected in parallel with the external battery 140 . The external transistor 130 functions as a switch. The external transistor 130 and an external resistor 131 are used to control whether to input the current/voltage signal from the signal generator 110 to the external battery 140 . As shown in FIG. 1 , the real part (Zreal) and the imaginary part (Zimag) of the impedance Z of the external battery 140 can be obtained through calculation by the measuring circuit 120 . However, since the characteristics of the external transistor 130 are affected by temperature and voltage, the signal passing through the external transistor 130 will be deformed, such as changes in phase and amplitude, and the signal input to the external battery 140 will also be deformed, such as the current Both the duty cycle and the amplitude of the signal vary. And this change is not constant, but varies with the ambient temperature, the voltage applied to the external transistor 130 , and the characteristics of the external transistor 130 itself. This will lead to inaccurate measurement results of the impedance of the external battery 140 .

FIG. 2 is a schematic diagram of signal deformation of the external transistor in FIG. 1 . 2, ideally, the gate voltage (Ideal Gate voltage) of the external transistor 130 and the MOS current (Ideal MOS current) flowing through the external transistor 130 are both square waves, and the square wave has an ideal vertical rising and falling edges, and the duty cycle of the signal is 50%. However, due to the above-mentioned problems, the actual gate voltage (Gate voltage) and MOS current (MOS current) of the external transistor 130 are deformed, which is specifically manifested in that its rising and falling edges are not ideal vertical rise and fall, Instead, it curves up and down. The left figure in Fig. 2 shows the deformation of the rising edge (Up), and the right figure shows the deformation of the falling edge (Down). In addition, the rising and falling edges of the gate voltage and MOS current have phase shifts respectively, and the phase shifts of the rising and falling edges are not equal, which means that the duty cycle of the signal has also changed, resulting in error. For different types and parameters of the external transistor 130 , as well as different ambient temperatures and voltages, the curves shown in FIG. 2 will be different. Therefore, it is necessary to provide a method for compensating the signal errors of various external transistors 130 under different ambient temperatures and voltages.

Contents of the invention

The technical problem to be solved by the present invention is to provide an error compensation circuit, which performs error compensation on the output signal of the external components in the battery impedance measurement circuit, and realizes accurate measurement of the external battery impedance.

In order to solve the above technical problems, the present invention provides an error compensation circuit, the input signal of the error compensation circuit has a rising edge and a falling edge, and the error compensation circuit is connected with an external component for compensating the error caused by the external component. error, the error compensation circuit includes: a delay unit, a first error detection unit, a second error detection unit, a first error compensation unit, a second error compensation unit and an output control unit; wherein the delay unit is used for Delaying the input signal for a fixed time to generate a first delayed signal; the first error detection unit is used to compare the first delayed signal with the output signal of the external component to detect the output signal The rising edge error of the second error detection unit is used to compare the first delay signal and the output signal of the external component to detect the falling edge error of the output signal; the first error compensation unit is used to Generate a first compensation signal according to the rising edge error and the input signal, the second error compensation unit is used to generate a second compensation signal according to the falling edge error and the input signal; and the output control unit uses for controlling the error compensation circuit to output the first compensation signal or the second compensation signal.

In an embodiment of the present invention, the error compensation circuit further includes a first counting unit and a second counting unit, the first counting unit is used to count the rising edge errors detected by the first error detection unit, The second counting unit is used for counting the falling edge errors detected by the second error detecting unit.

In an embodiment of the present invention, the first counting unit includes a first register for registering the number of rising edge errors, and the second counting unit includes a first register for registering the number of falling edge errors Second register.

In an embodiment of the present invention, when the number of rising edge errors reaches a first threshold, the first counting unit sends the number of rising edge errors to the first error compensation unit; When the number of falling edge errors reaches a second threshold, the second counting unit is configured to send the number of falling edge errors to the second error compensation unit.

In an embodiment of the present invention, the first error detection unit and/or the second error detection unit is a phase frequency detector.

In an embodiment of the present invention, the fixed time delay is 2 microseconds.

In an embodiment of the present invention, the output control unit is a switch circuit.

In an embodiment of the present invention, the input signal is a square wave.

In an embodiment of the present invention, the output signal is connected to an external battery and used to measure the impedance of the external battery.

In an embodiment of the present invention, the error compensation circuit is adapted to be integrated in a battery impedance measurement circuit.

In order to solve the above-mentioned technical problems, the present invention also proposes a battery impedance measurement system, which includes the above-mentioned error compensation circuit.

The error compensation circuit of the present invention uses the output signal of the external component as a feedback input, and detects the rising edge and falling edge of the output signal of the external component respectively, thereby performing real-time error compensation for the error of the rising edge and falling edge respectively, It can effectively compensate the errors caused by temperature, voltage, etc. on the output signal of external components, and is suitable for various types of external components. The battery impedance measurement system of the present invention adopts the error compensation circuit, which can improve the accuracy of the impedance measurement of the external battery.

Description of drawings

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

1 is a schematic diagram of a battery impedance measurement system;

Fig. 2 is a schematic diagram of deformation of the signal of the external transistor in Fig. 1;

3 is a schematic structural diagram of a battery impedance measurement system according to an embodiment of the present invention;

4 is a schematic structural diagram of a battery impedance measurement system according to another embodiment of the present invention;

FIG. 5 is a schematic diagram of signals after being compensated by an error compensation circuit according to an embodiment of the present invention.

detailed description

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

In the following description, many specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways than those described here, so the present invention is not limited by the specific embodiments disclosed below.

In addition, it should be noted that the use of words such as "first" and "second" to define components is only for the convenience of distinguishing corresponding components. To limit the protection scope of this application. In addition, although the terms used in this application are selected from well-known and commonly used terms, some terms mentioned in the specification of this application may be selected by the applicant according to his or her judgment, and their detailed meanings are listed in this article described in the relevant section of the description. Furthermore, it is required that this application be understood not only by the actual terms used, but also by the meaning implied by each term.

It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on the other element. On, connected or coupled to, or in contact with, the other component, or there may be an intervening component. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present. Likewise, when a first component is referred to as being "electrically contacting" or "electrically coupled to" a second component, there exists an electrical path between the first component and the second component that allows electrical current to flow. This electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow, even without direct contact between conductive components.

In the battery impedance measurement circuit, the external components are used to control the on-off of the current transmitted to the battery under test, so the performance of the external components itself has an important impact on the transmission of the measurement signal, and also has a significant impact on the accuracy of the measurement results. Embodiments of the present invention describe an error compensation circuit and a battery impedance measurement system including the error compensation circuit.

FIG. 3 is a schematic structural diagram of a battery impedance measurement system according to an embodiment of the present invention. As shown in FIG. 3 , in the battery impedance measurement system 200 , the signal generator 210 can generate a square wave signal as the input signal S of the error compensation circuit 220 of the present invention. It can be understood that the square wave signal has a rising edge and a falling edge. Extracting the first harmonic from a square wave signal produces a sine wave signal. The sine wave signal can be in the form of a sine function or a cosine function according to the phase difference, and the sine wave signal and the cosine wave signal can be used as input signals of the impedance measurement circuit 250 .

Under normal circumstances, the signal measured from both ends of the external battery 240 of the impedance to be measured is input to the impedance measurement circuit 250 after passing through the processing circuit 260 . The impedance measurement circuit 250 calculates and outputs the impedance Z of the external connection 240 according to the sine wave signal and/or the cosine wave signal generated by the signal generator 210 and the signal after the processing circuit 260 . Impedance measurement circuit 250 may be measurement circuit 120 as described in FIG. 1 .

Referring to FIG. 3 , the present invention provides an error compensation circuit 220 . The error compensation circuit 220 is connected to an external component 230 for compensating errors caused by the external component 230 . The error compensation circuit 220 includes a delay unit 221 , a first error detection unit 222 a , a second error detection unit 222 b , a first error compensation unit 223 a , a second error compensation unit 223 b and an output control unit 224 . Wherein, the delay unit 221 is configured to delay the input signal S for a fixed time to generate the first delayed signal S1. The first delayed signal S1 is transmitted to the first error detection unit 222a and the second error detection unit 222b. Correspondingly, the first delayed signal S1 also includes a rising edge and a falling edge.

In an embodiment of the present invention, the fixed delay of the first delayed signal S1 relative to the input signal S is 2 μs. The duration of the fixed delay is determined by the maximum delay that the external component 230 can cause.

Referring to FIG. 3 , the first delayed signal S1 is input into the first error detection unit 222 a and the second error detection unit 222 b respectively. In the embodiment shown in FIG. 3 , the external component 230 is specifically a transistor, the drain of the transistor is connected to the anode of the external connection 240 after passing through a resistor 231 ; the source of the transistor is connected to the negative terminal of the external connection 240 . The output terminal of the output control unit 224 is connected to the gate of the transistor, that is, the output signal of the output control unit 224 is used as a switch control signal Sc of the transistor to control the transistor to be turned on and off. The drain of the transistor is connected to the first error detection unit 222a and the second error detection unit 222b, and the output signal Sext after passing through the external element 230 is input to the first error detection unit 222a and the second error detection unit 222b.

The first error detection unit 222a is used to compare the first delay signal S1 and the output signal Sext of the external component 230 to detect the rising edge error Sd_u of the output signal Sext, and the second error detection unit 222b is used to compare the first delay signal S1 and the output signal Sext of the external component 230 to detect the falling edge error Sd_d of the output signal Sext.

The present invention does not limit the specific implementation of the external component 230, the external component 230 can be various types of transistors, such as bipolar transistors (BJT), field effect transistors (FET), etc., and can also be other similar meeting Electronic components that cause errors.

3, the first error detection unit 222a is connected to the first error compensation unit 223a, and the detected rising edge error Sd_u is input to the first error compensation unit 223a; the second error detection unit 222b is connected to the second error compensation unit 223a; The compensation unit 223b is connected to input the detected falling edge error Sd_d to the second error compensation unit 223b. The input signal S generated from the signal generator 210 is also input into the first error compensation unit 223a and the second error compensation unit 223b at the same time.

The first error compensation unit 223a determines its output first compensation signal Sc1 according to the input signal S and the rising edge error Sd_u, and inputs the first compensation signal Sc1 to the output control unit 224; the second error compensation unit 223b according to the input signal S and the falling edge error Sd_d determine the output second compensation signal Sc2, and input the second compensation signal Sc2 to the output control unit 224 .

The output control unit 224 is used for controlling the error compensation circuit 220 to output the first compensation signal Sc1 or the second compensation signal Sc2. Specifically, the output control unit 224 determines the control signal Sc to be output to the external component 230 according to the first compensation signal Sc1 and the second compensation signal Sc2. The control signal Sc may be the first compensation signal Sc1 or the second compensation signal Sc2. The signal input to the external component 230 is controlled by the control signal Sc, so as to compensate for problems such as rising edge and falling edge deformation and delay caused by the external component 230 .

In some embodiments, the output control unit 224 is a switch circuit.

For example, when the fixed delay of the first delayed signal S1 relative to the input signal S is set to be 2 μs, that is, 2000 ns. The first error detection unit 222a detects that the rising edge error Sd_u of the output signal Sext is 200ns, and the second error detection unit 222b detects that the falling edge error Sd_d of the output signal Sext is 600ns, then the first error compensation unit 223a will make the first compensation The signal Sc1 is delayed by 1800 ns compared to the input signal S, and the second error compensation unit 223 b delays the second compensation signal Sc2 by 1400 ns compared to the input signal S.

In some embodiments, the first error detection unit 222a and/or the second error detection unit 222b may be a phase detector or a phase and frequency detector (Phase and Frequency Detector). A phase detector can be used to detect the phase difference between an input signal and a reference signal. The first error detection unit 222a is used to detect the phase difference between the rising edge of the output signal Sext and the rising edge of the first delayed signal S1, and the second error detection unit 222b is used to detect the falling edge of the output signal Sext and the first delayed signal S1. The phase difference between the falling edges of the time signal S1.

In a preferred embodiment, both the first error detection unit 222a and the second error detection unit 222b are phase and frequency detectors for comparing the phase or frequency difference between the signal to be tested and the reference signal. Typically, phase and frequency detectors include two output pins: an up (UP) pin and a down (DOWN) pin. According to the comparison result, a pulse train is generated on the UP and DOWN pins. The pulse train indicates the degree to which the signal to be detected needs to be adjusted. For example, the pulse train on the UP pin indicates the degree to which the frequency of the signal to be tested needs to be increased. The pulse train indicates how much the frequency of the signal under test needs to be reduced. For a signal input to a phase and frequency detector, the phase of the signal can be obtained from the position of the detected signal edges and the frequency of the signal can be obtained from the number of detected signal edges. It can be understood that the phase and frequency detector obtains the phase and frequency of the detected signal through a certain calculation method.

The phase and frequency detector as the first error detection unit 222a is set to be triggered by a rising edge. Correspondingly, the phase and frequency detector serving as the second error detection unit 222b is set to trigger on the falling edge. When the frequency and/or phase of the rising edge of the first delay signal S1 and the rising edge of the output signal Sext of the external component 230 are different, the UP pin or the DOWN pin of the first error detection unit 222a outputs a pulse train as the first A rising edge error Sd_u output by the error detection unit 222a. Correspondingly, when the frequency and/or phase of the falling edge of the first delayed signal S1 and the falling edge of the output signal Sext of the external component 230 are different, the UP pin or the DOWN pin of the second error detection unit 222b outputs a pulse train , as the falling edge error Sd_d output by the second error detection unit 222b.

The phase detector or phase and frequency detector used in the present invention can be a commonly used phase and frequency detector in the field, and is suitable for integration in an integrated circuit.

In some cases, due to the jitter of the first delayed signal S1 and/or the output signal Sext, the first error detection unit 222a and the second error detection unit 222b may wrongly detect some jitter as the rising edge error Sd_u and/or the falling edge error Along the error Sd_d. To solve this problem, in some embodiments, the error compensation circuit 220 of the present invention further includes a first counting unit 225a and a second counting unit 225b, as shown in FIG. 4 .

FIG. 4 is a schematic structural diagram of a battery impedance measurement system according to another embodiment of the present invention. In the embodiment shown in FIG. 4, the first error detection unit 222a sends the detected rising edge error Sd_u to the first counting unit 225a, and the first counting unit 225a counts the number of the received rising edge errors Sd_u counting, and when the number reaches a first threshold, the first counting unit 225a sends the rising edge error Sd_u to the first error compensation unit 223a. Referring to Fig. 4, the first counting unit 225a of this embodiment is also connected with the first register 226a, and the first register 226a is used to register the quantity of the rising edge error Sd_u obtained by the first counting unit 225a, and in this When the number of rising edge errors Sd_u reaches the first threshold, the rising edge errors Sd_u are sent to the first error compensation unit 223a.

Similarly, the second error detection unit 222b sends the detected falling edge error Sd_d to the second counting unit 225b, and the second counting unit 225b counts the number of the received falling edge error Sd_d, when it is found that the number reaches When a second threshold is reached, the second counting unit 225b sends the falling edge error Sd_d to the second error compensation unit 223b. Referring to Fig. 4, the second counting unit 225b of this embodiment is also connected with the second register 226b, and the second register 226b is used to register the quantity of the falling edge error Sd_d obtained by the second counting unit 225b, and in this The falling edge error Sd_d is sent to the second error compensation unit 223b only when the amount of the falling edge error Sd_d reaches the second threshold.

In some embodiments, the first threshold and the second threshold are two fixed values. Only when the counting results of the first counting unit 225a and the second counting unit 225b reach the first threshold and the second threshold respectively, the output results of the first register 226a and the second register 226b will be updated once. Jitter causes false compensation.

In the embodiment shown in FIG. 3 and FIG. 4 , the first error detection unit 222a detects the falling edge error Sd_d of the output signal Sext, and the second error detection unit 222b detects the rising edge error Sd_u of the output signal Sext. In other embodiments, the first error detection unit 222a can detect the rising edge error Sd_u of the output signal Sext, and the second error detection unit 222b can detect the falling edge error Sd_d of the output signal Sext.

In a specific embodiment, it is assumed that the clock period of the battery impedance measurement system 200 of the present invention is 62.5 ns. If after the measurement of the error compensation circuit 220 of the present invention, the count result obtained by the first register 226a is 13, and the count result obtained by the second register 226b is 8, it means that the detected rising edge error Sd_u of the output signal Sext is 13*62.5=812.5ns, the falling edge error Sd_d is 8*62.5=500ns.

The first error compensation unit 223a and the second error compensation unit 223b compensate the rising edge and falling edge of the signal input to the external component 230 according to the counting results obtained from the first register 226a and the second register 226b, thereby canceling The signal is distorted due to the external components 230 .

Referring to FIG. 4 , the first error compensation unit 223a obtains a compensated first compensation signal Sc1 according to the counting result of the first register 226a and the input signal S, and the first compensation signal Sc1 represents a compensated rising edge signal. The second error compensation unit 223b obtains a compensated second compensation signal Sc2 according to the counting result of the second register 226b and the input signal S, and the second compensation signal Sc2 represents a compensated falling edge signal. When the rising edge signal of the first compensation signal Sc1 is sent to the external component 230 through the output control unit 224, the external component 230 is turned on; when the falling edge signal of the second compensation signal Sc2 is sent to the external component through the output control unit 224 After 230, the external component 230 is turned off. The output control unit 224 controls the first compensation signal Sc1 and the second compensation signal Sc2 to be connected to the external component 230 in turn, and accordingly, the external component 230 is turned on or off.

FIG. 5 is a schematic diagram of signals after being compensated by an error compensation circuit according to an embodiment of the present invention. FIG. 5 shows the output signal Sext, the control signal Sc, the gate current (Gate current) of the external device 230 and the MOS current (MOS current) of the external device 230 in order from top to bottom. Wherein, the output signal Sext is the voltage signal (VR) obtained from the connection between the resistor 231 and the external component 230 , and the control signal Sc is the gate voltage (Gatevoltage) measured from the gate of the external component 230 . As shown in FIG. 5, after the error compensation circuit 220 of the present invention, the rising and falling edges of the gate voltage of the external element 230 and the MOS current are almost vertical, and the duty cycle of the two signals has reached an ideal state. Below 50%, no offset occurs. Therefore, the error compensation circuit 220 of the present invention compensates the rising edge and falling edge signals respectively.

In some embodiments, the battery impedance measurement circuit is provided in an integrated circuit chip, and the error compensation circuit of the present invention is suitable for being integrated in the integrated circuit chip including the battery impedance measurement circuit.

Referring to FIG. 3 , the battery impedance measurement system 200 of the present invention further includes an additional delay unit T1. The additional delay unit T1 is used to delay the input signal S generated by the signal generator 210 to obtain a delayed signal S2 , and input the delayed signal S2 into the impedance measurement circuit 250 . The processing circuit 260 may include an analog-to-digital conversion unit ADC, a delay unit, a CIC filter (Cascaded integrator-comb filter, integral-comb cascade filter), etc., and the output signal Sext through error compensation is processed to obtain the processed The output signal Sext1.

As shown in FIG. 1 and FIG. 3, the impedance measurement circuit 250 can be the measurement circuit 120 shown in FIG. 1, which is a kind of FFT/DFT circuit, including modules such as multipliers, and can be based on the delay signal S2 and the processed The output signal Sext1 of the external battery 240 to be measured is input into the impedance measuring circuit 250 to calculate the values of the real part (Zreal) and the imaginary part (Zimag) of the impedance Z of the external battery 240 to be measured.

In addition, it should be noted that referring to FIG. 1 , the battery impedance measurement system 200 of the present invention may further include a corresponding analog-to-digital conversion unit ADC, a digital-to-analog conversion unit DAC, and the like. Those skilled in the art can add other electronic components, functional modules, etc. on the basis of the idea of the present invention.

The basic concepts have been described above, and obviously, for those skilled in the art, the disclosure of the above-mentioned embodiments of the invention is only used as an example, and does not constitute a limitation to the present application. Although not expressly stated here, various modifications, improvements and amendments to this application may be made by those skilled in the art. Such modifications, improvements, and amendments are suggested in this application, so such modifications, improvements, and amendments still belong to the spirit and scope of the exemplary embodiments of this application.

Meanwhile, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and/or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that two or more references to "an embodiment" or "an embodiment" or "an alternative embodiment" in different places in this specification do not necessarily refer to the same embodiment . In addition, certain features, structures or characteristics of one or more embodiments of the present application may be properly combined.

Although the present invention has been described with reference to the current specific embodiments, those of ordinary skill in the art should recognize that the above embodiments are only used to illustrate the present invention, and other modifications can be made without departing from the spirit of the present invention. Various equivalent changes or substitutions, therefore, as long as the changes and modifications to the above embodiments are within the spirit of the present invention, they will all fall within the scope of the claims of the present application.

Claims (11)

1. An error compensation circuit, wherein an input signal of the error compensation circuit has a rising edge and a falling edge, and the error compensation circuit is connected to an external component for compensating an error caused by the external component, the error compensation circuit comprising: the device comprises a delay unit, a first error detection unit, a second error detection unit, a first error compensation unit, a second error compensation unit and an output control unit; wherein,

the delay unit is used for delaying the input signal for a fixed time to generate a first delay signal;

the first error detection unit is used for comparing the first delay signal with an output signal of the external component to detect a rising edge error of the output signal, and the second error detection unit is used for comparing the first delay signal with the output signal of the external component to detect a falling edge error of the output signal;

the first error compensation unit is used for generating a first compensation signal according to the rising edge error and the input signal, and the second error compensation unit is used for generating a second compensation signal according to the falling edge error and the input signal; and

the output control unit is used for controlling the error compensation circuit to output the first compensation signal or the second compensation signal.

2. The circuit of claim 1, further comprising a first counting unit to count rising edge errors detected by the first error detection unit and a second counting unit to count falling edge errors detected by the second error detection unit.

3. The circuit of claim 2, wherein the first counting unit includes a first register for registering the number of rising edge errors and the second counting unit includes a second register for registering the number of falling edge errors.

4. The circuit of claim 2, wherein the first counting unit sends the number of rising edge errors to the first error compensation unit when the number of rising edge errors reaches a first threshold; and when the number of the falling edge errors reaches a second threshold value, the second counting unit is used for sending the number of the falling edge errors to the second error compensation unit.

5. The circuit of claim 1, wherein the first error detection unit and/or the second error detection unit is a phase frequency detector.

6. The circuit of claim 1, wherein the fixed time delay is 2 microseconds.

7. The circuit of claim 1, wherein the output control unit is a switching circuit.

8. The circuit of claim 1, wherein the input signal is a square wave.

9. The circuit of claim 1, wherein the output signal is connected to an external battery and is used to measure an impedance of the external battery.

10. The circuit of claim 1, wherein the error compensation circuit is adapted to be integrated in a battery impedance measurement circuit.

11. A battery impedance measurement system comprising an error compensation circuit according to any one of claims 1 to 10.

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