CN113820578B - Method for measuring semiconductor device - Google Patents
Method for measuring semiconductor device Download PDFInfo
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- CN113820578B CN113820578B CN202111073814.4A CN202111073814A CN113820578B CN 113820578 B CN113820578 B CN 113820578B CN 202111073814 A CN202111073814 A CN 202111073814A CN 113820578 B CN113820578 B CN 113820578B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 180
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000003917 TEM image Methods 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000010884 ion-beam technique Methods 0.000 claims abstract description 26
- 238000005259 measurement Methods 0.000 claims description 23
- 239000003550 marker Substances 0.000 claims description 9
- 238000012163 sequencing technique Methods 0.000 claims 1
- 230000005540 biological transmission Effects 0.000 abstract description 13
- 230000000875 corresponding effect Effects 0.000 description 21
- 239000000463 material Substances 0.000 description 8
- 239000007787 solid Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000004080 punching Methods 0.000 description 5
- 238000004627 transmission electron microscopy Methods 0.000 description 5
- 238000004458 analytical method Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000012512 characterization method Methods 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- -1 gallium ions Chemical class 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910001338 liquidmetal Inorganic materials 0.000 description 2
- 238000001000 micrograph Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000013523 data management Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2648—Characterising semiconductor materials
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/02—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by transmitting the radiation through the material
- G01N23/04—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by transmitting the radiation through the material and forming images of the material
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/20—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by using diffraction of the radiation by the materials, e.g. for investigating crystal structure; by using scattering of the radiation by the materials, e.g. for investigating non-crystalline materials; by using reflection of the radiation by the materials
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/22—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material
- G01N23/225—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material using electron or ion
- G01N23/2251—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material using electron or ion using incident electron beams, e.g. scanning electron microscopy [SEM]
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Analytical Chemistry (AREA)
- Biochemistry (AREA)
- General Health & Medical Sciences (AREA)
- Immunology (AREA)
- Pathology (AREA)
- Crystallography & Structural Chemistry (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention provides a measuring method of a semiconductor device, which comprises the following steps: providing a semiconductor device, wherein the semiconductor device comprises a substrate and a semiconductor structure positioned on the substrate; generating a mark map in the image processing software according to the reference mark setting of the semiconductor structure; simultaneously generating a plurality of physical marks on the semiconductor structure according to the mark pattern using the focused ion beam; the TEM image of the semiconductor structure is obtained by using a transmission electron microscope, and the dimension of the semiconductor structure is measured according to a plurality of entity marks.
Description
[ field of technology ]
The invention relates to the technical field of semiconductors, in particular to a measuring method of a semiconductor device.
[ background Art ]
The three-dimensional memory (3D NAND Flash) is widely applied to computers, solid state disks and electronic equipment due to the advantages of high memory density, high programming speed and the like. Three-dimensional memory increases memory capacity by stacking memory cells (also referred to as data cells). The core region (core) of the three-dimensional memory is formed with a stack structure (NO stack) comprising alternately stacked gate layers and insulating layers, and an accurate characterization of the stack structure of the core region is critical to the performance of the final device. With the continuous expansion of the storage capacity, the stacking of the stacked structure tends to be higher and higher. Thus, precise marking and measurement of the number of layers of the stacked structure becomes more and more difficult.
Heretofore, the stacking structure is marked by manpower in STEM, however, as the number of layers of the stacking structure is higher, the manual marking is particularly time-consuming and labor-consuming, and the cost is higher. Therefore, there is a need to develop a method for automatically and rapidly marking a stacked structure.
[ invention ]
The invention aims to provide a measuring method of a semiconductor device, by which a semiconductor structure can be automatically and rapidly marked, so that the labor time is saved and the cost is reduced.
In order to solve the above problems, the present invention provides a method for measuring a semiconductor device, comprising: providing a semiconductor device, wherein the semiconductor device comprises a substrate and a semiconductor structure positioned on the substrate; generating a mark map in the image processing software according to the reference mark setting of the semiconductor structure; simultaneously generating a plurality of physical marks on the semiconductor structure according to the mark pattern using the focused ion beam; a TEM image of the semiconductor structure is acquired using a transmission electron microscope and dimensional measurements of the semiconductor structure are made based on the plurality of physical marks.
Wherein the semiconductor structure includes sacrificial layers and insulating layers alternately stacked along a first longitudinal direction perpendicular to the main surface of the substrate.
Wherein the semiconductor structure includes gate layers and insulating layers alternately stacked along a first longitudinal direction perpendicular to a main surface of the substrate.
Wherein, before the dimension measurement is performed on the semiconductor structure, the method further comprises:
the number of gate layers or insulating layers of the semiconductor structure is ordered.
The marking graph comprises a plurality of marking points which are distributed at equal intervals in the vertical direction.
Wherein the number of the plurality of mark points corresponds to the number of layers of the semiconductor structure.
Wherein a plurality of physical marks are simultaneously formed in a first lateral direction parallel to the major surface of the substrate in accordance with the mark pattern using a focused ion beam.
Wherein the physical mark comprises holes, and the size range of the holes comprises 15-25nm.
The pixel size of the semiconductor structure selected by size measurement corresponds to the pixel size of the TEM image.
And selecting a position with a horizontal distance range of 100-200nm from the corresponding physical mark to measure the dimension of the semiconductor structure.
The beneficial effects of the invention are as follows: unlike the prior art, the invention provides a method for measuring a semiconductor device, which comprises the following steps: providing a semiconductor device, wherein the semiconductor device comprises a substrate and a semiconductor structure positioned on the substrate; generating a mark map in the image processing software according to the reference mark setting of the semiconductor structure; simultaneously generating a plurality of physical marks on the semiconductor structure according to the mark pattern using the focused ion beam; the TEM image of the semiconductor structure is obtained by using a transmission electron microscope, and the dimension of the semiconductor structure is measured according to a plurality of entity marks.
[ description of the drawings ]
FIG. 1a is a TEM image of the entire stacked structure of the prior art;
FIG. 1b is a TEM image of a portion of a prior art laminate structure with marked points;
FIG. 2 is a flow chart of a method for measuring a semiconductor device according to an embodiment of the invention;
FIG. 3a is an image of a mark pattern formed in one embodiment of the present invention;
FIG. 3b is an image of a plurality of physical marks formed in accordance with one embodiment of the present invention;
FIG. 3c is an image of a semiconductor structure prior to forming a plurality of physical marks in accordance with one embodiment of the present invention;
FIG. 3d is an image of a semiconductor structure after a plurality of physical marks are formed in accordance with one embodiment of the present invention;
FIG. 4a is an overall TEM image of a semiconductor structure at 400ms of FIB operation time, according to one embodiment of the present invention;
FIG. 4b is a partial TEM image of the semiconductor structure of FIG. 4 a;
FIG. 4c is another partial TEM image of the semiconductor structure of FIG. 4 a;
FIG. 5 is a graph comparing the thickness of a sacrificial layer obtained when the FIB has an on time of 400ms with the thickness of a sacrificial layer obtained using STEM marks;
FIG. 6 is a graph comparing the thickness of an insulating layer obtained when the FIB has an on time of 400ms with the thickness of a sacrificial layer obtained using STEM marks;
FIG. 7a is a partial TEM image of a semiconductor structure at an FIB working time of 2s according to one embodiment of the present invention;
FIG. 7b is a partial TEM image of the semiconductor structure of FIG. 7 a;
FIG. 7c is another partial TEM image of the semiconductor structure of FIG. 7 a;
FIG. 8 is a graph of data for thickness of sacrificial layer obtained with an on time of 2s for the FIB;
fig. 9 is a graph of data of the thickness of the insulating layer obtained when the FIB has an on time of 2s.
[ detailed description ] of the invention
The invention is described in further detail below with reference to the drawings and examples. It is specifically noted that the following examples are only for illustrating the present invention, but do not limit the scope of the present invention. Likewise, the following examples are only some, but not all, of the examples of the present invention, and all other examples, which a person of ordinary skill in the art would obtain without making any inventive effort, are within the scope of the present invention.
In addition, directional terms such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., as used herein, refer only to the directions of the attached drawings. Accordingly, directional terminology is used to describe and understand the invention and is not limiting of the invention. In the various drawings, like elements are designated by like reference numerals. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings.
Three-dimensional memory (3D NAND Flash) is provided with increased storage capacity by stacking memory cells (also referred to as data cells). The core region (core) of the three-dimensional memory is formed with a stack structure (NO stack) comprising alternately stacked gate layers and insulating layers, and an accurate characterization of the stack structure of the core region is critical to the performance of the final device. As shown in fig. 1a, a TEM image of a prior art stacked structure is obtained by Transmission Electron Microscopy (TEM), and then the dimensions of the stacked structure are measured by image processing software, such as DM3 (Digital Micrograph, a software for transmission electron microscopy data acquisition and analysis).
The marking and measuring process for the stacked structure in the prior art specifically includes: firstly, punching and marking a grid layer (also can be an insulating layer) by using a transmission scanning electron microscope (STEM), and marking the number of layers of the corresponding grid layer beside a marking hole after punching the marking hole, for example, as shown in fig. 1b, the number of layers of the corresponding grid layer is 21; then, selecting a gate layer with a certain number of layers (such as 5 layers), continuously punching and marking the gate layer by using STEM, marking the number of layers of the corresponding gate layer beside a marking hole after punching the marking hole, for example, as shown in fig. 1b, the number of layers of the corresponding gate layer is 26; then repeatedly carrying out punching marking on the grid layers by using STEM and marking the layer number of the corresponding grid layer beside the marking hole for a plurality of times, and fully marking the layer numbers of all the grid layers of the stacked structure; and finally, measuring the size of the stacked structure according to the number of layers of the grid electrode layer. However, with the continuous expansion of the storage capacity of the three-dimensional memory, the number of stacked layers of the stacked structure tends to be higher, so that the adoption of the manual marking is particularly time-consuming and labor-consuming, and the cost is also higher.
In view of this, as shown in fig. 2, the present invention provides a flow chart of a method for measuring a semiconductor device, and the specific flow chart may include the following steps with reference to the images shown in fig. 3a to 3 d:
s101, step: a semiconductor device is provided that includes a substrate and a semiconductor structure located on the substrate.
Wherein the semiconductor structure includes sacrificial layers and insulating layers alternately stacked along a first longitudinal direction perpendicular to the main surface of the substrate.
In particular, the semiconductor structure may comprise sacrificial layers and insulating layers alternately stacked along a first longitudinal direction perpendicular to the main surface of the substrate, wherein the insulating layers are used to separate the plurality of sacrificial layers, and the material of the insulating layers may be made of an oxide such as silicon oxide (SiO 2 ) While the material of the sacrificial layer may be composed of a nitride, such as silicon nitride (SiN). Since the material of the sacrificial layer is mostly nitride, it is advantageous to simultaneously form a stacked structure of a plurality of sacrificial layers and a plurality of insulating layers alternately stacked, and thus, a semiconductor structure including the sacrificial layers and the insulating layers alternately stacked in a first longitudinal direction perpendicular to the main surface of the substrate can be formed by a deposition process.
Wherein in a variation, the semiconductor structure includes gate layers and insulating layers alternately stacked along a first longitudinal direction perpendicular to the major surface of the substrate.
Specifically, the semiconductor device includes a substrate and a semiconductor structure on the substrate, wherein the substrate is a semiconductor material, and may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC), or the like, or other materials, without being particularly limited, as a basis for forming the semiconductor device. While the semiconductor structure may include gate layers alternately stacked in a first longitudinal direction perpendicular to the main surface of the substrate and insulating layers for separating the plurality of gate layers, the material of the insulating layers may be made of an oxide such as silicon oxide (SiO 2 ) And the material of the gate layer may be composed of a conductive material such as tungsten (W). Because the number of layers of the semiconductor structure is very large and the alternately stacked gate layers and insulating layers cannot be directly formed at one time, the alternately stacked sacrificial layers and insulating layers need to be formed at one time by adopting a deposition process, and then the sacrificial layers are removed by adopting a wet etching processAnd finally, forming a gate layer at the original sacrificial layer, thereby forming alternately stacked gate layers and stacked layers. As can be seen from the above, the semiconductor structure may include gate layers and insulating layers alternately stacked and may include sacrificial layers and insulating layers alternately stacked according to the progress of the process flow of the semiconductor structure.
Wherein, after the step S101, further comprising:
preparing the object to be tested for the semiconductor device.
Specifically, at the execution of S101 step: after providing a semiconductor device comprising a substrate and a semiconductor structure on the substrate, the semiconductor device is a sample to be tested that has reached the sample preparation standard, however, there may also be a need to prepare the semiconductor device for the sample to be tested when performing subsequent steps, such as when using a focused ion beam system or a transmission scanning electron microscope, e.g. cutting, thinning, polishing, etc. the semiconductor device is required to reach the sample preparation standard in practical situations.
S102, step: a signature is generated in the image processing software based on the reference signature settings of the semiconductor structure.
Specifically, after the semiconductor device is formed by performing step S101, and the sample to be tested, which can be used for performing the following steps, is formed, a signature can be generated in an image processing software according to the reference signature setting of the semiconductor structure, where the image processing software can be DM3 (Digital Micrograph, which is a software for data acquisition and analysis of a transmission electron microscope), and DM3 has various functions of image acquisition, image processing and analysis, data management and report printing.
Note that the pattern of the marks set according to the reference marks of the semiconductor structure may be equally spaced or non-equally spaced, and the pattern of the marks is not particularly limited.
The marking graph comprises a plurality of marking points which are distributed at equal intervals in the vertical direction.
Specifically, as shown in fig. 3a, in an embodiment of the present invention, the image forming a marker may be a plurality of marker points (such as a plurality of white dots shown in fig. 3 a) respectively at equal intervals in a vertical direction, and the plurality of marker points may be formed by setting by the image processing software DM3, where parameters such as positions, spacing distances, and the like of the plurality of marker points may be set by DM3 to form a plurality of marker points as required.
Wherein, before the dimension measurement is performed on the semiconductor structure, the method further comprises:
the number of gate layers or insulating layers of the semiconductor structure is ordered.
Specifically, by setting the reference mark of the semiconductor structure, a mark graph comprising a plurality of mark points distributed at equal intervals is generated in the image processing software, which is favorable for carrying out layer number sequence on the semiconductor structure with a plurality of layer numbers, and the layer number sequence is used as a reference standard, which is favorable for better measuring the semiconductor structure, so that the problem that the same layer number is repeatedly measured or measured data does not correspond to the layer number can be effectively avoided.
Wherein the number of the plurality of mark points corresponds to the number of layers of the semiconductor structure.
Specifically, as can be seen from the foregoing, the semiconductor structure may be alternatively stacked gate layers and insulating layers, or alternatively stacked sacrificial layers and insulating layers, and the structure of the semiconductor device is formed by alternately stacking two different film layers, no matter whether the semiconductor structure includes a gate layer or an insulating layer, with the continuous expansion of the storage capacity of the three-dimensional memory, the number of layers of the alternatively stacked two different film layers tends to be higher and higher, for example, the number of layers of the gate layer or the sacrificial layer of the semiconductor structure may reach 196 layers or more, and at this time, if the number of marking points is irregular, the number of layers of the semiconductor structure is easy to be disordered, and a method of forming a plurality of marking points by corresponding the number of marking points to the number of layers of the semiconductor structure may be adopted. For example, assuming that the semiconductor structure is formed by alternately stacking gate layers and insulating layers, the number of gate layers is 32, each 4 layers may be selected to mark a mark point, and 8 equally spaced mark points may be selected. Note that the number of the plurality of mark points corresponds to the number of layers of the semiconductor structure means that the number of mark points is positively correlated with the number of layers of the semiconductor structure, that is, the higher the number of layers of the semiconductor structure is, the greater the number of mark points in the generated mark map is. The number of marker points may be set with reference to the number of marker points used for an existing TEM image having the same gate layer or insulating layer as the semiconductor structure.
S103, step: a plurality of physical marks are simultaneously generated on the semiconductor structure according to the mark pattern using a focused ion beam.
Specifically, as the integration level of the three-dimensional memory is continuously improved, the feature size is continuously reduced, and FIB (focused ion beam) technology has become an important technology in semiconductor manufacturing, and is widely applied to aspects such as photomask repairing, defect detection analysis of the three-dimensional memory, preparation of a thin sheet sample of a TEM (transmission electron microscope), scanning electron microscope, and the like. A focused ion beam may be used to form a plurality of physical marks on a semiconductor structure as shown in fig. 3b, according to the mark pattern in fig. 3 a. As can be seen from the above, the process of forming the physical mark in the prior art needs to use the high-intensity electron beam under the transmission scanning electron microscope (STEM) to punch the stacked structure, and then switch to the transmission scanning electron microscope to perform the image capturing, so as to facilitate the number of marking layers of the subsequent stacked structure. Therefore, the method in the prior art is equivalent to representing the sample twice under the TEM, and is time-consuming and labor-consuming, the semiconductor structure is automatically marked by making a mark map in advance through image processing software, then a plurality of entity marks are generated on the semiconductor structure according to the mark map by utilizing the FIB, and the film layer of the semiconductor structure can be automatically marked by utilizing the mark map made in advance, so that the image can be directly taken according to the entity marks in the TEM, the time is saved, the labor is saved, and the cost is greatly reduced.
In particular, a focused ion beam may be formed using a FIB system to form a plurality of physical marks on a semiconductor structure. The FIB system can comprise an ion source, an external electric field, a negative electric field, a diaphragm, a primary electrostatic lens, a primary octagon deflector, an iris diaphragm, a blanking deflector blanking diaphragm, a secondary octagon deflector, a secondary electrostatic lens, a microchannel plate detector and the like. The ion source generates a liquid metal ion beam, usually gallium ions, which has the advantages of low melting point, good stability and the like. The generated liquid metal ions are converged into an ultrafine tip through an applied electric field, and evaporated and separated from materials are formed on the surface of the metal ions in a liquid state to form ion beam current; by applying a negative electric field, it is pumped out. The liquid ion source has a minimum threshold that causes it to develop a stable emission current. The minimum current for stable emission of gallium ions was 0.5uA. Typically, the operating voltage required to bombard the sample surface by a focused ion beam is in the range of 5KV-30KV, the operating current is in the range of 1pA-20nA, and when the operating current is selected to be 1pA, the minimum beam spot diameter is less than 5nm. Meanwhile, the FIB system has the characteristics of high precision and good stability, has good performance of pollution-free and good vibration isolation effect under vacuum, and can realize the processing and on-line observation of the focused ion beam. Thus, by focusing the ion beam, more precise physical marks can be formed on the semiconductor structure.
Wherein a plurality of physical marks are simultaneously formed in a first lateral direction parallel to the major surface of the substrate in accordance with the mark pattern using a focused ion beam.
Specifically, the parameters of the FIB system can be controlled to control the depth, size and other dimensions of the formed physical mark. Preferably, when e-beam0 ° (i.e., the direction of the focused ion beam is not changed, that is, the direction of the focused ion beam is formed along a first lateral direction parallel to the major surface of the substrate) is selected in the FIB system, a plurality of dense and well-defined physical marks may be formed on the semiconductor structure by the focused ion beam. Wherein, as shown in fig. 3c, in order to select e-beam0 ° in the FIB system to form an image of the whole structure of the semiconductor structure before the plurality of physical marks are formed on the semiconductor structure, at this time, the semiconductor structure is not bent, as shown in fig. 3d, in order to select e-beam0 ° in the FIB system to form an image of the whole structure of the semiconductor structure after the plurality of physical marks are formed on the semiconductor structure, it is known that the plurality of physical marks are formed on the semiconductor structure by focusing the ion beam, and the bending of the semiconductor structure is not caused, that is, the feasibility of forming the plurality of physical marks on the semiconductor structure by focusing the ion beam is verified.
Wherein the physical mark comprises holes, and the size range of the holes comprises 15-25nm.
Specifically, the shape of the physical mark is not particularly limited, and the physical mark may be any pattern that facilitates marking, such as a circle, a square, or other shapes, as long as it can be realized as a reference for subsequent measurement. Preferably, for convenience of forming by focusing the ion beam, the physical mark may be a hole, and as it is known from the above, the parameters of the FIB system may be controlled to control the depth and size of the formed physical mark, and when the working current is selected to be 1pA, the minimum beam spot diameter is less than 5nm, so that the hole with the size range of 15-25nm may be formed by controlling the parameters of the FIB system. When the size of the hole is too large, the film layer of the semiconductor structure is easily damaged, and when the size of the hole is too small, the hole and the mark are not easily found, preferably, when the size of the hole, such as the diameter of the hole, is 20nm, the mark and the subsequent measurement are facilitated on the basis that the film layer of the semiconductor structure is not affected.
Specifically, on the premise of ensuring that the semiconductor device is not bent, the parameters of a proper FIB system can be selected, so that uniform and clear entity marks are obtained. It can be seen from the above that the parameters of the FIB system can be controlled to control the depth and the size of the formed physical mark, the working voltage of the FIB system ranges from 5KV to 30KV, the working current ranges from 1pA to 20nA, and the working time of the FIB system can be adjusted, so that the size and the depth of the formed hole can be controlled by controlling the working time, the working voltage and the working current of the FIB. Typically, a fixed operating voltage, such as 30KV, is selected to control the size and depth of the holes formed by adjusting the operating current and operating time. In order to form holes of about 20nm, the FIB system preferably has an operating current of 7pA and an operating time in the range of 400ms-2s, wherein the operating time range includes 400ms and 2s.
In addition, it should be noted that, generally, a fixed working voltage of the FIB system is selected, but the working voltage of the FIB system is not particularly limited, and may be any value between 5KV and 30KV, and the working voltage may be adjusted according to the size and depth of the hole formed in actual need.
S104, step: a TEM image of the semiconductor structure is acquired using a transmission electron microscope and dimensional measurements of the semiconductor structure are made based on the plurality of physical marks.
Specifically, a TEM image of a semiconductor structure may be obtained by a transmission electron microscope, and a dimension measurement may be performed on the semiconductor structure according to a plurality of physical marks, for example, as shown in fig. 4a, the TEM image is an overall TEM image of the semiconductor structure when the working time in the FIB system is 400ms, at this time, two areas are selected from the semiconductor structure, and a corresponding partial TEM image of the semiconductor structure shown in fig. 4b and another partial TEM image of the semiconductor structure shown in fig. 4c are obtained, where fig. 4b and fig. 4c correspond to areas with different layers, respectively, and the structures shown in the two areas are identical, and only the number of layers marked in the drawing is different. When the operating voltage in the FIB system is 30KV, the operating current is 7pA and the operating time is 400ms, as shown in fig. 4b and fig. 4c, a plurality of sparse and bright spots are formed on the gate layer of the semiconductor structure by focusing the ion beam, so that no damage to the sample and expansion of the measurable range are ensured.
Specifically, from the above, local TEM images of semiconductor structures with different layer numbers can be obtained, and similarly, it can be known that local TEM images of semiconductor structures with different layer number ranges can be obtained multiple times, so as to obtain TEM images of all film layers in the semiconductor structure, and then the thickness of all film layers in the semiconductor structure can be measured by measuring software.
When the working voltage in the FIB system is 30KV, the working current is 7pA and the working time is 400ms, TEM images of all film layers in the semiconductor structure are obtained, then the thicknesses of the sacrificial layer (i.e. silicon nitride, ntride) and the insulating layer (i.e. silicon Oxide, oxide) in the semiconductor structure from layer 1 to layer 15 are measured by measuring software, and the method of forming entity marks by STEM in the prior art is adopted, then the thicknesses of the sacrificial layer and the insulating layer (i.e. silicon Oxide, oxide) in the same semiconductor structure from layer 1 to layer 15 are measured by measuring software, and the collected partial data can be shown in the following fig. 5 and fig. 6 respectively.
The abscissa of fig. 5 shows the number of sacrificial layers of the semiconductor device, the ordinate shows the thickness (in nm) of the corresponding sacrificial layer, the thinner black curve with solid dots is the measurement data obtained by STEM forming the solid mark (i.e., STEM mark), and the thicker gray curve with hollow dots is the measurement data obtained by FIB forming the solid mark (i.e., FIB mark).
The abscissa of fig. 6 shows the number of insulating layers of the semiconductor device, the ordinate shows the thickness (in nm) of the corresponding insulating layer, the thin black curve with solid dots is the measurement data obtained by STEM marking, and the thick gray curve with hollow dots is the measurement data obtained by FIB marking.
Wherein the data of fig. 5 and 6 are collated, the data obtained are shown in table 1 below:
TABLE 1
As can be seen from fig. 5, 6 and table 1, the relative error between the FIB-marked measurement result and STEM-marked measurement result is only 0.1-0.2%, ensuring the FIB-marked measurement accuracy. Compared with STEM marks in the prior art, the adoption of the FIB marks can save the expensive cost of using a scanning projection microscope, and meanwhile, the adoption of the FIB marks can automatically and quickly mark the semiconductor structure, thereby saving the labor time.
And selecting a position with a horizontal distance range of 100-200nm from the corresponding physical mark to measure the dimension of the semiconductor structure.
Specifically, a TEM image of the semiconductor structure may be obtained by a transmission electron microscope, and a dimension measurement may be performed on the semiconductor structure according to a plurality of physical marks, for example, as shown in fig. 7a, the whole TEM image of the semiconductor structure when the working time is 2s in the FIB system is shown in fig. 7a, at this time, two regions are selected from the semiconductor structure, and a corresponding partial TEM image of the semiconductor structure shown in fig. 7b and another partial TEM image of the semiconductor structure shown in fig. 7c are obtained, where fig. 7b and 7c respectively correspond to regions with the same layer number range (for example, 54 layers to 64 layers) and different positions. When the operating voltage in the FIB system is 30KV, the operating current 7pA and the operating time is 2s, a plurality of dense and well-defined holes are formed in the gate layer of the semiconductor structure by focusing the ion beam as shown in fig. 7b and 7 c.
Specifically, from the above, local TEM images of the semiconductor structure in the same layer number range and at different positions can be obtained, and similarly, local TEM images of the semiconductor structure in the same layer number range and at different positions can be obtained multiple times, so as to obtain TEM images of the semiconductor structure in all positions in the same layer number range, and then the thickness of all film layers in the same layer number and at different positions in the semiconductor structure can be measured by measuring software.
When the working voltage in the FIB system is 30KV, the working current is 7pA and the working time is 2s, obtaining TEM images of different positions in the same layer number range in the semiconductor structure, measuring the film thicknesses of the measuring positions of the sacrificial layer and the insulating layer in the semiconductor structure and the corresponding physical marks or spots within the range of-100 nm to 355nm through measuring software, wherein the positive and negative of the distance values only represent the difference of the relative positions, for example, -100nm and 100nm refer to being respectively positioned on the left side and the right side of the spots, and the subsequent same is repeated, and the collected partial data can be respectively shown in the following fig. 8 and 9.
As shown in fig. 8, the result of FIB mark measurement is that the abscissa is the distance value (in nm) between the measured position of the sacrificial layer and the corresponding spot, and the ordinate is the thickness (in nm) of the corresponding sacrificial layer.
As shown in fig. 9, the result of FIB mark measurement is that the abscissa is the distance value (in nm) between the measured position of the insulating layer and the corresponding spot, and the ordinate is the thickness (in nm) of the corresponding sacrificial layer.
By collating the data of fig. 8 and 9, the average value of the sacrificial layer thickness was 28.23nm, the standard deviation (std) was 0.06, the error Rate (RSD) of STEM marking was 0.5% with the prior art, the average value of the insulating layer thickness was 19.04nm, the standard deviation (std) was 0.06, the error Rate (RSD) of STEM marking was 0.9% with the prior art, and the measurement accuracy of FIB marking was ensured. As can be seen from fig. 8 and 9, it is preferable to select a position with a horizontal distance ranging from 100nm to 200nm from the corresponding physical mark to measure the dimension of the semiconductor structure, because the curves at the corresponding positions in the interval are denser and have a smaller fluctuation range, that is, the measured values corresponding to the interval are more accurate, as shown in fig. 8 and 9. Furthermore, it should be noted that 100-200nm includes the distance to the left and right sides of the solid mark or spot, i.e. the corresponding ranges should be 100 to 200nm and-200 to-100 nm. Compared with STEM marks in the prior art, the adoption of the FIB marks can save the expensive cost of using a scanning projection microscope, and meanwhile, the adoption of the FIB marks can automatically and quickly mark the semiconductor structure, thereby saving the labor time.
The pixel size of the semiconductor structure selected by size measurement corresponds to the pixel size of the TEM image.
Specifically, when the TEM image of the semiconductor structure is measured, the image processing software DM3 is generally used, for example, when the TEM image of the semiconductor structure is turned on by using the image processing software DM3, the pixel size to be measured is set according to the pixel size (pixel size) of the TEM image of the semiconductor structure, and when the pixel size of the TEM image of the semiconductor structure is consistent with the pixel size selected for size measurement, the actual value of the semiconductor structure is measured by the image processing software DM 3. In general, in order to measure the true value of the semiconductor structure size, a pixel size that corresponds to the TEM image needs to be selected, where the correspondence generally refers to the pixel size that corresponds to the TEM image. Furthermore, when it is not necessary to obtain a true value of the semiconductor structure size, only one relative value is needed, the correspondence here may be a pixel size proportional to the TEM image.
Unlike the prior art, the method for measuring a semiconductor device in this embodiment includes: providing a semiconductor device, wherein the semiconductor device comprises a substrate and a semiconductor structure positioned on the substrate; generating a mark map in the image processing software according to the reference mark setting of the semiconductor structure; simultaneously generating a plurality of physical marks on the semiconductor structure according to the mark pattern using the focused ion beam; the TEM image of the semiconductor structure is obtained by using a transmission electron microscope, and the dimension of the semiconductor structure is measured according to a plurality of entity marks.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (10)
1. A method for measuring a semiconductor device, comprising:
providing a semiconductor device, wherein the semiconductor device comprises a substrate and a semiconductor structure positioned on the substrate;
generating a mark map in image processing software according to the reference mark setting of the semiconductor structure;
simultaneously generating a plurality of physical marks on the semiconductor structure according to the mark map using a focused ion beam;
respectively selecting two areas from the semiconductor structure, and acquiring two local TEM images of the semiconductor structure, wherein the two local TEM images respectively correspond to areas with different layers, the two areas are consistent in structure, and the marked layers in the two TEM images are different;
local TEM images of the semiconductor structure with different layer numbers are obtained, local TEM images of the semiconductor structure with different layer number ranges are obtained for multiple times, TEM images of all film layers in the semiconductor structure are obtained, and then the thickness of all film layers in the semiconductor structure is measured through measuring software.
2. The method of measuring a semiconductor device according to claim 1, wherein the semiconductor structure includes sacrificial layers and insulating layers alternately stacked along a first longitudinal direction perpendicular to a main surface of the substrate.
3. The method of measuring a semiconductor device of claim 1, wherein the semiconductor structure comprises gate layers and insulating layers alternately stacked along a first longitudinal direction perpendicular to a major surface of the substrate.
4. The method of claim 3, further comprising, prior to said dimension measuring said semiconductor structure:
and sequencing the number of layers of the gate layer or the insulating layer of the semiconductor structure.
5. The method of claim 1, wherein the marker pattern comprises a plurality of marker points equally spaced in a vertical direction.
6. The method of claim 5, wherein the number of the plurality of mark points corresponds to the number of layers of the semiconductor structure.
7. The method of claim 1, wherein the plurality of physical marks are formed simultaneously along a first lateral direction parallel to a major surface of the substrate according to the mark pattern using a focused ion beam.
8. The method of claim 1, wherein the physical mark comprises a hole, and wherein the hole has a size ranging from 15 nm to 25nm.
9. The method of claim 1, wherein the selected pixel size for dimension measurement of the semiconductor structure corresponds to the selected pixel size of the TEM image.
10. The method of claim 1, wherein the semiconductor structure is sized by selecting a position having a horizontal distance ranging from 100nm to 200nm from the corresponding physical mark.
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