CN113809049A - Radio frequency chip packaging structure with high shielding performance and isolation and packaging method - Google Patents
Radio frequency chip packaging structure with high shielding performance and isolation and packaging method Download PDFInfo
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- CN113809049A CN113809049A CN202111093457.8A CN202111093457A CN113809049A CN 113809049 A CN113809049 A CN 113809049A CN 202111093457 A CN202111093457 A CN 202111093457A CN 113809049 A CN113809049 A CN 113809049A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000002955 isolation Methods 0.000 title claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 97
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 97
- 239000010703 silicon Substances 0.000 claims abstract description 97
- 239000002184 metal Substances 0.000 claims abstract description 48
- 229910052751 metal Inorganic materials 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000003466 welding Methods 0.000 claims abstract description 20
- 239000000945 filler Substances 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims abstract description 5
- 238000002161 passivation Methods 0.000 claims description 27
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 239000000969 carrier Substances 0.000 claims description 6
- 239000003292 glue Substances 0.000 claims description 3
- 238000005476 soldering Methods 0.000 claims 2
- 238000005538 encapsulation Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000004021 metal welding Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000007789 sealing Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005672 electromagnetic field Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
- H01L25/165—Containers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
本发明涉及集成电路封装技术领域，具体涉及一种高屏蔽性和隔离度的射频芯片封装结构及封装方法，该封装结构包括上下两个正面相对设置的第一硅晶圆和第二硅晶圆，第一硅晶圆的正面设有若干个焊柱并形成有金属腔体，第二硅晶圆的正面键合有若干个射频芯片，焊柱焊接在第二硅晶圆的正面且每个射频芯片分别位于每个金属腔体内，焊柱的周围设有填充料，由此采用多个布线层与金属焊柱构成金属腔，有效实现了电磁波的屏蔽作用，并在多芯片的射频微波系统封装中，有效实现不同功能芯片之间的信号隔离；在该封装方法中，采用封装加工工艺，硅基板与硅帽的制造工艺相同，加工周期短，精度高。
The invention relates to the technical field of integrated circuit packaging, in particular to a radio frequency chip packaging structure and packaging method with high shielding and isolation. , the front of the first silicon wafer is provided with a number of welding posts and a metal cavity is formed, the front of the second silicon wafer is bonded with a number of radio frequency chips, the welding posts are welded on the front of the second silicon wafer and each The radio frequency chip is located in each metal cavity, and the filler material is arranged around the welding post. Therefore, multiple wiring layers and metal welding posts are used to form the metal cavity, which effectively realizes the shielding effect of electromagnetic waves, and can be used in the multi-chip radio frequency microwave system. In the packaging, signal isolation between different functional chips is effectively achieved; in this packaging method, the packaging processing technology is adopted, the manufacturing process of the silicon substrate and the silicon cap is the same, the processing cycle is short, and the precision is high.
Description
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a radio frequency chip packaging structure with high shielding property and isolation and a packaging method.
Background
With the increasing demand of radio frequency microsystems for electromagnetic shielding and isolation between chips in radio frequency system-in-package, and the higher demands for high integration and miniaturization of the system, the system-in-package of multiple chips becomes difficult to realize in a compact space. The packaging method with the electromagnetic shielding function and the radio frequency chip isolation degree can not only well give consideration to the performance of the radio frequency chip, but also greatly improve the integration degree of the system, so that the packaging method utilizing the packaging process to solve the isolation degree between the electromagnetic shielding of the radio frequency chip and the chip has great advantages in packaging the radio frequency front end and the radar chip.
The current mainstream electromagnetic shielding and chip isolation method is realized by constructing a plurality of metal cavities on a structural member; and placing the radio frequency chip in the metal cavity, interconnecting metals, and covering the cavity by using a metal cover plate. This solution mainly suffers from the following problems:
1. the multi-metal cavity is difficult to construct and process, the processing cost is high, and the processing precision is poor due to the mechanical processing mode, so that uncertain noise loss is brought to a system;
2. the structure integration of the metal cavity is adopted, the product volume is large, a small-sized microsystem is not easy to construct, and the secondary integration with other components is not easy.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a method for measuring the internal temperature of an integrated circuit, which aims to solve the problems of poor electromagnetic shielding performance and poor isolation in the existing radio frequency chip packaging.
In order to solve the technical problems, the technical scheme provided by the invention is as follows: the utility model provides a radio frequency chip packaging structure of high shielding nature and isolation, includes two front relative first silicon wafer and the second silicon wafer that set up about, and the front of first silicon wafer is equipped with a plurality of welding column and is formed with the metal cavity, and the front bonding of second silicon wafer has a plurality of radio frequency chip, and the welding column welding is located every metal cavity respectively at the front of second silicon wafer and every radio frequency chip, is equipped with the stopping around the welding column.
Furthermore, a first passivation layer, a first wiring layer and a second passivation layer are sequentially arranged on the front surface of the first silicon wafer, and the welding column is welded on the second passivation layer.
Furthermore, a third passivation layer, a second wiring layer, a fourth passivation layer and a fifth passivation layer are sequentially arranged on the front surface of the second silicon wafer, and a third wiring layer is arranged in the fifth passivation layer.
Further, the radio frequency chip is welded on the second silicon wafer through conductive glue.
The radio frequency chip is bonded with the second silicon wafer through a gold wire.
The packaging method of the radio frequency chip packaging structure with high shielding performance and isolation comprises the following steps:
s: providing two silicon wafer carriers, and forming a silicon cover plate and a silicon substrate on the front surfaces of the two silicon wafer carriers respectively through a wafer-level wiring process;
s: arranging a silicon cap on the silicon cover plate and forming a metal cavity, bonding a radio frequency chip on the silicon substrate, and then flip-chip-welding the silicon cap on the silicon substrate to enable each chip to be positioned in each metal cavity;
s: and filling the filler around the silicon cap to form a packaging body.
Further, in the step S, the thickness of the silicon wafer carrier is 200-900 μm, the thickness of the radio frequency chip is 50-800 μm, and the radio frequency chip is provided with Pad supporting gold wire bonding, and the diameter of the gold wire is 200-900 μm.
Furthermore, the silicon cap is a welding column, the diameter of the welding column is 100-900 μm, and the height of the welding column is 300-3000 μm.
Furthermore, the wafer-level wiring process comprises a plurality of passivation layers and metal layers which are alternately arranged, wherein the thickness of each metal layer is 2-10 mu m, and the thickness of each passivation layer is 5-20 mu m.
Furthermore, metal columns are arranged on the silicon cap, the diameter d of each metal column, the distance p between every two metal columns and the distance a between every two rows of metal holes meet the condition that p/d is less than 2, and d/a is less than 0.2.
The beneficial effect that this technical scheme brought is: 1. in the packaging structure, a plurality of wiring layers and metal welding columns form a metal cavity, so that the shielding effect of electromagnetic waves is effectively realized, and in the packaging of a multi-chip radio frequency microwave system, the signal isolation among chips with different functions is effectively realized; 2. in the packaging method, a packaging processing technology is adopted, the manufacturing process of the silicon substrate is the same as that of the silicon cap, the processing period is short, and the precision is high; 3. the wire and the implanted column are used in a silicon cap mode, so that the welding with the silicon substrate is easier, and the welding precision is high; 4. the whole structure has high strength, good sealing performance and high reliability.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a package structure according to the present invention;
FIG. 2 is a schematic diagram of a first silicon wafer carrier and silicon cap of the packaging method of the present invention;
FIG. 3 is a top view of FIG. 2;
FIG. 4 is a schematic view of a second silicon wafer carrier in the packaging method of the present invention;
FIG. 5 is a top view of FIG. 4;
FIG. 6 is a schematic diagram of a second silicon wafer carrier and an RF chip in the packaging method of the present invention;
fig. 7 is a schematic diagram of two silicon wafer carriers after being soldered in the packaging method of the present invention. Detailed description of the preferred embodimentsthe following description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, is intended to illustrate and explain the present invention and not to limit the same. As shown in fig. 1, the radio frequency chip packaging structure with high shielding performance and isolation includes a first silicon wafer 101 and a second silicon wafer 106, which are disposed opposite to each other on the upper and lower front surfaces, the front surface of the first silicon wafer 101 is sequentially provided with a first passivation layer 102, a first wiring layer 103 and a second passivation layer 104, an opening of the second passivation layer 104 is further welded with a solder column 105 to form a silicon cap structure, and the plurality of solder columns 105 together enclose a metal cavity, thereby forming a silicon cover plate. The solder columns 105, i.e. the silicon caps, have shielding and isolating functions here.
A third passivation layer 107, a second wiring layer 108, a fourth passivation layer 109 and a fifth passivation layer 111 are sequentially arranged on the front surface of the second silicon wafer 106, a third wiring layer 110 is further arranged in the fifth passivation layer 111, a plurality of radio frequency chips 113 are further welded on the front surface of the second silicon wafer 106 through conductive adhesive 112, and meanwhile, the radio frequency chips 113 are bonded with the second silicon wafer 106 through gold wires 114, so that a silicon substrate structure is formed, and Pad of the radio frequency chips 113 is interconnected with Pad of the silicon substrate.
The solder columns 105 are soldered on the front surface of the second silicon wafer 106, each rf chip 113 is exactly located in each metal cavity, and the filling material 115 is further disposed around the solder columns 105, thereby finally forming the whole package.
Through the technical scheme, the metal cavity is formed by the wiring layers and the metal welding columns, the electromagnetic wave shielding effect is effectively realized, and the signal isolation among chips with different functions can be effectively realized in the multi-chip radio frequency microwave system packaging. And the silicon cap form of wiring and planting columns on the silicon chip is adopted, so that the welding with the silicon substrate is more convenient, and the welding precision is high. The lower substrate can be designed as a microstrip line, so that the signal line and the ground line are positioned in different levels, and the silicon cap can be directly inserted into the wiring structure of the lower substrate and welded with the ground line, so that the shielding effect is better, and the leakage of electromagnetic waves is reduced. The sealing of the filler 115 can enhance the bonding strength between the silicon cap and the silicon substrate, resulting in higher package strength and better reliability.
Specifically, as shown in fig. 2 to 7, the method for packaging the rf chip package structure with high shielding and isolation includes the following steps:
s1: providing two silicon wafer carriers, and forming a silicon cover plate and a silicon substrate on the front surfaces of the two silicon wafer carriers respectively through a wafer-level wiring process;
s2: arranging a silicon cap on the silicon cover plate and forming a metal cavity, bonding a radio frequency chip on the silicon substrate, and then flip-chip welding the silicon cap to the silicon substrate to enable each chip to be positioned in the metal cavity;
s3: and filling the filler around the silicon cap to form a packaging body.
In this embodiment, the thickness of the silicon wafer carrier is 200-900 μm, the thickness of the RF chip is 50-800 μm, and the RF chip is provided with Pad supporting gold wire bonding, and the diameter of the gold wire is 15-50 μm.
In this embodiment, the silicon cap is a solder column, the diameter of the solder column is 100-900 μm, and the height is 300-3000 μm.
In this embodiment, the wafer-level wiring process includes a plurality of passivation layers and metal layers alternately arranged, the thickness of the metal layers is 2-10 μm, and the thickness of the passivation layers is 5-20 μm.
In this embodiment, be equipped with the metal post on the silicon cap, it plays the effect of shielding and isolation, and when the diameter d of metal post and the interval p of metal post to and the interval a of two rows of metal holes changed, can influence the ability of two rows of metal posts constraint electromagnetic waves, if the structural metal post interval that d and p size constitute is too big, then will have electromagnetic energy to reveal from the gap, only when it relates to the proportion enough hours, its influence of revealing the electromagnetic wave can be ignored. Therefore, the smaller the metal posts are, the closer the spacing is, the closer the electromagnetic field bound between the two rows of metal posts is to the field distribution in the metal cavity, respectively, and the relationship between the three parameters is: p/d is less than 2, d/a is less than 0.2.
In addition, the rf chip is bonded to the silicon substrate by conductive glue, and then high temperature curing is required. And the bonding mode adopts gold wire ball bonding or gold wire wedge bonding, the highest point of the bonding wire cannot contact the metal layer of the silicon cap, and a gap of 10-300 mu m is required to be reserved.
And welding the silicon cap and the silicon substrate by adopting tin paste, and coating the tin paste by using a printing screen plate, wherein the thickness of the tin paste is 5-300 mu m.
The main component of the filling material is epoxy resin, and the filling material ensures that the pouring sealant does not contact the chip and the bonding wires during pouring.
In conclusion, in the method, the silicon cap is manufactured by adopting a packaging processing technology, and can be processed together with the silicon substrate in the same way as the silicon substrate manufacturing technology, so that the processing period is shortened, the processing precision is improved, and the processing of the small-size cavity cap can be realized. The mode can realize integrated manufacturing, the process integration level is higher, the metal cavity is formed by the wiring layer and the metal welding columns, the electromagnetic wave shielding effect can be effectively realized, and in multi-chip radio frequency micro-system packaging, signal isolation among chips with different functions can be effectively realized.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
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| CN202111093457.8A CN113809049A (en) | 2021-09-17 | 2021-09-17 | Radio frequency chip packaging structure with high shielding performance and isolation and packaging method |
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| CN202111093457.8A CN113809049A (en) | 2021-09-17 | 2021-09-17 | Radio frequency chip packaging structure with high shielding performance and isolation and packaging method |
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Cited By (2)
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| CN114373741A (en) * | 2022-03-08 | 2022-04-19 | 荣耀终端有限公司 | Module, die, wafer and manufacturing method of die |
| CN115426797A (en) * | 2022-07-27 | 2022-12-02 | 成都汉芯国科集成技术有限公司 | Surface-mounted low-cost high-power radio frequency switch and manufacturing method thereof |
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| CN115426797A (en) * | 2022-07-27 | 2022-12-02 | 成都汉芯国科集成技术有限公司 | Surface-mounted low-cost high-power radio frequency switch and manufacturing method thereof |
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